Lines Matching +full:micro +full:- +full:tlb

44 .Bl -tag -width "Li PMC_CLASS_IAP"
46 Fixed-function counters that count only one hardware event per counter.
58 .%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual"
60 .%N "Order Number: 253669-043US"
69 .Bl -column "PMC_CAP_INTERRUPT" "Support"
86 .Bl -tag -width indent
88 Configure the Off-core Response bits.
89 .Bl -tag -width indent
126 M-state initial lookup stat in L3.
128 E-state.
130 S-state.
132 F-state.
136 No details on snoop-related information.
146 Hit denotes a cache-line was valid before snoop effect.
157 A snoop was needed and it HitM-ed in local or remote cache.
158 HitM denotes a cache-line was in modified state before effect as a results of snoop.
164 Target was non-DRAM system address.
172 Configure the PMC to count the number of de-asserted to asserted
199 .Bl -tag -width indent
205 Speculative cache-line split load uops dispatched to L1D.
208 Speculative cache-line split Store- address uops dispatched to L1D.
214 Misses in all TLB levels that cause a page walk of any page size from demand loads.
217 Misses in all TLB levels that caused page walk completed of any size by demand loads.
228 Number of flags-merge uops allocated.
320 Miss in all TLB levels causes an page walk of any page size (4K/2M/4M/1G).
323 Miss in all TLB levels causes a page walk that completes of any page size
330 Store operations that miss the first TLB level but hit the second and do not
334 Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch.
337 Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch.
516 Count number of non-delivered uops to RAT per thread.
560 Cycles stalled due to re-order buffer full.
588 Counts total number of uops to be executed per-thread each cycle.
592 Counts total number of uops to be executed per-core each cycle.
596 Off-core Response Performance Monitoring.
601 Off-core Response Performance Monitoring.
606 DTLB flush attempts of the thread- specific entries.
621 Number of assists associated with 256-bit AVX store operations.
624 Number of transitions from AVX- 256 to legacy SSE when penalty applicable.
627 Number of transitions from SSE to AVX-256 when penalty applicable.
630 Counts the number of micro-ops retired, Use cmask=1 and invert to count
641 Number of self-modifying-code machine clears detected.
751 Retired load uops which data sources were LLC hit and cross-core snoop
752 missed in on-pkg core cache.
756 Retired load uops which data sources were LLC and cross-core snoop hits in
757 on-pkg core cache.
850 .An -nosplit