Lines Matching +full:micro +full:- +full:tlb

50 .%B IA-32 Intel\(rg Architecture Software Developer's Manual
52 .%N Order Number 253669-027US
63 .Bl -column "PMC_CAP_INTERRUPT" "Support"
80 .Bl -tag -width indent
86 Configure the PMC to count the number of de-asserted to asserted
112 Events that require core-specificity to be specified use a
118 .Bl -tag -width indent -compact
133 .Bl -tag -width indent -compact
148 .Bl -tag -width "exclude" -compact
165 .Bl -tag -width indent -compact
183 .Bl -tag -width indent
346 The number of completed read-for-ownership transactions.
349 The number of completed write-back transactions from the data cache
350 unit, excluding L2 write-backs.
394 un-cacheable.
409 The number of data references that missed the TLB.
419 .Bl -tag -width indent -compact
461 streaming buffers counting both cacheable and un-cacheable fetches.
471 The number of instruction TLB misses.
589 The number of non-halted bus cycles.
633 The number of SSE2 128-bit integer instructions retired.
657 The number of times self-modifying code was detected.
699 The number of non-halted bus cycles of this code while the other core
714 The number of micro-ops retired.
717 The following table shows the mapping between the PMC-independent
721 .Bl -column "branch-mispredicts" "Description"
724 .It Li branch-mispredicts Ta Li Br_MisPred_Ret
725 .It Li dc-misses Ta (unsupported)
726 .It Li ic-misses Ta Li ICache_Misses
729 .It Li unhalted-cycles Ta (unsupported)
738 .%N Order Number 309222-017
742 .Bl -tag -width indent -compact