Lines Matching +full:micro +full:- +full:tlb

44 .Bl -tag -width "Li PMC_CLASS_IAP"
46 Fixed-function counters that count only one hardware event per counter.
58 .%B "Intel(R) 64 and IA-32 Architectures Software Developes Manual"
60 .%N "Order Number: 253669-033US"
69 .Bl -column "PMC_CAP_INTERRUPT" "Support"
86 .Bl -tag -width indent
88 Configure the Off-core Response bits.
89 .Bl -tag -width indent
114 I/O, full or partial writes, WC or non-temporal stores, CLFLUSH, Fences,
138 Non-DRAM requests that were serviced by IOH.
145 Configure the PMC to count the number of de-asserted to asserted
172 .Bl -tag -width indent
184 Counts number of loads delayed with at-Retirement block code.
214 Counts the number of instructions with an architecturally-visible store
219 Counts the number of instructions with an architecturally-visible store
232 Counts both primary and secondary misses to the TLB
262 Load instructions retired remote DRAM and remote home-remote cache HITM
325 from the one-cycle delayed staging latch before it is written into the LB.
367 decode enough instructions per cycle to sustain the 4-wide pipeline.
564 sizes and other implementation-specific characteristics; value comparison to
566 See Table A-1.
571 and other implementation-specific characteristics; value comparison to
573 See Table A-1.
580 see Table A-1
584 see Table A-1
786 This includes only instructions and not micro-op branches.
810 Counts mispredicted non-indirect near calls executed, (should always be 0).
861 Counts the cycles of stall due to re- order buffer full.
865 floating-point unit (FPU) control word.
877 Counts the number of instructions decoded that are macro-fused but not
893 Counts the number of micro-ops delivered by loop stream detector
952 issued on ports 0-4.
971 Counts number of cycles the SQ is full to handle off-core requests.
998 see Section 30.6.1.3, Off-core Response Performance Monitoring in the
1015 see Section 30.6.1.3, Off-core Response Performance Monitoring in the
1020 See Table A-1
1031 sub-operations of complex floating point instructions like transcendental
1038 Counts the number of micro-ops retired, (macro-fused=1, micro- fused=2,
1040 Most instructions are composed of one or two micro-ops.
1050 Counts number of macro-fused uops retired.
1060 Self-modifying code causes a sever penalty in all Intel 64 and IA-32
1065 See Table A-1.
1077 See Table A-1.
1089 Counts SIMD packed single-precision floating point Uops retired.
1092 Counts SIMD calar single-precision floating point Uops retired.
1095 Counts SIMD packed double- precision floating point Uops retired.
1098 Counts SIMD scalar double-precision floating point Uops retired.
1101 Counts 128-bit SIMD vector integer Uops retired.
1137 Counts both primary and secondary misses to the TLB.
1140 Counts the first floating-point instruction following any MMX instruction.
1142 floating-point and MMX technology states.
1145 Counts the first MMX instruction following a floating-point instruction.
1147 floating-point and MMX technology states.
1153 floating-point and MMX technology states.
1195 not allow new micro-ops to enter the out-of-order pipeline.
1198 and prevent the stalled micro-ops from entering the pipe.
1200 micro-ops retry entering the execution pipe in the next cycle and the
1201 ROB-read port stall is counted again.
1210 read port stalls occurred, which did not allow new micro-ops to enter the
1213 flag stalls occurred Cycles floating-point unit (FPU) status word stalls
1224 the front- end of the pipeline until the renamed segment retires.
1332 micro-code assist intervention.
1340 Counts number of floating point micro-code assist when the output value
1344 Counts number of floating point micro-code assist when the input value (one