Lines Matching +full:micro +full:- +full:tlb

44 .Bl -tag -width "Li PMC_CLASS_IAP"
46 Fixed-function counters that count only one hardware event per counter.
58 .%B "Intel(R) 64 and IA-32 Architectures Software Developes Manual"
60 .%N "Order Number: 253669-033US"
67 Not all CPUs in this family implement fixed-function counters.
70 .Bl -column "PMC_CAP_INTERRUPT" "Support"
87 .Bl -tag -width indent
89 Configure the Off-core Response bits.
90 .Bl -tag -width indent
113 I/O, full or partial writes, WC or non-temporal stores, CLFLUSH, Fences,
137 Non-DRAM requests that were serviced by IOH.
144 Configure the PMC to count the number of de-asserted to asserted
171 .Bl -tag -width indent
177 Counts number of loads delayed with at-Retirement block code.
206 Counts the number of instructions with an architecturally-visible store
211 Counts the number of instructions with an architecturally-visible store
224 Counts both primary and secondary misses to the TLB
328 one-cycle delayed staging latch before it is written into the LB.
368 decode enough instructions per cycle to sustain the 4-wide pipeline.
556 due to a L2 hardware-prefetch.
557 Because cache hierarchy, cache sizes and other implementation-specific
559 see Table A-1
565 line fills due to L2 hardware-prefetches.
566 Because cache hierarchy, cache sizes and other implementation-specific
568 see Table A-1
574 see Table A-1
578 see Table A-1
647 The event does not include non- memory accesses, such as I/O accesses.
662 Counts the number of DTLB first level misses that hit in the second level TLB.
819 This includes only instructions and not micro-op branches.
843 Counts mispredicted non-indirect near calls executed, (should always be 0).
891 Counts the cycles of stall due to re- order buffer full.
895 floating-point unit (FPU) control word.
907 Counts the number of instructions decoded that are macro-fused but not
922 Counts the number of micro-ops delivered by loop stream detector
958 Invert=1 to count P0-4 stalled cycles Use Cmask=1, Edge=1, Invert=1 to count
959 P0-4 stalls.
966 Use Cmask=1 for active cycles; Cmask=0 for weighted cycles; Use CMask=1, Invert=1 to count P0-4 sta…
967 cycles Use Cmask=1, Edge=1, Invert=1 to count P0-4 stalls.
977 Counts number of cycles the SQ is full to handle off-core requests.
980 see Section 30.6.1.3, Off-core Response Performance Monitoring in the
997 see Section 30.6.1.3, Off-core Response Performance Monitoring in the
1002 See Table A-1
1016 sub-operations of complex floating point instructions like transcendental
1020 Counts the number of micro-ops retired, (macro-fused=1, micro- fused=2,
1022 Most instructions are composed of one or two micro-ops.
1031 Counts number of macro-fused uops retired.
1041 Self-modifying code causes a sever penalty in all Intel 64 and IA-32
1046 See Table A-1
1058 See Table A-1
1064 Counts SIMD packed single-precision floating point Uops retired.
1067 Counts SIMD calar single-precision floating point Uops retired.
1070 Counts SIMD packed double- precision floating point Uops retired.
1073 Counts SIMD scalar double-precision floating point Uops retired.
1076 Counts 128-bit SIMD vector integer Uops retired.
1111 Counts both primary and secondary misses to the TLB.
1114 Counts the first floating-point instruction following any MMX instruction.
1116 floating-point and MMX technology states.
1119 Counts the first MMX instruction following a floating-point instruction.
1121 floating-point and MMX technology states.
1127 floating-point and MMX technology states.
1165 not allow new micro-ops to enter the out-of-order pipeline.
1167 the same cycle and prevent the stalled micro-ops from entering the pipe.
1168 In such a case, micro-ops retry entering the execution pipe in the next
1169 cycle and the ROB-read port stall is counted again.
1178 read port stalls occurred, which did not allow new micro-ops to enter the
1181 Cycles floating-point unit (FPU) status word stalls occurred.
1190 segment occurs, a stall occurs in the front-end of the pipeline until the
1292 micro-code assist intervention.
1300 Counts number of floating point micro-code assist when the output value
1304 Counts number of floating point micro-code assist when the input value (one
1331 .Bl -tag -width indent
1398 Counts micro-ops decoded by decoder 0.
1422 Counts number of SSE NTA prefetch/weakly-ordered instructions which missed
1434 systems while the guest operating systems use the standard TLB caches.
1478 Counts the number of ITLB misses that hit in the second level TLB.
1533 Counts number of TPR writes one or two micro-ops.
1537 Counts the number of macro-fusion assists
1538 Counts SIMD packed single- precision floating point Uops retired.