Lines Matching +full:micro +full:- +full:tlb

44 .Bl -tag -width "Li PMC_CLASS_IAP"
46 Fixed-function counters that count only one hardware event per counter.
58 .%B "IA-32 Intel(R) Architecture Software Developer's Manual"
60 .%N "Order Number 253669-027US"
67 Not all CPUs in this family implement fixed-function counters.
70 .Bl -column "PMC_CAP_INTERRUPT" "Support"
87 .Bl -tag -width indent
93 Configure the PMC to count the number of de-asserted to asserted
119 Events that require core-specificity to be specified use a
125 .Bl -tag -width indent
141 .Bl -tag -width indent
157 .Bl -tag -width "exclude"
175 .Bl -tag -width indent
197 .Bl -tag -width indent
213 .Bl -tag -width indent
223 .Bl -tag -width indent
438 The number explicit write-back bus transactions due to dirty line
485 was generated by a non-SIMD execution unit.
492 The number of Data TLB misses, including misses that result from
499 The number of Data TLB misses due to load operations.
502 The number of Data TLB misses due to store operations.
533 The number of floating point computational micro-ops executed.
860 The number of micro-ops dispatched for execution.
863 The number of cycles micro-ops were dispatched for execution on port
867 The number of cycles micro-ops were dispatched for execution on port
871 The number of cycles micro-ops were dispatched for execution on port
875 The number of cycles micro-ops were dispatched for execution on port
879 The number of cycles micro-ops were dispatched for execution on port
883 The number of cycles micro-ops were dispatched for execution on port
983 The number of SIMD saturated arithmetic micro-ops executed.
986 The number of SIMD micro-ops executed.
989 The number of SIMD packed arithmetic micro-ops executed.
992 The number of SIMD packed logical micro-ops executed.
995 The number of SIMD packed multiply micro-ops executed.
998 The number of SIMD pack micro-ops executed.
1001 The number of SIMD packed shift micro-ops executed.
1004 The number of SIMD unpack micro-ops executed.
1028 The number of times SSE non-temporal store instructions were executed.
1057 The number of micro-ops retired that fused a load with another
1061 The number of store address calculations that fused into one micro-op.
1065 micro-op.
1068 The number of fused micro-ops retired.
1071 The number of non-fused micro-ops retired.
1074 The number of micro-ops retired.
1085 The following table shows the mapping between the PMC-independent
1089 .Bl -column "branch-mispredicts" "cpu_clk_unhalted.core_p" "PMC Class"
1092 .It Li branch-mispredicts Ta Li BR_INST_RETIRED.MISPRED Ta Li PMC_CLASS_IAP
1093 .It Li ic-misses Ta Li L1I_MISSES Ta Li PMC_CLASS_IAP
1096 .It Li unhalted-cycles Ta Li CPU_CLK_UNHALTED.CORE_P Ta Li PMC_CLASS_IAF