Lines Matching +full:micro +full:- +full:tlb

42         "BriefDescription": "Speculative and retired macro-conditional branches.",
51 …"BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indi…
87         "BriefDescription": "Not taken macro-conditional branches.",
96         "BriefDescription": "Taken speculative and retired macro-conditional branches.",
105 …"BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding…
158         "BriefDescription": "All (macro) branch instructions retired. (Precise Event - PEBS).",
324 …     "BriefDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS).",
330 …     "PublicDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS)",
476 …miss-pending demand load this thread, increment by 1. Note this is in DCU and connected to Umask 1…
486 …"BriefDescription": "Each cycle there was a MLC-miss pending demand load this thread (i.e. Non-com…
506 …-pending demand load this thread and no uops dispatched, increment by 1. Note this is in DCU and c…
516 …scription": "Each cycle there was a MLC-miss pending demand load and no uops dispatched on this th…
548 …n. For instructions that consist of multiple micro-ops, this event counts the retirement of the la…
553 …    "BriefDescription": "Number of instructions retired. General Counter   - architectural event.",
561         "BriefDescription": "Instructions retired. (Precise Event - PEBS).",
613 …up with a valid block-code written to the load buffer (including blocks due to Memory Order Buffer…
640 …"BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwa…
645 …tore.  See the table of not supported store forwards in the Intel? 64 and IA-32 Architectures Opti…
669 …"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware pref…
678 …"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software pref…
732 …"PublicDescription": "Maskmov false fault - counts number of time ucode passes through Maskmov flo…
737         "BriefDescription": "Self-modifying code (SMC) detected.",
742 …"PublicDescription": "This event is incremented when self-modifying code (SMC) is detected, which …
756         "BriefDescription": "Increments the number of flags-merge uops in flight each cycle.",
765 …      "BriefDescription": "Performance sensitive flags-merging uops added by Sandy Bridge u-arch.",
771 …cuting performance-sensitive flags-merging uops. For example, shift CL (merge_arith_flags). For mo…
790 … where base is EBR/RBP/R13, using RIP relative or 16-bit addressing modes. See the Intel? 64 and I…
795         "BriefDescription": "Resource-related stall cycles.",
840         "BriefDescription": "Cycles stalled due to re-order buffer full.",
1065 …    "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
1075 …    "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
1085 …    "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
1095 …    "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
1105         "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.",
1120 …": "This event counts the number of Uops issued by the front-end of the pipeilne to the back-end.",
1154         "PublicDescription": "This event counts the number of micro-ops retired.",
1176 …h cycle - meaning, 4 micro-ops or 4 instructions could retire each cycle.  This event is used in d…