| ea608a01 | 09-Oct-2023 |
Sumit Gupta <sumitg@nvidia.com> |
firmware: tegra: Add suspend hook and reset BPMP IPC early on resume
Add suspend hook and a 'suspended' field in the 'struct tegra_bpmp' to mark if BPMP is suspended. Also, add a 'flags' field in th
firmware: tegra: Add suspend hook and reset BPMP IPC early on resume
Add suspend hook and a 'suspended' field in the 'struct tegra_bpmp' to mark if BPMP is suspended. Also, add a 'flags' field in the 'struct tegra_bpmp_message' whose 'TEGRA_BPMP_MESSAGE_RESET' bit can be set from the Tegra MC driver to signal that the reset of BPMP IPC channels is required before sending MRQ to the BPMP FW. Together both the fields allow us to handle any requests that might be sent too soon as they can cause hang during system resume.
One case where we see BPMP requests being sent before the BPMP driver has resumed is the memory bandwidth requests which are triggered by onlining the CPUs during system resume. The CPUs are onlined before the BPMP has resumed and we need to reset the BPMP IPC channels to handle these requests.
The additional check for 'flags' is done to avoid any un-intended BPMP IPC reset if the tegra_bpmp_transfer*() API gets called during suspend sequence after the BPMP driver is suspended.
Fixes: f41e1442ac5b ("cpufreq: tegra194: add OPP support and set bandwidth") Co-developed-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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| e852af72 | 11-May-2023 |
Sumit Gupta <sumitg@nvidia.com> |
memory: tegra: Make CPU cluster BW request a multiple of MC channels
Make CPU cluster's bandwidth (BW) request a multiple of MC channels. CPU OPP tables have BW info per MC channel. But, the actual
memory: tegra: Make CPU cluster BW request a multiple of MC channels
Make CPU cluster's bandwidth (BW) request a multiple of MC channels. CPU OPP tables have BW info per MC channel. But, the actual BW depends on the number of MC channels which can change as per the boot config. Get the number of MC channels which are actually enabled in current boot configuration and multiply the BW request from a CPU cluster with the number of enabled MC channels. This is not required to be done for other MC clients.
Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
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| b76bd1b3 | 22-Sep-2022 |
Manish Bhardwaj <mbhardwaj@nvidia.com> |
firmware: tegra: include IVC header file only once
Add the necessary definition to prevent compilation errors from the ivc.h file being included multiple times. This does not currently cause any com
firmware: tegra: include IVC header file only once
Add the necessary definition to prevent compilation errors from the ivc.h file being included multiple times. This does not currently cause any compilation issues, but fix this anyway.
Signed-off-by: Manish Bhardwaj <mbhardwaj@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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| bebf683b | 09-Nov-2022 |
Kartik <kkartik@nvidia.com> |
soc/tegra: fuse: Use platform info with SoC revision
Tegra pre-silicon platforms do not have chip revisions. This makes the revision SoC attribute meaningless on these platforms.
Instead, populate
soc/tegra: fuse: Use platform info with SoC revision
Tegra pre-silicon platforms do not have chip revisions. This makes the revision SoC attribute meaningless on these platforms.
Instead, populate the revision SoC attribute with a combination of the platform name and the chip revision for silicon platforms, and simply with the platform name on pre-silicon platforms.
Signed-off-by: Kartik <kkartik@nvidia.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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| b7134422 | 11-May-2022 |
Sumit Gupta <sumitg@nvidia.com> |
soc/tegra: cbb: Add CBB 1.0 driver for Tegra194
Adding driver to handle errors from Control Backbone (CBB) which are generated due to illegal accesses. CBB 1.0 is used in Tegra194 SoCs. When an erro
soc/tegra: cbb: Add CBB 1.0 driver for Tegra194
Adding driver to handle errors from Control Backbone (CBB) which are generated due to illegal accesses. CBB 1.0 is used in Tegra194 SoCs. When an error is reported from a NOC within CBB, the driver prints debug information about failed transaction like Error Code, Error Description, Master, Address, AXI ID, Cache, Protection, Security Group etc. It then causes system crash using BUG_ON() or call WARN() based on whether the error type is fatal or not.
Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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