1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2017-2021 NVIDIA CORPORATION. All rights reserved. 4 */ 5 6 #include <linux/io.h> 7 #include <linux/iommu.h> 8 #include <linux/module.h> 9 #include <linux/mod_devicetable.h> 10 #include <linux/of.h> 11 #include <linux/of_platform.h> 12 #include <linux/platform_device.h> 13 14 #include <soc/tegra/mc.h> 15 16 #if defined(CONFIG_ARCH_TEGRA_186_SOC) 17 #include <dt-bindings/memory/tegra186-mc.h> 18 #endif 19 20 #include "mc.h" 21 22 #define MC_SID_STREAMID_OVERRIDE_MASK GENMASK(7, 0) 23 #define MC_SID_STREAMID_SECURITY_WRITE_ACCESS_DISABLED BIT(16) 24 #define MC_SID_STREAMID_SECURITY_OVERRIDE BIT(8) 25 26 static int tegra186_mc_probe(struct tegra_mc *mc) 27 { 28 struct platform_device *pdev = to_platform_device(mc->dev); 29 unsigned int i; 30 char name[8]; 31 int err; 32 33 mc->bcast_ch_regs = devm_platform_ioremap_resource_byname(pdev, "broadcast"); 34 if (IS_ERR(mc->bcast_ch_regs)) { 35 if (PTR_ERR(mc->bcast_ch_regs) == -EINVAL) { 36 dev_warn(&pdev->dev, 37 "Broadcast channel is missing, please update your device-tree\n"); 38 mc->bcast_ch_regs = NULL; 39 goto populate; 40 } 41 42 return PTR_ERR(mc->bcast_ch_regs); 43 } 44 45 mc->ch_regs = devm_kcalloc(mc->dev, mc->soc->num_channels, sizeof(*mc->ch_regs), 46 GFP_KERNEL); 47 if (!mc->ch_regs) 48 return -ENOMEM; 49 50 for (i = 0; i < mc->soc->num_channels; i++) { 51 snprintf(name, sizeof(name), "ch%u", i); 52 53 mc->ch_regs[i] = devm_platform_ioremap_resource_byname(pdev, name); 54 if (IS_ERR(mc->ch_regs[i])) 55 return PTR_ERR(mc->ch_regs[i]); 56 } 57 58 populate: 59 err = of_platform_populate(mc->dev->of_node, NULL, NULL, mc->dev); 60 if (err < 0) 61 return err; 62 63 return 0; 64 } 65 66 static void tegra186_mc_remove(struct tegra_mc *mc) 67 { 68 of_platform_depopulate(mc->dev); 69 } 70 71 #if IS_ENABLED(CONFIG_IOMMU_API) 72 static void tegra186_mc_client_sid_override(struct tegra_mc *mc, 73 const struct tegra_mc_client *client, 74 unsigned int sid) 75 { 76 u32 value, old; 77 78 value = readl(mc->regs + client->regs.sid.security); 79 if ((value & MC_SID_STREAMID_SECURITY_OVERRIDE) == 0) { 80 /* 81 * If the secure firmware has locked this down the override 82 * for this memory client, there's nothing we can do here. 83 */ 84 if (value & MC_SID_STREAMID_SECURITY_WRITE_ACCESS_DISABLED) 85 return; 86 87 /* 88 * Otherwise, try to set the override itself. Typically the 89 * secure firmware will never have set this configuration. 90 * Instead, it will either have disabled write access to 91 * this field, or it will already have set an explicit 92 * override itself. 93 */ 94 WARN_ON((value & MC_SID_STREAMID_SECURITY_OVERRIDE) == 0); 95 96 value |= MC_SID_STREAMID_SECURITY_OVERRIDE; 97 writel(value, mc->regs + client->regs.sid.security); 98 } 99 100 value = readl(mc->regs + client->regs.sid.override); 101 old = value & MC_SID_STREAMID_OVERRIDE_MASK; 102 103 if (old != sid) { 104 dev_dbg(mc->dev, "overriding SID %x for %s with %x\n", old, 105 client->name, sid); 106 writel(sid, mc->regs + client->regs.sid.override); 107 } 108 } 109 #endif 110 111 static int tegra186_mc_probe_device(struct tegra_mc *mc, struct device *dev) 112 { 113 #if IS_ENABLED(CONFIG_IOMMU_API) 114 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 115 struct of_phandle_args args; 116 unsigned int i, index = 0; 117 118 while (!of_parse_phandle_with_args(dev->of_node, "interconnects", "#interconnect-cells", 119 index, &args)) { 120 if (args.np == mc->dev->of_node && args.args_count != 0) { 121 for (i = 0; i < mc->soc->num_clients; i++) { 122 const struct tegra_mc_client *client = &mc->soc->clients[i]; 123 124 if (client->id == args.args[0]) { 125 u32 sid = fwspec->ids[0] & MC_SID_STREAMID_OVERRIDE_MASK; 126 127 tegra186_mc_client_sid_override(mc, client, sid); 128 } 129 } 130 } 131 132 index++; 133 } 134 #endif 135 136 return 0; 137 } 138 139 static int tegra186_mc_resume(struct tegra_mc *mc) 140 { 141 unsigned int i; 142 143 for (i = 0; i < mc->soc->num_clients; i++) { 144 const struct tegra_mc_client *client = &mc->soc->clients[i]; 145 146 tegra186_mc_client_sid_override(mc, client, client->sid); 147 } 148 149 return 0; 150 } 151 152 const struct tegra_mc_ops tegra186_mc_ops = { 153 .probe = tegra186_mc_probe, 154 .remove = tegra186_mc_remove, 155 .resume = tegra186_mc_resume, 156 .probe_device = tegra186_mc_probe_device, 157 .handle_irq = tegra30_mc_handle_irq, 158 }; 159 160 #if defined(CONFIG_ARCH_TEGRA_186_SOC) 161 static const struct tegra_mc_client tegra186_mc_clients[] = { 162 { 163 .id = TEGRA186_MEMORY_CLIENT_PTCR, 164 .name = "ptcr", 165 .sid = TEGRA186_SID_PASSTHROUGH, 166 .regs = { 167 .sid = { 168 .override = 0x000, 169 .security = 0x004, 170 }, 171 }, 172 }, { 173 .id = TEGRA186_MEMORY_CLIENT_AFIR, 174 .name = "afir", 175 .sid = TEGRA186_SID_AFI, 176 .regs = { 177 .sid = { 178 .override = 0x070, 179 .security = 0x074, 180 }, 181 }, 182 }, { 183 .id = TEGRA186_MEMORY_CLIENT_HDAR, 184 .name = "hdar", 185 .sid = TEGRA186_SID_HDA, 186 .regs = { 187 .sid = { 188 .override = 0x0a8, 189 .security = 0x0ac, 190 }, 191 }, 192 }, { 193 .id = TEGRA186_MEMORY_CLIENT_HOST1XDMAR, 194 .name = "host1xdmar", 195 .sid = TEGRA186_SID_HOST1X, 196 .regs = { 197 .sid = { 198 .override = 0x0b0, 199 .security = 0x0b4, 200 }, 201 }, 202 }, { 203 .id = TEGRA186_MEMORY_CLIENT_NVENCSRD, 204 .name = "nvencsrd", 205 .sid = TEGRA186_SID_NVENC, 206 .regs = { 207 .sid = { 208 .override = 0x0e0, 209 .security = 0x0e4, 210 }, 211 }, 212 }, { 213 .id = TEGRA186_MEMORY_CLIENT_SATAR, 214 .name = "satar", 215 .sid = TEGRA186_SID_SATA, 216 .regs = { 217 .sid = { 218 .override = 0x0f8, 219 .security = 0x0fc, 220 }, 221 }, 222 }, { 223 .id = TEGRA186_MEMORY_CLIENT_MPCORER, 224 .name = "mpcorer", 225 .sid = TEGRA186_SID_PASSTHROUGH, 226 .regs = { 227 .sid = { 228 .override = 0x138, 229 .security = 0x13c, 230 }, 231 }, 232 }, { 233 .id = TEGRA186_MEMORY_CLIENT_NVENCSWR, 234 .name = "nvencswr", 235 .sid = TEGRA186_SID_NVENC, 236 .regs = { 237 .sid = { 238 .override = 0x158, 239 .security = 0x15c, 240 }, 241 }, 242 }, { 243 .id = TEGRA186_MEMORY_CLIENT_AFIW, 244 .name = "afiw", 245 .sid = TEGRA186_SID_AFI, 246 .regs = { 247 .sid = { 248 .override = 0x188, 249 .security = 0x18c, 250 }, 251 }, 252 }, { 253 .id = TEGRA186_MEMORY_CLIENT_HDAW, 254 .name = "hdaw", 255 .sid = TEGRA186_SID_HDA, 256 .regs = { 257 .sid = { 258 .override = 0x1a8, 259 .security = 0x1ac, 260 }, 261 }, 262 }, { 263 .id = TEGRA186_MEMORY_CLIENT_MPCOREW, 264 .name = "mpcorew", 265 .sid = TEGRA186_SID_PASSTHROUGH, 266 .regs = { 267 .sid = { 268 .override = 0x1c8, 269 .security = 0x1cc, 270 }, 271 }, 272 }, { 273 .id = TEGRA186_MEMORY_CLIENT_SATAW, 274 .name = "sataw", 275 .sid = TEGRA186_SID_SATA, 276 .regs = { 277 .sid = { 278 .override = 0x1e8, 279 .security = 0x1ec, 280 }, 281 }, 282 }, { 283 .id = TEGRA186_MEMORY_CLIENT_ISPRA, 284 .name = "ispra", 285 .sid = TEGRA186_SID_ISP, 286 .regs = { 287 .sid = { 288 .override = 0x220, 289 .security = 0x224, 290 }, 291 }, 292 }, { 293 .id = TEGRA186_MEMORY_CLIENT_ISPWA, 294 .name = "ispwa", 295 .sid = TEGRA186_SID_ISP, 296 .regs = { 297 .sid = { 298 .override = 0x230, 299 .security = 0x234, 300 }, 301 }, 302 }, { 303 .id = TEGRA186_MEMORY_CLIENT_ISPWB, 304 .name = "ispwb", 305 .sid = TEGRA186_SID_ISP, 306 .regs = { 307 .sid = { 308 .override = 0x238, 309 .security = 0x23c, 310 }, 311 }, 312 }, { 313 .id = TEGRA186_MEMORY_CLIENT_XUSB_HOSTR, 314 .name = "xusb_hostr", 315 .sid = TEGRA186_SID_XUSB_HOST, 316 .regs = { 317 .sid = { 318 .override = 0x250, 319 .security = 0x254, 320 }, 321 }, 322 }, { 323 .id = TEGRA186_MEMORY_CLIENT_XUSB_HOSTW, 324 .name = "xusb_hostw", 325 .sid = TEGRA186_SID_XUSB_HOST, 326 .regs = { 327 .sid = { 328 .override = 0x258, 329 .security = 0x25c, 330 }, 331 }, 332 }, { 333 .id = TEGRA186_MEMORY_CLIENT_XUSB_DEVR, 334 .name = "xusb_devr", 335 .sid = TEGRA186_SID_XUSB_DEV, 336 .regs = { 337 .sid = { 338 .override = 0x260, 339 .security = 0x264, 340 }, 341 }, 342 }, { 343 .id = TEGRA186_MEMORY_CLIENT_XUSB_DEVW, 344 .name = "xusb_devw", 345 .sid = TEGRA186_SID_XUSB_DEV, 346 .regs = { 347 .sid = { 348 .override = 0x268, 349 .security = 0x26c, 350 }, 351 }, 352 }, { 353 .id = TEGRA186_MEMORY_CLIENT_TSECSRD, 354 .name = "tsecsrd", 355 .sid = TEGRA186_SID_TSEC, 356 .regs = { 357 .sid = { 358 .override = 0x2a0, 359 .security = 0x2a4, 360 }, 361 }, 362 }, { 363 .id = TEGRA186_MEMORY_CLIENT_TSECSWR, 364 .name = "tsecswr", 365 .sid = TEGRA186_SID_TSEC, 366 .regs = { 367 .sid = { 368 .override = 0x2a8, 369 .security = 0x2ac, 370 }, 371 }, 372 }, { 373 .id = TEGRA186_MEMORY_CLIENT_GPUSRD, 374 .name = "gpusrd", 375 .sid = TEGRA186_SID_GPU, 376 .regs = { 377 .sid = { 378 .override = 0x2c0, 379 .security = 0x2c4, 380 }, 381 }, 382 }, { 383 .id = TEGRA186_MEMORY_CLIENT_GPUSWR, 384 .name = "gpuswr", 385 .sid = TEGRA186_SID_GPU, 386 .regs = { 387 .sid = { 388 .override = 0x2c8, 389 .security = 0x2cc, 390 }, 391 }, 392 }, { 393 .id = TEGRA186_MEMORY_CLIENT_SDMMCRA, 394 .name = "sdmmcra", 395 .sid = TEGRA186_SID_SDMMC1, 396 .regs = { 397 .sid = { 398 .override = 0x300, 399 .security = 0x304, 400 }, 401 }, 402 }, { 403 .id = TEGRA186_MEMORY_CLIENT_SDMMCRAA, 404 .name = "sdmmcraa", 405 .sid = TEGRA186_SID_SDMMC2, 406 .regs = { 407 .sid = { 408 .override = 0x308, 409 .security = 0x30c, 410 }, 411 }, 412 }, { 413 .id = TEGRA186_MEMORY_CLIENT_SDMMCR, 414 .name = "sdmmcr", 415 .sid = TEGRA186_SID_SDMMC3, 416 .regs = { 417 .sid = { 418 .override = 0x310, 419 .security = 0x314, 420 }, 421 }, 422 }, { 423 .id = TEGRA186_MEMORY_CLIENT_SDMMCRAB, 424 .name = "sdmmcrab", 425 .sid = TEGRA186_SID_SDMMC4, 426 .regs = { 427 .sid = { 428 .override = 0x318, 429 .security = 0x31c, 430 }, 431 }, 432 }, { 433 .id = TEGRA186_MEMORY_CLIENT_SDMMCWA, 434 .name = "sdmmcwa", 435 .sid = TEGRA186_SID_SDMMC1, 436 .regs = { 437 .sid = { 438 .override = 0x320, 439 .security = 0x324, 440 }, 441 }, 442 }, { 443 .id = TEGRA186_MEMORY_CLIENT_SDMMCWAA, 444 .name = "sdmmcwaa", 445 .sid = TEGRA186_SID_SDMMC2, 446 .regs = { 447 .sid = { 448 .override = 0x328, 449 .security = 0x32c, 450 }, 451 }, 452 }, { 453 .id = TEGRA186_MEMORY_CLIENT_SDMMCW, 454 .name = "sdmmcw", 455 .sid = TEGRA186_SID_SDMMC3, 456 .regs = { 457 .sid = { 458 .override = 0x330, 459 .security = 0x334, 460 }, 461 }, 462 }, { 463 .id = TEGRA186_MEMORY_CLIENT_SDMMCWAB, 464 .name = "sdmmcwab", 465 .sid = TEGRA186_SID_SDMMC4, 466 .regs = { 467 .sid = { 468 .override = 0x338, 469 .security = 0x33c, 470 }, 471 }, 472 }, { 473 .id = TEGRA186_MEMORY_CLIENT_VICSRD, 474 .name = "vicsrd", 475 .sid = TEGRA186_SID_VIC, 476 .regs = { 477 .sid = { 478 .override = 0x360, 479 .security = 0x364, 480 }, 481 }, 482 }, { 483 .id = TEGRA186_MEMORY_CLIENT_VICSWR, 484 .name = "vicswr", 485 .sid = TEGRA186_SID_VIC, 486 .regs = { 487 .sid = { 488 .override = 0x368, 489 .security = 0x36c, 490 }, 491 }, 492 }, { 493 .id = TEGRA186_MEMORY_CLIENT_VIW, 494 .name = "viw", 495 .sid = TEGRA186_SID_VI, 496 .regs = { 497 .sid = { 498 .override = 0x390, 499 .security = 0x394, 500 }, 501 }, 502 }, { 503 .id = TEGRA186_MEMORY_CLIENT_NVDECSRD, 504 .name = "nvdecsrd", 505 .sid = TEGRA186_SID_NVDEC, 506 .regs = { 507 .sid = { 508 .override = 0x3c0, 509 .security = 0x3c4, 510 }, 511 }, 512 }, { 513 .id = TEGRA186_MEMORY_CLIENT_NVDECSWR, 514 .name = "nvdecswr", 515 .sid = TEGRA186_SID_NVDEC, 516 .regs = { 517 .sid = { 518 .override = 0x3c8, 519 .security = 0x3cc, 520 }, 521 }, 522 }, { 523 .id = TEGRA186_MEMORY_CLIENT_APER, 524 .name = "aper", 525 .sid = TEGRA186_SID_APE, 526 .regs = { 527 .sid = { 528 .override = 0x3d0, 529 .security = 0x3d4, 530 }, 531 }, 532 }, { 533 .id = TEGRA186_MEMORY_CLIENT_APEW, 534 .name = "apew", 535 .sid = TEGRA186_SID_APE, 536 .regs = { 537 .sid = { 538 .override = 0x3d8, 539 .security = 0x3dc, 540 }, 541 }, 542 }, { 543 .id = TEGRA186_MEMORY_CLIENT_NVJPGSRD, 544 .name = "nvjpgsrd", 545 .sid = TEGRA186_SID_NVJPG, 546 .regs = { 547 .sid = { 548 .override = 0x3f0, 549 .security = 0x3f4, 550 }, 551 }, 552 }, { 553 .id = TEGRA186_MEMORY_CLIENT_NVJPGSWR, 554 .name = "nvjpgswr", 555 .sid = TEGRA186_SID_NVJPG, 556 .regs = { 557 .sid = { 558 .override = 0x3f8, 559 .security = 0x3fc, 560 }, 561 }, 562 }, { 563 .id = TEGRA186_MEMORY_CLIENT_SESRD, 564 .name = "sesrd", 565 .sid = TEGRA186_SID_SE, 566 .regs = { 567 .sid = { 568 .override = 0x400, 569 .security = 0x404, 570 }, 571 }, 572 }, { 573 .id = TEGRA186_MEMORY_CLIENT_SESWR, 574 .name = "seswr", 575 .sid = TEGRA186_SID_SE, 576 .regs = { 577 .sid = { 578 .override = 0x408, 579 .security = 0x40c, 580 }, 581 }, 582 }, { 583 .id = TEGRA186_MEMORY_CLIENT_ETRR, 584 .name = "etrr", 585 .sid = TEGRA186_SID_ETR, 586 .regs = { 587 .sid = { 588 .override = 0x420, 589 .security = 0x424, 590 }, 591 }, 592 }, { 593 .id = TEGRA186_MEMORY_CLIENT_ETRW, 594 .name = "etrw", 595 .sid = TEGRA186_SID_ETR, 596 .regs = { 597 .sid = { 598 .override = 0x428, 599 .security = 0x42c, 600 }, 601 }, 602 }, { 603 .id = TEGRA186_MEMORY_CLIENT_TSECSRDB, 604 .name = "tsecsrdb", 605 .sid = TEGRA186_SID_TSECB, 606 .regs = { 607 .sid = { 608 .override = 0x430, 609 .security = 0x434, 610 }, 611 }, 612 }, { 613 .id = TEGRA186_MEMORY_CLIENT_TSECSWRB, 614 .name = "tsecswrb", 615 .sid = TEGRA186_SID_TSECB, 616 .regs = { 617 .sid = { 618 .override = 0x438, 619 .security = 0x43c, 620 }, 621 }, 622 }, { 623 .id = TEGRA186_MEMORY_CLIENT_GPUSRD2, 624 .name = "gpusrd2", 625 .sid = TEGRA186_SID_GPU, 626 .regs = { 627 .sid = { 628 .override = 0x440, 629 .security = 0x444, 630 }, 631 }, 632 }, { 633 .id = TEGRA186_MEMORY_CLIENT_GPUSWR2, 634 .name = "gpuswr2", 635 .sid = TEGRA186_SID_GPU, 636 .regs = { 637 .sid = { 638 .override = 0x448, 639 .security = 0x44c, 640 }, 641 }, 642 }, { 643 .id = TEGRA186_MEMORY_CLIENT_AXISR, 644 .name = "axisr", 645 .sid = TEGRA186_SID_GPCDMA_0, 646 .regs = { 647 .sid = { 648 .override = 0x460, 649 .security = 0x464, 650 }, 651 }, 652 }, { 653 .id = TEGRA186_MEMORY_CLIENT_AXISW, 654 .name = "axisw", 655 .sid = TEGRA186_SID_GPCDMA_0, 656 .regs = { 657 .sid = { 658 .override = 0x468, 659 .security = 0x46c, 660 }, 661 }, 662 }, { 663 .id = TEGRA186_MEMORY_CLIENT_EQOSR, 664 .name = "eqosr", 665 .sid = TEGRA186_SID_EQOS, 666 .regs = { 667 .sid = { 668 .override = 0x470, 669 .security = 0x474, 670 }, 671 }, 672 }, { 673 .id = TEGRA186_MEMORY_CLIENT_EQOSW, 674 .name = "eqosw", 675 .sid = TEGRA186_SID_EQOS, 676 .regs = { 677 .sid = { 678 .override = 0x478, 679 .security = 0x47c, 680 }, 681 }, 682 }, { 683 .id = TEGRA186_MEMORY_CLIENT_UFSHCR, 684 .name = "ufshcr", 685 .sid = TEGRA186_SID_UFSHC, 686 .regs = { 687 .sid = { 688 .override = 0x480, 689 .security = 0x484, 690 }, 691 }, 692 }, { 693 .id = TEGRA186_MEMORY_CLIENT_UFSHCW, 694 .name = "ufshcw", 695 .sid = TEGRA186_SID_UFSHC, 696 .regs = { 697 .sid = { 698 .override = 0x488, 699 .security = 0x48c, 700 }, 701 }, 702 }, { 703 .id = TEGRA186_MEMORY_CLIENT_NVDISPLAYR, 704 .name = "nvdisplayr", 705 .sid = TEGRA186_SID_NVDISPLAY, 706 .regs = { 707 .sid = { 708 .override = 0x490, 709 .security = 0x494, 710 }, 711 }, 712 }, { 713 .id = TEGRA186_MEMORY_CLIENT_BPMPR, 714 .name = "bpmpr", 715 .sid = TEGRA186_SID_BPMP, 716 .regs = { 717 .sid = { 718 .override = 0x498, 719 .security = 0x49c, 720 }, 721 }, 722 }, { 723 .id = TEGRA186_MEMORY_CLIENT_BPMPW, 724 .name = "bpmpw", 725 .sid = TEGRA186_SID_BPMP, 726 .regs = { 727 .sid = { 728 .override = 0x4a0, 729 .security = 0x4a4, 730 }, 731 }, 732 }, { 733 .id = TEGRA186_MEMORY_CLIENT_BPMPDMAR, 734 .name = "bpmpdmar", 735 .sid = TEGRA186_SID_BPMP, 736 .regs = { 737 .sid = { 738 .override = 0x4a8, 739 .security = 0x4ac, 740 }, 741 }, 742 }, { 743 .id = TEGRA186_MEMORY_CLIENT_BPMPDMAW, 744 .name = "bpmpdmaw", 745 .sid = TEGRA186_SID_BPMP, 746 .regs = { 747 .sid = { 748 .override = 0x4b0, 749 .security = 0x4b4, 750 }, 751 }, 752 }, { 753 .id = TEGRA186_MEMORY_CLIENT_AONR, 754 .name = "aonr", 755 .sid = TEGRA186_SID_AON, 756 .regs = { 757 .sid = { 758 .override = 0x4b8, 759 .security = 0x4bc, 760 }, 761 }, 762 }, { 763 .id = TEGRA186_MEMORY_CLIENT_AONW, 764 .name = "aonw", 765 .sid = TEGRA186_SID_AON, 766 .regs = { 767 .sid = { 768 .override = 0x4c0, 769 .security = 0x4c4, 770 }, 771 }, 772 }, { 773 .id = TEGRA186_MEMORY_CLIENT_AONDMAR, 774 .name = "aondmar", 775 .sid = TEGRA186_SID_AON, 776 .regs = { 777 .sid = { 778 .override = 0x4c8, 779 .security = 0x4cc, 780 }, 781 }, 782 }, { 783 .id = TEGRA186_MEMORY_CLIENT_AONDMAW, 784 .name = "aondmaw", 785 .sid = TEGRA186_SID_AON, 786 .regs = { 787 .sid = { 788 .override = 0x4d0, 789 .security = 0x4d4, 790 }, 791 }, 792 }, { 793 .id = TEGRA186_MEMORY_CLIENT_SCER, 794 .name = "scer", 795 .sid = TEGRA186_SID_SCE, 796 .regs = { 797 .sid = { 798 .override = 0x4d8, 799 .security = 0x4dc, 800 }, 801 }, 802 }, { 803 .id = TEGRA186_MEMORY_CLIENT_SCEW, 804 .name = "scew", 805 .sid = TEGRA186_SID_SCE, 806 .regs = { 807 .sid = { 808 .override = 0x4e0, 809 .security = 0x4e4, 810 }, 811 }, 812 }, { 813 .id = TEGRA186_MEMORY_CLIENT_SCEDMAR, 814 .name = "scedmar", 815 .sid = TEGRA186_SID_SCE, 816 .regs = { 817 .sid = { 818 .override = 0x4e8, 819 .security = 0x4ec, 820 }, 821 }, 822 }, { 823 .id = TEGRA186_MEMORY_CLIENT_SCEDMAW, 824 .name = "scedmaw", 825 .sid = TEGRA186_SID_SCE, 826 .regs = { 827 .sid = { 828 .override = 0x4f0, 829 .security = 0x4f4, 830 }, 831 }, 832 }, { 833 .id = TEGRA186_MEMORY_CLIENT_APEDMAR, 834 .name = "apedmar", 835 .sid = TEGRA186_SID_APE, 836 .regs = { 837 .sid = { 838 .override = 0x4f8, 839 .security = 0x4fc, 840 }, 841 }, 842 }, { 843 .id = TEGRA186_MEMORY_CLIENT_APEDMAW, 844 .name = "apedmaw", 845 .sid = TEGRA186_SID_APE, 846 .regs = { 847 .sid = { 848 .override = 0x500, 849 .security = 0x504, 850 }, 851 }, 852 }, { 853 .id = TEGRA186_MEMORY_CLIENT_NVDISPLAYR1, 854 .name = "nvdisplayr1", 855 .sid = TEGRA186_SID_NVDISPLAY, 856 .regs = { 857 .sid = { 858 .override = 0x508, 859 .security = 0x50c, 860 }, 861 }, 862 }, { 863 .id = TEGRA186_MEMORY_CLIENT_VICSRD1, 864 .name = "vicsrd1", 865 .sid = TEGRA186_SID_VIC, 866 .regs = { 867 .sid = { 868 .override = 0x510, 869 .security = 0x514, 870 }, 871 }, 872 }, { 873 .id = TEGRA186_MEMORY_CLIENT_NVDECSRD1, 874 .name = "nvdecsrd1", 875 .sid = TEGRA186_SID_NVDEC, 876 .regs = { 877 .sid = { 878 .override = 0x518, 879 .security = 0x51c, 880 }, 881 }, 882 }, 883 }; 884 885 const struct tegra_mc_soc tegra186_mc_soc = { 886 .num_clients = ARRAY_SIZE(tegra186_mc_clients), 887 .clients = tegra186_mc_clients, 888 .num_address_bits = 40, 889 .num_channels = 4, 890 .client_id_mask = 0xff, 891 .intmask = MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS | 892 MC_INT_SECERR_SEC | MC_INT_DECERR_VPR | 893 MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM, 894 .ops = &tegra186_mc_ops, 895 .ch_intmask = 0x0000000f, 896 .global_intstatus_channel_shift = 0, 897 }; 898 #endif 899