1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * x86 SMP booting functions 4 * 5 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 6 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 7 * Copyright 2001 Andi Kleen, SuSE Labs. 8 * 9 * Much of the core SMP work is based on previous work by Thomas Radke, to 10 * whom a great many thanks are extended. 11 * 12 * Thanks to Intel for making available several different Pentium, 13 * Pentium Pro and Pentium-II/Xeon MP machines. 14 * Original development of Linux SMP code supported by Caldera. 15 * 16 * Fixes 17 * Felix Koop : NR_CPUS used properly 18 * Jose Renau : Handle single CPU case. 19 * Alan Cox : By repeated request 8) - Total BogoMIPS report. 20 * Greg Wright : Fix for kernel stacks panic. 21 * Erich Boleyn : MP v1.4 and additional changes. 22 * Matthias Sattler : Changes for 2.1 kernel map. 23 * Michel Lespinasse : Changes for 2.1 kernel map. 24 * Michael Chastain : Change trampoline.S to gnu as. 25 * Alan Cox : Dumb bug: 'B' step PPro's are fine 26 * Ingo Molnar : Added APIC timers, based on code 27 * from Jose Renau 28 * Ingo Molnar : various cleanups and rewrites 29 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. 30 * Maciej W. Rozycki : Bits for genuine 82489DX APICs 31 * Andi Kleen : Changed for SMP boot into long mode. 32 * Martin J. Bligh : Added support for multi-quad systems 33 * Dave Jones : Report invalid combinations of Athlon CPUs. 34 * Rusty Russell : Hacked into shape for new "hotplug" boot process. 35 * Andi Kleen : Converted to new state machine. 36 * Ashok Raj : CPU hotplug support 37 * Glauber Costa : i386 and x86_64 integration 38 */ 39 40 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 41 42 #include <linux/init.h> 43 #include <linux/smp.h> 44 #include <linux/export.h> 45 #include <linux/sched.h> 46 #include <linux/sched/topology.h> 47 #include <linux/sched/hotplug.h> 48 #include <linux/sched/task_stack.h> 49 #include <linux/percpu.h> 50 #include <linux/memblock.h> 51 #include <linux/err.h> 52 #include <linux/nmi.h> 53 #include <linux/tboot.h> 54 #include <linux/gfp.h> 55 #include <linux/cpuidle.h> 56 #include <linux/numa.h> 57 #include <linux/pgtable.h> 58 #include <linux/overflow.h> 59 #include <linux/stackprotector.h> 60 61 #include <asm/acpi.h> 62 #include <asm/desc.h> 63 #include <asm/nmi.h> 64 #include <asm/irq.h> 65 #include <asm/realmode.h> 66 #include <asm/cpu.h> 67 #include <asm/numa.h> 68 #include <asm/tlbflush.h> 69 #include <asm/mtrr.h> 70 #include <asm/mwait.h> 71 #include <asm/apic.h> 72 #include <asm/io_apic.h> 73 #include <asm/fpu/api.h> 74 #include <asm/setup.h> 75 #include <asm/uv/uv.h> 76 #include <linux/mc146818rtc.h> 77 #include <asm/i8259.h> 78 #include <asm/misc.h> 79 #include <asm/qspinlock.h> 80 #include <asm/intel-family.h> 81 #include <asm/cpu_device_id.h> 82 #include <asm/spec-ctrl.h> 83 #include <asm/hw_irq.h> 84 #include <asm/stackprotector.h> 85 #include <asm/sev.h> 86 87 /* representing HT siblings of each logical CPU */ 88 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); 89 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 90 91 /* representing HT and core siblings of each logical CPU */ 92 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); 93 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 94 95 /* representing HT, core, and die siblings of each logical CPU */ 96 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_die_map); 97 EXPORT_PER_CPU_SYMBOL(cpu_die_map); 98 99 /* Per CPU bogomips and other parameters */ 100 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 101 EXPORT_PER_CPU_SYMBOL(cpu_info); 102 103 /* Logical package management. We might want to allocate that dynamically */ 104 unsigned int __max_logical_packages __read_mostly; 105 EXPORT_SYMBOL(__max_logical_packages); 106 static unsigned int logical_packages __read_mostly; 107 static unsigned int logical_die __read_mostly; 108 109 /* Maximum number of SMT threads on any online core */ 110 int __read_mostly __max_smt_threads = 1; 111 112 /* Flag to indicate if a complete sched domain rebuild is required */ 113 bool x86_topology_update; 114 115 int arch_update_cpu_topology(void) 116 { 117 int retval = x86_topology_update; 118 119 x86_topology_update = false; 120 return retval; 121 } 122 123 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) 124 { 125 unsigned long flags; 126 127 spin_lock_irqsave(&rtc_lock, flags); 128 CMOS_WRITE(0xa, 0xf); 129 spin_unlock_irqrestore(&rtc_lock, flags); 130 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = 131 start_eip >> 4; 132 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 133 start_eip & 0xf; 134 } 135 136 static inline void smpboot_restore_warm_reset_vector(void) 137 { 138 unsigned long flags; 139 140 /* 141 * Paranoid: Set warm reset code and vector here back 142 * to default values. 143 */ 144 spin_lock_irqsave(&rtc_lock, flags); 145 CMOS_WRITE(0, 0xf); 146 spin_unlock_irqrestore(&rtc_lock, flags); 147 148 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0; 149 } 150 151 /* 152 * Report back to the Boot Processor during boot time or to the caller processor 153 * during CPU online. 154 */ 155 static void smp_callin(void) 156 { 157 int cpuid; 158 159 /* 160 * If waken up by an INIT in an 82489DX configuration 161 * cpu_callout_mask guarantees we don't get here before 162 * an INIT_deassert IPI reaches our local APIC, so it is 163 * now safe to touch our local APIC. 164 */ 165 cpuid = smp_processor_id(); 166 167 /* 168 * the boot CPU has finished the init stage and is spinning 169 * on callin_map until we finish. We are free to set up this 170 * CPU, first the APIC. (this is probably redundant on most 171 * boards) 172 */ 173 apic_ap_setup(); 174 175 /* 176 * Save our processor parameters. Note: this information 177 * is needed for clock calibration. 178 */ 179 smp_store_cpu_info(cpuid); 180 181 /* 182 * The topology information must be up to date before 183 * calibrate_delay() and notify_cpu_starting(). 184 */ 185 set_cpu_sibling_map(raw_smp_processor_id()); 186 187 ap_init_aperfmperf(); 188 189 /* 190 * Get our bogomips. 191 * Update loops_per_jiffy in cpu_data. Previous call to 192 * smp_store_cpu_info() stored a value that is close but not as 193 * accurate as the value just calculated. 194 */ 195 calibrate_delay(); 196 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy; 197 pr_debug("Stack at about %p\n", &cpuid); 198 199 wmb(); 200 201 notify_cpu_starting(cpuid); 202 203 /* 204 * Allow the master to continue. 205 */ 206 cpumask_set_cpu(cpuid, cpu_callin_mask); 207 } 208 209 static int cpu0_logical_apicid; 210 static int enable_start_cpu0; 211 /* 212 * Activate a secondary processor. 213 */ 214 static void notrace start_secondary(void *unused) 215 { 216 /* 217 * Don't put *anything* except direct CPU state initialization 218 * before cpu_init(), SMP booting is too fragile that we want to 219 * limit the things done here to the most necessary things. 220 */ 221 cr4_init(); 222 223 #ifdef CONFIG_X86_32 224 /* switch away from the initial page table */ 225 load_cr3(swapper_pg_dir); 226 __flush_tlb_all(); 227 #endif 228 cpu_init_secondary(); 229 rcu_cpu_starting(raw_smp_processor_id()); 230 x86_cpuinit.early_percpu_clock_init(); 231 smp_callin(); 232 233 enable_start_cpu0 = 0; 234 235 /* otherwise gcc will move up smp_processor_id before the cpu_init */ 236 barrier(); 237 /* 238 * Check TSC synchronization with the boot CPU: 239 */ 240 check_tsc_sync_target(); 241 242 speculative_store_bypass_ht_init(); 243 244 /* 245 * Lock vector_lock, set CPU online and bring the vector 246 * allocator online. Online must be set with vector_lock held 247 * to prevent a concurrent irq setup/teardown from seeing a 248 * half valid vector space. 249 */ 250 lock_vector_lock(); 251 set_cpu_online(smp_processor_id(), true); 252 lapic_online(); 253 unlock_vector_lock(); 254 cpu_set_state_online(smp_processor_id()); 255 x86_platform.nmi_init(); 256 257 /* enable local interrupts */ 258 local_irq_enable(); 259 260 x86_cpuinit.setup_percpu_clockev(); 261 262 wmb(); 263 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); 264 } 265 266 /** 267 * topology_is_primary_thread - Check whether CPU is the primary SMT thread 268 * @cpu: CPU to check 269 */ 270 bool topology_is_primary_thread(unsigned int cpu) 271 { 272 return apic_id_is_primary_thread(per_cpu(x86_cpu_to_apicid, cpu)); 273 } 274 275 /** 276 * topology_smt_supported - Check whether SMT is supported by the CPUs 277 */ 278 bool topology_smt_supported(void) 279 { 280 return smp_num_siblings > 1; 281 } 282 283 /** 284 * topology_phys_to_logical_pkg - Map a physical package id to a logical 285 * 286 * Returns logical package id or -1 if not found 287 */ 288 int topology_phys_to_logical_pkg(unsigned int phys_pkg) 289 { 290 int cpu; 291 292 for_each_possible_cpu(cpu) { 293 struct cpuinfo_x86 *c = &cpu_data(cpu); 294 295 if (c->initialized && c->phys_proc_id == phys_pkg) 296 return c->logical_proc_id; 297 } 298 return -1; 299 } 300 EXPORT_SYMBOL(topology_phys_to_logical_pkg); 301 /** 302 * topology_phys_to_logical_die - Map a physical die id to logical 303 * 304 * Returns logical die id or -1 if not found 305 */ 306 int topology_phys_to_logical_die(unsigned int die_id, unsigned int cur_cpu) 307 { 308 int cpu; 309 int proc_id = cpu_data(cur_cpu).phys_proc_id; 310 311 for_each_possible_cpu(cpu) { 312 struct cpuinfo_x86 *c = &cpu_data(cpu); 313 314 if (c->initialized && c->cpu_die_id == die_id && 315 c->phys_proc_id == proc_id) 316 return c->logical_die_id; 317 } 318 return -1; 319 } 320 EXPORT_SYMBOL(topology_phys_to_logical_die); 321 322 /** 323 * topology_update_package_map - Update the physical to logical package map 324 * @pkg: The physical package id as retrieved via CPUID 325 * @cpu: The cpu for which this is updated 326 */ 327 int topology_update_package_map(unsigned int pkg, unsigned int cpu) 328 { 329 int new; 330 331 /* Already available somewhere? */ 332 new = topology_phys_to_logical_pkg(pkg); 333 if (new >= 0) 334 goto found; 335 336 new = logical_packages++; 337 if (new != pkg) { 338 pr_info("CPU %u Converting physical %u to logical package %u\n", 339 cpu, pkg, new); 340 } 341 found: 342 cpu_data(cpu).logical_proc_id = new; 343 return 0; 344 } 345 /** 346 * topology_update_die_map - Update the physical to logical die map 347 * @die: The die id as retrieved via CPUID 348 * @cpu: The cpu for which this is updated 349 */ 350 int topology_update_die_map(unsigned int die, unsigned int cpu) 351 { 352 int new; 353 354 /* Already available somewhere? */ 355 new = topology_phys_to_logical_die(die, cpu); 356 if (new >= 0) 357 goto found; 358 359 new = logical_die++; 360 if (new != die) { 361 pr_info("CPU %u Converting physical %u to logical die %u\n", 362 cpu, die, new); 363 } 364 found: 365 cpu_data(cpu).logical_die_id = new; 366 return 0; 367 } 368 369 void __init smp_store_boot_cpu_info(void) 370 { 371 int id = 0; /* CPU 0 */ 372 struct cpuinfo_x86 *c = &cpu_data(id); 373 374 *c = boot_cpu_data; 375 c->cpu_index = id; 376 topology_update_package_map(c->phys_proc_id, id); 377 topology_update_die_map(c->cpu_die_id, id); 378 c->initialized = true; 379 } 380 381 /* 382 * The bootstrap kernel entry code has set these up. Save them for 383 * a given CPU 384 */ 385 void smp_store_cpu_info(int id) 386 { 387 struct cpuinfo_x86 *c = &cpu_data(id); 388 389 /* Copy boot_cpu_data only on the first bringup */ 390 if (!c->initialized) 391 *c = boot_cpu_data; 392 c->cpu_index = id; 393 /* 394 * During boot time, CPU0 has this setup already. Save the info when 395 * bringing up AP or offlined CPU0. 396 */ 397 identify_secondary_cpu(c); 398 c->initialized = true; 399 } 400 401 static bool 402 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 403 { 404 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 405 406 return (cpu_to_node(cpu1) == cpu_to_node(cpu2)); 407 } 408 409 static bool 410 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) 411 { 412 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 413 414 return !WARN_ONCE(!topology_same_node(c, o), 415 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " 416 "[node: %d != %d]. Ignoring dependency.\n", 417 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); 418 } 419 420 #define link_mask(mfunc, c1, c2) \ 421 do { \ 422 cpumask_set_cpu((c1), mfunc(c2)); \ 423 cpumask_set_cpu((c2), mfunc(c1)); \ 424 } while (0) 425 426 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 427 { 428 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 429 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 430 431 if (c->phys_proc_id == o->phys_proc_id && 432 c->cpu_die_id == o->cpu_die_id && 433 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) { 434 if (c->cpu_core_id == o->cpu_core_id) 435 return topology_sane(c, o, "smt"); 436 437 if ((c->cu_id != 0xff) && 438 (o->cu_id != 0xff) && 439 (c->cu_id == o->cu_id)) 440 return topology_sane(c, o, "smt"); 441 } 442 443 } else if (c->phys_proc_id == o->phys_proc_id && 444 c->cpu_die_id == o->cpu_die_id && 445 c->cpu_core_id == o->cpu_core_id) { 446 return topology_sane(c, o, "smt"); 447 } 448 449 return false; 450 } 451 452 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 453 { 454 if (c->phys_proc_id == o->phys_proc_id && 455 c->cpu_die_id == o->cpu_die_id) 456 return true; 457 return false; 458 } 459 460 static bool match_l2c(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 461 { 462 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 463 464 /* If the arch didn't set up l2c_id, fall back to SMT */ 465 if (per_cpu(cpu_l2c_id, cpu1) == BAD_APICID) 466 return match_smt(c, o); 467 468 /* Do not match if L2 cache id does not match: */ 469 if (per_cpu(cpu_l2c_id, cpu1) != per_cpu(cpu_l2c_id, cpu2)) 470 return false; 471 472 return topology_sane(c, o, "l2c"); 473 } 474 475 /* 476 * Unlike the other levels, we do not enforce keeping a 477 * multicore group inside a NUMA node. If this happens, we will 478 * discard the MC level of the topology later. 479 */ 480 static bool match_pkg(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 481 { 482 if (c->phys_proc_id == o->phys_proc_id) 483 return true; 484 return false; 485 } 486 487 /* 488 * Define intel_cod_cpu[] for Intel COD (Cluster-on-Die) CPUs. 489 * 490 * Any Intel CPU that has multiple nodes per package and does not 491 * match intel_cod_cpu[] has the SNC (Sub-NUMA Cluster) topology. 492 * 493 * When in SNC mode, these CPUs enumerate an LLC that is shared 494 * by multiple NUMA nodes. The LLC is shared for off-package data 495 * access but private to the NUMA node (half of the package) for 496 * on-package access. CPUID (the source of the information about 497 * the LLC) can only enumerate the cache as shared or unshared, 498 * but not this particular configuration. 499 */ 500 501 static const struct x86_cpu_id intel_cod_cpu[] = { 502 X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, 0), /* COD */ 503 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, 0), /* COD */ 504 X86_MATCH_INTEL_FAM6_MODEL(ANY, 1), /* SNC */ 505 {} 506 }; 507 508 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 509 { 510 const struct x86_cpu_id *id = x86_match_cpu(intel_cod_cpu); 511 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 512 bool intel_snc = id && id->driver_data; 513 514 /* Do not match if we do not have a valid APICID for cpu: */ 515 if (per_cpu(cpu_llc_id, cpu1) == BAD_APICID) 516 return false; 517 518 /* Do not match if LLC id does not match: */ 519 if (per_cpu(cpu_llc_id, cpu1) != per_cpu(cpu_llc_id, cpu2)) 520 return false; 521 522 /* 523 * Allow the SNC topology without warning. Return of false 524 * means 'c' does not share the LLC of 'o'. This will be 525 * reflected to userspace. 526 */ 527 if (match_pkg(c, o) && !topology_same_node(c, o) && intel_snc) 528 return false; 529 530 return topology_sane(c, o, "llc"); 531 } 532 533 534 #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_CLUSTER) || defined(CONFIG_SCHED_MC) 535 static inline int x86_sched_itmt_flags(void) 536 { 537 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0; 538 } 539 540 #ifdef CONFIG_SCHED_MC 541 static int x86_core_flags(void) 542 { 543 return cpu_core_flags() | x86_sched_itmt_flags(); 544 } 545 #endif 546 #ifdef CONFIG_SCHED_SMT 547 static int x86_smt_flags(void) 548 { 549 return cpu_smt_flags() | x86_sched_itmt_flags(); 550 } 551 #endif 552 #ifdef CONFIG_SCHED_CLUSTER 553 static int x86_cluster_flags(void) 554 { 555 return cpu_cluster_flags() | x86_sched_itmt_flags(); 556 } 557 #endif 558 #endif 559 560 static struct sched_domain_topology_level x86_numa_in_package_topology[] = { 561 #ifdef CONFIG_SCHED_SMT 562 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, 563 #endif 564 #ifdef CONFIG_SCHED_CLUSTER 565 { cpu_clustergroup_mask, x86_cluster_flags, SD_INIT_NAME(CLS) }, 566 #endif 567 #ifdef CONFIG_SCHED_MC 568 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, 569 #endif 570 { NULL, }, 571 }; 572 573 static struct sched_domain_topology_level x86_hybrid_topology[] = { 574 #ifdef CONFIG_SCHED_SMT 575 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, 576 #endif 577 #ifdef CONFIG_SCHED_MC 578 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, 579 #endif 580 { cpu_cpu_mask, SD_INIT_NAME(DIE) }, 581 { NULL, }, 582 }; 583 584 static struct sched_domain_topology_level x86_topology[] = { 585 #ifdef CONFIG_SCHED_SMT 586 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, 587 #endif 588 #ifdef CONFIG_SCHED_CLUSTER 589 { cpu_clustergroup_mask, x86_cluster_flags, SD_INIT_NAME(CLS) }, 590 #endif 591 #ifdef CONFIG_SCHED_MC 592 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, 593 #endif 594 { cpu_cpu_mask, SD_INIT_NAME(DIE) }, 595 { NULL, }, 596 }; 597 598 /* 599 * Set if a package/die has multiple NUMA nodes inside. 600 * AMD Magny-Cours, Intel Cluster-on-Die, and Intel 601 * Sub-NUMA Clustering have this. 602 */ 603 static bool x86_has_numa_in_package; 604 605 void set_cpu_sibling_map(int cpu) 606 { 607 bool has_smt = smp_num_siblings > 1; 608 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1; 609 struct cpuinfo_x86 *c = &cpu_data(cpu); 610 struct cpuinfo_x86 *o; 611 int i, threads; 612 613 cpumask_set_cpu(cpu, cpu_sibling_setup_mask); 614 615 if (!has_mp) { 616 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu)); 617 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); 618 cpumask_set_cpu(cpu, cpu_l2c_shared_mask(cpu)); 619 cpumask_set_cpu(cpu, topology_core_cpumask(cpu)); 620 cpumask_set_cpu(cpu, topology_die_cpumask(cpu)); 621 c->booted_cores = 1; 622 return; 623 } 624 625 for_each_cpu(i, cpu_sibling_setup_mask) { 626 o = &cpu_data(i); 627 628 if (match_pkg(c, o) && !topology_same_node(c, o)) 629 x86_has_numa_in_package = true; 630 631 if ((i == cpu) || (has_smt && match_smt(c, o))) 632 link_mask(topology_sibling_cpumask, cpu, i); 633 634 if ((i == cpu) || (has_mp && match_llc(c, o))) 635 link_mask(cpu_llc_shared_mask, cpu, i); 636 637 if ((i == cpu) || (has_mp && match_l2c(c, o))) 638 link_mask(cpu_l2c_shared_mask, cpu, i); 639 640 if ((i == cpu) || (has_mp && match_die(c, o))) 641 link_mask(topology_die_cpumask, cpu, i); 642 } 643 644 threads = cpumask_weight(topology_sibling_cpumask(cpu)); 645 if (threads > __max_smt_threads) 646 __max_smt_threads = threads; 647 648 for_each_cpu(i, topology_sibling_cpumask(cpu)) 649 cpu_data(i).smt_active = threads > 1; 650 651 /* 652 * This needs a separate iteration over the cpus because we rely on all 653 * topology_sibling_cpumask links to be set-up. 654 */ 655 for_each_cpu(i, cpu_sibling_setup_mask) { 656 o = &cpu_data(i); 657 658 if ((i == cpu) || (has_mp && match_pkg(c, o))) { 659 link_mask(topology_core_cpumask, cpu, i); 660 661 /* 662 * Does this new cpu bringup a new core? 663 */ 664 if (threads == 1) { 665 /* 666 * for each core in package, increment 667 * the booted_cores for this new cpu 668 */ 669 if (cpumask_first( 670 topology_sibling_cpumask(i)) == i) 671 c->booted_cores++; 672 /* 673 * increment the core count for all 674 * the other cpus in this package 675 */ 676 if (i != cpu) 677 cpu_data(i).booted_cores++; 678 } else if (i != cpu && !c->booted_cores) 679 c->booted_cores = cpu_data(i).booted_cores; 680 } 681 } 682 } 683 684 /* maps the cpu to the sched domain representing multi-core */ 685 const struct cpumask *cpu_coregroup_mask(int cpu) 686 { 687 return cpu_llc_shared_mask(cpu); 688 } 689 690 const struct cpumask *cpu_clustergroup_mask(int cpu) 691 { 692 return cpu_l2c_shared_mask(cpu); 693 } 694 695 static void impress_friends(void) 696 { 697 int cpu; 698 unsigned long bogosum = 0; 699 /* 700 * Allow the user to impress friends. 701 */ 702 pr_debug("Before bogomips\n"); 703 for_each_possible_cpu(cpu) 704 if (cpumask_test_cpu(cpu, cpu_callout_mask)) 705 bogosum += cpu_data(cpu).loops_per_jiffy; 706 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", 707 num_online_cpus(), 708 bogosum/(500000/HZ), 709 (bogosum/(5000/HZ))%100); 710 711 pr_debug("Before bogocount - setting activated=1\n"); 712 } 713 714 void __inquire_remote_apic(int apicid) 715 { 716 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; 717 const char * const names[] = { "ID", "VERSION", "SPIV" }; 718 int timeout; 719 u32 status; 720 721 pr_info("Inquiring remote APIC 0x%x...\n", apicid); 722 723 for (i = 0; i < ARRAY_SIZE(regs); i++) { 724 pr_info("... APIC 0x%x %s: ", apicid, names[i]); 725 726 /* 727 * Wait for idle. 728 */ 729 status = safe_apic_wait_icr_idle(); 730 if (status) 731 pr_cont("a previous APIC delivery may have failed\n"); 732 733 apic_icr_write(APIC_DM_REMRD | regs[i], apicid); 734 735 timeout = 0; 736 do { 737 udelay(100); 738 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; 739 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); 740 741 switch (status) { 742 case APIC_ICR_RR_VALID: 743 status = apic_read(APIC_RRR); 744 pr_cont("%08x\n", status); 745 break; 746 default: 747 pr_cont("failed\n"); 748 } 749 } 750 } 751 752 /* 753 * The Multiprocessor Specification 1.4 (1997) example code suggests 754 * that there should be a 10ms delay between the BSP asserting INIT 755 * and de-asserting INIT, when starting a remote processor. 756 * But that slows boot and resume on modern processors, which include 757 * many cores and don't require that delay. 758 * 759 * Cmdline "init_cpu_udelay=" is available to over-ride this delay. 760 * Modern processor families are quirked to remove the delay entirely. 761 */ 762 #define UDELAY_10MS_DEFAULT 10000 763 764 static unsigned int init_udelay = UINT_MAX; 765 766 static int __init cpu_init_udelay(char *str) 767 { 768 get_option(&str, &init_udelay); 769 770 return 0; 771 } 772 early_param("cpu_init_udelay", cpu_init_udelay); 773 774 static void __init smp_quirk_init_udelay(void) 775 { 776 /* if cmdline changed it from default, leave it alone */ 777 if (init_udelay != UINT_MAX) 778 return; 779 780 /* if modern processor, use no delay */ 781 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) || 782 ((boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) && (boot_cpu_data.x86 >= 0x18)) || 783 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) { 784 init_udelay = 0; 785 return; 786 } 787 /* else, use legacy delay */ 788 init_udelay = UDELAY_10MS_DEFAULT; 789 } 790 791 /* 792 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal 793 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this 794 * won't ... remember to clear down the APIC, etc later. 795 */ 796 int 797 wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip) 798 { 799 u32 dm = apic->dest_mode_logical ? APIC_DEST_LOGICAL : APIC_DEST_PHYSICAL; 800 unsigned long send_status, accept_status = 0; 801 int maxlvt; 802 803 /* Target chip */ 804 /* Boot on the stack */ 805 /* Kick the second */ 806 apic_icr_write(APIC_DM_NMI | dm, apicid); 807 808 pr_debug("Waiting for send to finish...\n"); 809 send_status = safe_apic_wait_icr_idle(); 810 811 /* 812 * Give the other CPU some time to accept the IPI. 813 */ 814 udelay(200); 815 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 816 maxlvt = lapic_get_maxlvt(); 817 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 818 apic_write(APIC_ESR, 0); 819 accept_status = (apic_read(APIC_ESR) & 0xEF); 820 } 821 pr_debug("NMI sent\n"); 822 823 if (send_status) 824 pr_err("APIC never delivered???\n"); 825 if (accept_status) 826 pr_err("APIC delivery error (%lx)\n", accept_status); 827 828 return (send_status | accept_status); 829 } 830 831 static int 832 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) 833 { 834 unsigned long send_status = 0, accept_status = 0; 835 int maxlvt, num_starts, j; 836 837 maxlvt = lapic_get_maxlvt(); 838 839 /* 840 * Be paranoid about clearing APIC errors. 841 */ 842 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 843 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 844 apic_write(APIC_ESR, 0); 845 apic_read(APIC_ESR); 846 } 847 848 pr_debug("Asserting INIT\n"); 849 850 /* 851 * Turn INIT on target chip 852 */ 853 /* 854 * Send IPI 855 */ 856 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, 857 phys_apicid); 858 859 pr_debug("Waiting for send to finish...\n"); 860 send_status = safe_apic_wait_icr_idle(); 861 862 udelay(init_udelay); 863 864 pr_debug("Deasserting INIT\n"); 865 866 /* Target chip */ 867 /* Send IPI */ 868 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); 869 870 pr_debug("Waiting for send to finish...\n"); 871 send_status = safe_apic_wait_icr_idle(); 872 873 mb(); 874 875 /* 876 * Should we send STARTUP IPIs ? 877 * 878 * Determine this based on the APIC version. 879 * If we don't have an integrated APIC, don't send the STARTUP IPIs. 880 */ 881 if (APIC_INTEGRATED(boot_cpu_apic_version)) 882 num_starts = 2; 883 else 884 num_starts = 0; 885 886 /* 887 * Run STARTUP IPI loop. 888 */ 889 pr_debug("#startup loops: %d\n", num_starts); 890 891 for (j = 1; j <= num_starts; j++) { 892 pr_debug("Sending STARTUP #%d\n", j); 893 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 894 apic_write(APIC_ESR, 0); 895 apic_read(APIC_ESR); 896 pr_debug("After apic_write\n"); 897 898 /* 899 * STARTUP IPI 900 */ 901 902 /* Target chip */ 903 /* Boot on the stack */ 904 /* Kick the second */ 905 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), 906 phys_apicid); 907 908 /* 909 * Give the other CPU some time to accept the IPI. 910 */ 911 if (init_udelay == 0) 912 udelay(10); 913 else 914 udelay(300); 915 916 pr_debug("Startup point 1\n"); 917 918 pr_debug("Waiting for send to finish...\n"); 919 send_status = safe_apic_wait_icr_idle(); 920 921 /* 922 * Give the other CPU some time to accept the IPI. 923 */ 924 if (init_udelay == 0) 925 udelay(10); 926 else 927 udelay(200); 928 929 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 930 apic_write(APIC_ESR, 0); 931 accept_status = (apic_read(APIC_ESR) & 0xEF); 932 if (send_status || accept_status) 933 break; 934 } 935 pr_debug("After Startup\n"); 936 937 if (send_status) 938 pr_err("APIC never delivered???\n"); 939 if (accept_status) 940 pr_err("APIC delivery error (%lx)\n", accept_status); 941 942 return (send_status | accept_status); 943 } 944 945 /* reduce the number of lines printed when booting a large cpu count system */ 946 static void announce_cpu(int cpu, int apicid) 947 { 948 static int current_node = NUMA_NO_NODE; 949 int node = early_cpu_to_node(cpu); 950 static int width, node_width; 951 952 if (!width) 953 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ 954 955 if (!node_width) 956 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ 957 958 if (cpu == 1) 959 printk(KERN_INFO "x86: Booting SMP configuration:\n"); 960 961 if (system_state < SYSTEM_RUNNING) { 962 if (node != current_node) { 963 if (current_node > (-1)) 964 pr_cont("\n"); 965 current_node = node; 966 967 printk(KERN_INFO ".... node %*s#%d, CPUs: ", 968 node_width - num_digits(node), " ", node); 969 } 970 971 /* Add padding for the BSP */ 972 if (cpu == 1) 973 pr_cont("%*s", width + 1, " "); 974 975 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); 976 977 } else 978 pr_info("Booting Node %d Processor %d APIC 0x%x\n", 979 node, cpu, apicid); 980 } 981 982 static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs) 983 { 984 int cpu; 985 986 cpu = smp_processor_id(); 987 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0) 988 return NMI_HANDLED; 989 990 return NMI_DONE; 991 } 992 993 /* 994 * Wake up AP by INIT, INIT, STARTUP sequence. 995 * 996 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS 997 * boot-strap code which is not a desired behavior for waking up BSP. To 998 * void the boot-strap code, wake up CPU0 by NMI instead. 999 * 1000 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined 1001 * (i.e. physically hot removed and then hot added), NMI won't wake it up. 1002 * We'll change this code in the future to wake up hard offlined CPU0 if 1003 * real platform and request are available. 1004 */ 1005 static int 1006 wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid, 1007 int *cpu0_nmi_registered) 1008 { 1009 int id; 1010 int boot_error; 1011 1012 preempt_disable(); 1013 1014 /* 1015 * Wake up AP by INIT, INIT, STARTUP sequence. 1016 */ 1017 if (cpu) { 1018 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); 1019 goto out; 1020 } 1021 1022 /* 1023 * Wake up BSP by nmi. 1024 * 1025 * Register a NMI handler to help wake up CPU0. 1026 */ 1027 boot_error = register_nmi_handler(NMI_LOCAL, 1028 wakeup_cpu0_nmi, 0, "wake_cpu0"); 1029 1030 if (!boot_error) { 1031 enable_start_cpu0 = 1; 1032 *cpu0_nmi_registered = 1; 1033 id = apic->dest_mode_logical ? cpu0_logical_apicid : apicid; 1034 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip); 1035 } 1036 1037 out: 1038 preempt_enable(); 1039 1040 return boot_error; 1041 } 1042 1043 int common_cpu_up(unsigned int cpu, struct task_struct *idle) 1044 { 1045 int ret; 1046 1047 /* Just in case we booted with a single CPU. */ 1048 alternatives_enable_smp(); 1049 1050 per_cpu(current_task, cpu) = idle; 1051 cpu_init_stack_canary(cpu, idle); 1052 1053 /* Initialize the interrupt stack(s) */ 1054 ret = irq_init_percpu_irqstack(cpu); 1055 if (ret) 1056 return ret; 1057 1058 #ifdef CONFIG_X86_32 1059 /* Stack for startup_32 can be just as for start_secondary onwards */ 1060 per_cpu(cpu_current_top_of_stack, cpu) = task_top_of_stack(idle); 1061 #else 1062 initial_gs = per_cpu_offset(cpu); 1063 #endif 1064 return 0; 1065 } 1066 1067 /* 1068 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad 1069 * (ie clustered apic addressing mode), this is a LOGICAL apic ID. 1070 * Returns zero if CPU booted OK, else error code from 1071 * ->wakeup_secondary_cpu. 1072 */ 1073 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle, 1074 int *cpu0_nmi_registered) 1075 { 1076 /* start_ip had better be page-aligned! */ 1077 unsigned long start_ip = real_mode_header->trampoline_start; 1078 1079 unsigned long boot_error = 0; 1080 unsigned long timeout; 1081 1082 #ifdef CONFIG_X86_64 1083 /* If 64-bit wakeup method exists, use the 64-bit mode trampoline IP */ 1084 if (apic->wakeup_secondary_cpu_64) 1085 start_ip = real_mode_header->trampoline_start64; 1086 #endif 1087 idle->thread.sp = (unsigned long)task_pt_regs(idle); 1088 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu); 1089 initial_code = (unsigned long)start_secondary; 1090 initial_stack = idle->thread.sp; 1091 1092 /* Enable the espfix hack for this CPU */ 1093 init_espfix_ap(cpu); 1094 1095 /* So we see what's up */ 1096 announce_cpu(cpu, apicid); 1097 1098 /* 1099 * This grunge runs the startup process for 1100 * the targeted processor. 1101 */ 1102 1103 if (x86_platform.legacy.warm_reset) { 1104 1105 pr_debug("Setting warm reset code and vector.\n"); 1106 1107 smpboot_setup_warm_reset_vector(start_ip); 1108 /* 1109 * Be paranoid about clearing APIC errors. 1110 */ 1111 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 1112 apic_write(APIC_ESR, 0); 1113 apic_read(APIC_ESR); 1114 } 1115 } 1116 1117 /* 1118 * AP might wait on cpu_callout_mask in cpu_init() with 1119 * cpu_initialized_mask set if previous attempt to online 1120 * it timed-out. Clear cpu_initialized_mask so that after 1121 * INIT/SIPI it could start with a clean state. 1122 */ 1123 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1124 smp_mb(); 1125 1126 /* 1127 * Wake up a CPU in difference cases: 1128 * - Use a method from the APIC driver if one defined, with wakeup 1129 * straight to 64-bit mode preferred over wakeup to RM. 1130 * Otherwise, 1131 * - Use an INIT boot APIC message for APs or NMI for BSP. 1132 */ 1133 if (apic->wakeup_secondary_cpu_64) 1134 boot_error = apic->wakeup_secondary_cpu_64(apicid, start_ip); 1135 else if (apic->wakeup_secondary_cpu) 1136 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); 1137 else 1138 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid, 1139 cpu0_nmi_registered); 1140 1141 if (!boot_error) { 1142 /* 1143 * Wait 10s total for first sign of life from AP 1144 */ 1145 boot_error = -1; 1146 timeout = jiffies + 10*HZ; 1147 while (time_before(jiffies, timeout)) { 1148 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) { 1149 /* 1150 * Tell AP to proceed with initialization 1151 */ 1152 cpumask_set_cpu(cpu, cpu_callout_mask); 1153 boot_error = 0; 1154 break; 1155 } 1156 schedule(); 1157 } 1158 } 1159 1160 if (!boot_error) { 1161 /* 1162 * Wait till AP completes initial initialization 1163 */ 1164 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) { 1165 /* 1166 * Allow other tasks to run while we wait for the 1167 * AP to come online. This also gives a chance 1168 * for the MTRR work(triggered by the AP coming online) 1169 * to be completed in the stop machine context. 1170 */ 1171 schedule(); 1172 } 1173 } 1174 1175 if (x86_platform.legacy.warm_reset) { 1176 /* 1177 * Cleanup possible dangling ends... 1178 */ 1179 smpboot_restore_warm_reset_vector(); 1180 } 1181 1182 return boot_error; 1183 } 1184 1185 int native_cpu_up(unsigned int cpu, struct task_struct *tidle) 1186 { 1187 int apicid = apic->cpu_present_to_apicid(cpu); 1188 int cpu0_nmi_registered = 0; 1189 unsigned long flags; 1190 int err, ret = 0; 1191 1192 lockdep_assert_irqs_enabled(); 1193 1194 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); 1195 1196 if (apicid == BAD_APICID || 1197 !physid_isset(apicid, phys_cpu_present_map) || 1198 !apic->apic_id_valid(apicid)) { 1199 pr_err("%s: bad cpu %d\n", __func__, cpu); 1200 return -EINVAL; 1201 } 1202 1203 /* 1204 * Already booted CPU? 1205 */ 1206 if (cpumask_test_cpu(cpu, cpu_callin_mask)) { 1207 pr_debug("do_boot_cpu %d Already started\n", cpu); 1208 return -ENOSYS; 1209 } 1210 1211 /* 1212 * Save current MTRR state in case it was changed since early boot 1213 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: 1214 */ 1215 mtrr_save_state(); 1216 1217 /* x86 CPUs take themselves offline, so delayed offline is OK. */ 1218 err = cpu_check_up_prepare(cpu); 1219 if (err && err != -EBUSY) 1220 return err; 1221 1222 /* the FPU context is blank, nobody can own it */ 1223 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL; 1224 1225 err = common_cpu_up(cpu, tidle); 1226 if (err) 1227 return err; 1228 1229 err = do_boot_cpu(apicid, cpu, tidle, &cpu0_nmi_registered); 1230 if (err) { 1231 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu); 1232 ret = -EIO; 1233 goto unreg_nmi; 1234 } 1235 1236 /* 1237 * Check TSC synchronization with the AP (keep irqs disabled 1238 * while doing so): 1239 */ 1240 local_irq_save(flags); 1241 check_tsc_sync_source(cpu); 1242 local_irq_restore(flags); 1243 1244 while (!cpu_online(cpu)) { 1245 cpu_relax(); 1246 touch_nmi_watchdog(); 1247 } 1248 1249 unreg_nmi: 1250 /* 1251 * Clean up the nmi handler. Do this after the callin and callout sync 1252 * to avoid impact of possible long unregister time. 1253 */ 1254 if (cpu0_nmi_registered) 1255 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0"); 1256 1257 return ret; 1258 } 1259 1260 /** 1261 * arch_disable_smp_support() - disables SMP support for x86 at runtime 1262 */ 1263 void arch_disable_smp_support(void) 1264 { 1265 disable_ioapic_support(); 1266 } 1267 1268 /* 1269 * Fall back to non SMP mode after errors. 1270 * 1271 * RED-PEN audit/test this more. I bet there is more state messed up here. 1272 */ 1273 static __init void disable_smp(void) 1274 { 1275 pr_info("SMP disabled\n"); 1276 1277 disable_ioapic_support(); 1278 1279 init_cpu_present(cpumask_of(0)); 1280 init_cpu_possible(cpumask_of(0)); 1281 1282 if (smp_found_config) 1283 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 1284 else 1285 physid_set_mask_of_physid(0, &phys_cpu_present_map); 1286 cpumask_set_cpu(0, topology_sibling_cpumask(0)); 1287 cpumask_set_cpu(0, topology_core_cpumask(0)); 1288 cpumask_set_cpu(0, topology_die_cpumask(0)); 1289 } 1290 1291 /* 1292 * Various sanity checks. 1293 */ 1294 static void __init smp_sanity_check(void) 1295 { 1296 preempt_disable(); 1297 1298 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) 1299 if (def_to_bigsmp && nr_cpu_ids > 8) { 1300 unsigned int cpu; 1301 unsigned nr; 1302 1303 pr_warn("More than 8 CPUs detected - skipping them\n" 1304 "Use CONFIG_X86_BIGSMP\n"); 1305 1306 nr = 0; 1307 for_each_present_cpu(cpu) { 1308 if (nr >= 8) 1309 set_cpu_present(cpu, false); 1310 nr++; 1311 } 1312 1313 nr = 0; 1314 for_each_possible_cpu(cpu) { 1315 if (nr >= 8) 1316 set_cpu_possible(cpu, false); 1317 nr++; 1318 } 1319 1320 set_nr_cpu_ids(8); 1321 } 1322 #endif 1323 1324 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { 1325 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n", 1326 hard_smp_processor_id()); 1327 1328 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1329 } 1330 1331 /* 1332 * Should not be necessary because the MP table should list the boot 1333 * CPU too, but we do it for the sake of robustness anyway. 1334 */ 1335 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { 1336 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n", 1337 boot_cpu_physical_apicid); 1338 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1339 } 1340 preempt_enable(); 1341 } 1342 1343 static void __init smp_cpu_index_default(void) 1344 { 1345 int i; 1346 struct cpuinfo_x86 *c; 1347 1348 for_each_possible_cpu(i) { 1349 c = &cpu_data(i); 1350 /* mark all to hotplug */ 1351 c->cpu_index = nr_cpu_ids; 1352 } 1353 } 1354 1355 static void __init smp_get_logical_apicid(void) 1356 { 1357 if (x2apic_mode) 1358 cpu0_logical_apicid = apic_read(APIC_LDR); 1359 else 1360 cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)); 1361 } 1362 1363 void __init smp_prepare_cpus_common(void) 1364 { 1365 unsigned int i; 1366 1367 smp_cpu_index_default(); 1368 1369 /* 1370 * Setup boot CPU information 1371 */ 1372 smp_store_boot_cpu_info(); /* Final full version of the data */ 1373 cpumask_copy(cpu_callin_mask, cpumask_of(0)); 1374 mb(); 1375 1376 for_each_possible_cpu(i) { 1377 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); 1378 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); 1379 zalloc_cpumask_var(&per_cpu(cpu_die_map, i), GFP_KERNEL); 1380 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); 1381 zalloc_cpumask_var(&per_cpu(cpu_l2c_shared_map, i), GFP_KERNEL); 1382 } 1383 1384 /* 1385 * Set 'default' x86 topology, this matches default_topology() in that 1386 * it has NUMA nodes as a topology level. See also 1387 * native_smp_cpus_done(). 1388 * 1389 * Must be done before set_cpus_sibling_map() is ran. 1390 */ 1391 set_sched_topology(x86_topology); 1392 1393 set_cpu_sibling_map(0); 1394 } 1395 1396 /* 1397 * Prepare for SMP bootup. 1398 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter 1399 * for common interface support. 1400 */ 1401 void __init native_smp_prepare_cpus(unsigned int max_cpus) 1402 { 1403 smp_prepare_cpus_common(); 1404 1405 smp_sanity_check(); 1406 1407 switch (apic_intr_mode) { 1408 case APIC_PIC: 1409 case APIC_VIRTUAL_WIRE_NO_CONFIG: 1410 disable_smp(); 1411 return; 1412 case APIC_SYMMETRIC_IO_NO_ROUTING: 1413 disable_smp(); 1414 /* Setup local timer */ 1415 x86_init.timers.setup_percpu_clockev(); 1416 return; 1417 case APIC_VIRTUAL_WIRE: 1418 case APIC_SYMMETRIC_IO: 1419 break; 1420 } 1421 1422 /* Setup local timer */ 1423 x86_init.timers.setup_percpu_clockev(); 1424 1425 smp_get_logical_apicid(); 1426 1427 pr_info("CPU0: "); 1428 print_cpu_info(&cpu_data(0)); 1429 1430 uv_system_init(); 1431 1432 set_mtrr_aps_delayed_init(); 1433 1434 smp_quirk_init_udelay(); 1435 1436 speculative_store_bypass_ht_init(); 1437 1438 snp_set_wakeup_secondary_cpu(); 1439 } 1440 1441 void arch_thaw_secondary_cpus_begin(void) 1442 { 1443 set_mtrr_aps_delayed_init(); 1444 } 1445 1446 void arch_thaw_secondary_cpus_end(void) 1447 { 1448 mtrr_aps_init(); 1449 } 1450 1451 /* 1452 * Early setup to make printk work. 1453 */ 1454 void __init native_smp_prepare_boot_cpu(void) 1455 { 1456 int me = smp_processor_id(); 1457 switch_to_new_gdt(me); 1458 /* already set me in cpu_online_mask in boot_cpu_init() */ 1459 cpumask_set_cpu(me, cpu_callout_mask); 1460 cpu_set_state_online(me); 1461 native_pv_lock_init(); 1462 } 1463 1464 void __init calculate_max_logical_packages(void) 1465 { 1466 int ncpus; 1467 1468 /* 1469 * Today neither Intel nor AMD support heterogeneous systems so 1470 * extrapolate the boot cpu's data to all packages. 1471 */ 1472 ncpus = cpu_data(0).booted_cores * topology_max_smt_threads(); 1473 __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus); 1474 pr_info("Max logical packages: %u\n", __max_logical_packages); 1475 } 1476 1477 void __init native_smp_cpus_done(unsigned int max_cpus) 1478 { 1479 pr_debug("Boot done\n"); 1480 1481 calculate_max_logical_packages(); 1482 1483 /* XXX for now assume numa-in-package and hybrid don't overlap */ 1484 if (x86_has_numa_in_package) 1485 set_sched_topology(x86_numa_in_package_topology); 1486 if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) 1487 set_sched_topology(x86_hybrid_topology); 1488 1489 nmi_selftest(); 1490 impress_friends(); 1491 mtrr_aps_init(); 1492 } 1493 1494 static int __initdata setup_possible_cpus = -1; 1495 static int __init _setup_possible_cpus(char *str) 1496 { 1497 get_option(&str, &setup_possible_cpus); 1498 return 0; 1499 } 1500 early_param("possible_cpus", _setup_possible_cpus); 1501 1502 1503 /* 1504 * cpu_possible_mask should be static, it cannot change as cpu's 1505 * are onlined, or offlined. The reason is per-cpu data-structures 1506 * are allocated by some modules at init time, and don't expect to 1507 * do this dynamically on cpu arrival/departure. 1508 * cpu_present_mask on the other hand can change dynamically. 1509 * In case when cpu_hotplug is not compiled, then we resort to current 1510 * behaviour, which is cpu_possible == cpu_present. 1511 * - Ashok Raj 1512 * 1513 * Three ways to find out the number of additional hotplug CPUs: 1514 * - If the BIOS specified disabled CPUs in ACPI/mptables use that. 1515 * - The user can overwrite it with possible_cpus=NUM 1516 * - Otherwise don't reserve additional CPUs. 1517 * We do this because additional CPUs waste a lot of memory. 1518 * -AK 1519 */ 1520 __init void prefill_possible_map(void) 1521 { 1522 int i, possible; 1523 1524 /* No boot processor was found in mptable or ACPI MADT */ 1525 if (!num_processors) { 1526 if (boot_cpu_has(X86_FEATURE_APIC)) { 1527 int apicid = boot_cpu_physical_apicid; 1528 int cpu = hard_smp_processor_id(); 1529 1530 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu); 1531 1532 /* Make sure boot cpu is enumerated */ 1533 if (apic->cpu_present_to_apicid(0) == BAD_APICID && 1534 apic->apic_id_valid(apicid)) 1535 generic_processor_info(apicid, boot_cpu_apic_version); 1536 } 1537 1538 if (!num_processors) 1539 num_processors = 1; 1540 } 1541 1542 i = setup_max_cpus ?: 1; 1543 if (setup_possible_cpus == -1) { 1544 possible = num_processors; 1545 #ifdef CONFIG_HOTPLUG_CPU 1546 if (setup_max_cpus) 1547 possible += disabled_cpus; 1548 #else 1549 if (possible > i) 1550 possible = i; 1551 #endif 1552 } else 1553 possible = setup_possible_cpus; 1554 1555 total_cpus = max_t(int, possible, num_processors + disabled_cpus); 1556 1557 /* nr_cpu_ids could be reduced via nr_cpus= */ 1558 if (possible > nr_cpu_ids) { 1559 pr_warn("%d Processors exceeds NR_CPUS limit of %u\n", 1560 possible, nr_cpu_ids); 1561 possible = nr_cpu_ids; 1562 } 1563 1564 #ifdef CONFIG_HOTPLUG_CPU 1565 if (!setup_max_cpus) 1566 #endif 1567 if (possible > i) { 1568 pr_warn("%d Processors exceeds max_cpus limit of %u\n", 1569 possible, setup_max_cpus); 1570 possible = i; 1571 } 1572 1573 set_nr_cpu_ids(possible); 1574 1575 pr_info("Allowing %d CPUs, %d hotplug CPUs\n", 1576 possible, max_t(int, possible - num_processors, 0)); 1577 1578 reset_cpu_possible_mask(); 1579 1580 for (i = 0; i < possible; i++) 1581 set_cpu_possible(i, true); 1582 } 1583 1584 #ifdef CONFIG_HOTPLUG_CPU 1585 1586 /* Recompute SMT state for all CPUs on offline */ 1587 static void recompute_smt_state(void) 1588 { 1589 int max_threads, cpu; 1590 1591 max_threads = 0; 1592 for_each_online_cpu (cpu) { 1593 int threads = cpumask_weight(topology_sibling_cpumask(cpu)); 1594 1595 if (threads > max_threads) 1596 max_threads = threads; 1597 } 1598 __max_smt_threads = max_threads; 1599 } 1600 1601 static void remove_siblinginfo(int cpu) 1602 { 1603 int sibling; 1604 struct cpuinfo_x86 *c = &cpu_data(cpu); 1605 1606 for_each_cpu(sibling, topology_core_cpumask(cpu)) { 1607 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling)); 1608 /*/ 1609 * last thread sibling in this cpu core going down 1610 */ 1611 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1) 1612 cpu_data(sibling).booted_cores--; 1613 } 1614 1615 for_each_cpu(sibling, topology_die_cpumask(cpu)) 1616 cpumask_clear_cpu(cpu, topology_die_cpumask(sibling)); 1617 1618 for_each_cpu(sibling, topology_sibling_cpumask(cpu)) { 1619 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling)); 1620 if (cpumask_weight(topology_sibling_cpumask(sibling)) == 1) 1621 cpu_data(sibling).smt_active = false; 1622 } 1623 1624 for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) 1625 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling)); 1626 for_each_cpu(sibling, cpu_l2c_shared_mask(cpu)) 1627 cpumask_clear_cpu(cpu, cpu_l2c_shared_mask(sibling)); 1628 cpumask_clear(cpu_llc_shared_mask(cpu)); 1629 cpumask_clear(cpu_l2c_shared_mask(cpu)); 1630 cpumask_clear(topology_sibling_cpumask(cpu)); 1631 cpumask_clear(topology_core_cpumask(cpu)); 1632 cpumask_clear(topology_die_cpumask(cpu)); 1633 c->cpu_core_id = 0; 1634 c->booted_cores = 0; 1635 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); 1636 recompute_smt_state(); 1637 } 1638 1639 static void remove_cpu_from_maps(int cpu) 1640 { 1641 set_cpu_online(cpu, false); 1642 cpumask_clear_cpu(cpu, cpu_callout_mask); 1643 cpumask_clear_cpu(cpu, cpu_callin_mask); 1644 /* was set by cpu_init() */ 1645 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1646 numa_remove_cpu(cpu); 1647 } 1648 1649 void cpu_disable_common(void) 1650 { 1651 int cpu = smp_processor_id(); 1652 1653 remove_siblinginfo(cpu); 1654 1655 /* It's now safe to remove this processor from the online map */ 1656 lock_vector_lock(); 1657 remove_cpu_from_maps(cpu); 1658 unlock_vector_lock(); 1659 fixup_irqs(); 1660 lapic_offline(); 1661 } 1662 1663 int native_cpu_disable(void) 1664 { 1665 int ret; 1666 1667 ret = lapic_can_unplug_cpu(); 1668 if (ret) 1669 return ret; 1670 1671 cpu_disable_common(); 1672 1673 /* 1674 * Disable the local APIC. Otherwise IPI broadcasts will reach 1675 * it. It still responds normally to INIT, NMI, SMI, and SIPI 1676 * messages. 1677 * 1678 * Disabling the APIC must happen after cpu_disable_common() 1679 * which invokes fixup_irqs(). 1680 * 1681 * Disabling the APIC preserves already set bits in IRR, but 1682 * an interrupt arriving after disabling the local APIC does not 1683 * set the corresponding IRR bit. 1684 * 1685 * fixup_irqs() scans IRR for set bits so it can raise a not 1686 * yet handled interrupt on the new destination CPU via an IPI 1687 * but obviously it can't do so for IRR bits which are not set. 1688 * IOW, interrupts arriving after disabling the local APIC will 1689 * be lost. 1690 */ 1691 apic_soft_disable(); 1692 1693 return 0; 1694 } 1695 1696 int common_cpu_die(unsigned int cpu) 1697 { 1698 int ret = 0; 1699 1700 /* We don't do anything here: idle task is faking death itself. */ 1701 1702 /* They ack this in play_dead() by setting CPU_DEAD */ 1703 if (cpu_wait_death(cpu, 5)) { 1704 if (system_state == SYSTEM_RUNNING) 1705 pr_info("CPU %u is now offline\n", cpu); 1706 } else { 1707 pr_err("CPU %u didn't die...\n", cpu); 1708 ret = -1; 1709 } 1710 1711 return ret; 1712 } 1713 1714 void native_cpu_die(unsigned int cpu) 1715 { 1716 common_cpu_die(cpu); 1717 } 1718 1719 void play_dead_common(void) 1720 { 1721 idle_task_exit(); 1722 1723 /* Ack it */ 1724 (void)cpu_report_death(); 1725 1726 /* 1727 * With physical CPU hotplug, we should halt the cpu 1728 */ 1729 local_irq_disable(); 1730 } 1731 1732 /** 1733 * cond_wakeup_cpu0 - Wake up CPU0 if needed. 1734 * 1735 * If NMI wants to wake up CPU0, start CPU0. 1736 */ 1737 void cond_wakeup_cpu0(void) 1738 { 1739 if (smp_processor_id() == 0 && enable_start_cpu0) 1740 start_cpu0(); 1741 } 1742 EXPORT_SYMBOL_GPL(cond_wakeup_cpu0); 1743 1744 /* 1745 * We need to flush the caches before going to sleep, lest we have 1746 * dirty data in our caches when we come back up. 1747 */ 1748 static inline void mwait_play_dead(void) 1749 { 1750 unsigned int eax, ebx, ecx, edx; 1751 unsigned int highest_cstate = 0; 1752 unsigned int highest_subcstate = 0; 1753 void *mwait_ptr; 1754 int i; 1755 1756 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD || 1757 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) 1758 return; 1759 if (!this_cpu_has(X86_FEATURE_MWAIT)) 1760 return; 1761 if (!this_cpu_has(X86_FEATURE_CLFLUSH)) 1762 return; 1763 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) 1764 return; 1765 1766 eax = CPUID_MWAIT_LEAF; 1767 ecx = 0; 1768 native_cpuid(&eax, &ebx, &ecx, &edx); 1769 1770 /* 1771 * eax will be 0 if EDX enumeration is not valid. 1772 * Initialized below to cstate, sub_cstate value when EDX is valid. 1773 */ 1774 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { 1775 eax = 0; 1776 } else { 1777 edx >>= MWAIT_SUBSTATE_SIZE; 1778 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { 1779 if (edx & MWAIT_SUBSTATE_MASK) { 1780 highest_cstate = i; 1781 highest_subcstate = edx & MWAIT_SUBSTATE_MASK; 1782 } 1783 } 1784 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | 1785 (highest_subcstate - 1); 1786 } 1787 1788 /* 1789 * This should be a memory location in a cache line which is 1790 * unlikely to be touched by other processors. The actual 1791 * content is immaterial as it is not actually modified in any way. 1792 */ 1793 mwait_ptr = ¤t_thread_info()->flags; 1794 1795 wbinvd(); 1796 1797 while (1) { 1798 /* 1799 * The CLFLUSH is a workaround for erratum AAI65 for 1800 * the Xeon 7400 series. It's not clear it is actually 1801 * needed, but it should be harmless in either case. 1802 * The WBINVD is insufficient due to the spurious-wakeup 1803 * case where we return around the loop. 1804 */ 1805 mb(); 1806 clflush(mwait_ptr); 1807 mb(); 1808 __monitor(mwait_ptr, 0, 0); 1809 mb(); 1810 __mwait(eax, 0); 1811 1812 cond_wakeup_cpu0(); 1813 } 1814 } 1815 1816 void hlt_play_dead(void) 1817 { 1818 if (__this_cpu_read(cpu_info.x86) >= 4) 1819 wbinvd(); 1820 1821 while (1) { 1822 native_halt(); 1823 1824 cond_wakeup_cpu0(); 1825 } 1826 } 1827 1828 void native_play_dead(void) 1829 { 1830 play_dead_common(); 1831 tboot_shutdown(TB_SHUTDOWN_WFS); 1832 1833 mwait_play_dead(); /* Only returns on failure */ 1834 if (cpuidle_play_dead()) 1835 hlt_play_dead(); 1836 } 1837 1838 #else /* ... !CONFIG_HOTPLUG_CPU */ 1839 int native_cpu_disable(void) 1840 { 1841 return -ENOSYS; 1842 } 1843 1844 void native_cpu_die(unsigned int cpu) 1845 { 1846 /* We said "no" in __cpu_disable */ 1847 BUG(); 1848 } 1849 1850 void native_play_dead(void) 1851 { 1852 BUG(); 1853 } 1854 1855 #endif 1856