1# SPDX-License-Identifier: GPL-2.0-only 2config ARCH_HAS_RESET_CONTROLLER 3 bool 4 5menuconfig RESET_CONTROLLER 6 bool "Reset Controller Support" 7 default y if ARCH_HAS_RESET_CONTROLLER 8 help 9 Generic Reset Controller support. 10 11 This framework is designed to abstract reset handling of devices 12 via GPIOs or SoC-internal reset controller modules. 13 14 If unsure, say no. 15 16if RESET_CONTROLLER 17 18config RESET_A10SR 19 tristate "Altera Arria10 System Resource Reset" 20 depends on MFD_ALTERA_A10SR || COMPILE_TEST 21 help 22 This option enables support for the external reset functions for 23 peripheral PHYs on the Altera Arria10 System Resource Chip. 24 25config RESET_ATH79 26 bool "AR71xx Reset Driver" if COMPILE_TEST 27 default ATH79 28 help 29 This enables the ATH79 reset controller driver that supports the 30 AR71xx SoC reset controller. 31 32config RESET_AXS10X 33 bool "AXS10x Reset Driver" if COMPILE_TEST 34 default ARC_PLAT_AXS10X 35 help 36 This enables the reset controller driver for AXS10x. 37 38config RESET_BCM6345 39 bool "BCM6345 Reset Controller" 40 depends on BMIPS_GENERIC || COMPILE_TEST 41 default BMIPS_GENERIC 42 help 43 This enables the reset controller driver for BCM6345 SoCs. 44 45config RESET_BERLIN 46 tristate "Berlin Reset Driver" 47 depends on ARCH_BERLIN || COMPILE_TEST 48 default m if ARCH_BERLIN 49 help 50 This enables the reset controller driver for Marvell Berlin SoCs. 51 52config RESET_BRCMSTB 53 tristate "Broadcom STB reset controller" 54 depends on ARCH_BRCMSTB || COMPILE_TEST 55 default ARCH_BRCMSTB 56 help 57 This enables the reset controller driver for Broadcom STB SoCs using 58 a SUN_TOP_CTRL_SW_INIT style controller. 59 60config RESET_BRCMSTB_RESCAL 61 tristate "Broadcom STB RESCAL reset controller" 62 depends on HAS_IOMEM 63 depends on ARCH_BRCMSTB || COMPILE_TEST 64 default ARCH_BRCMSTB 65 help 66 This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on 67 BCM7216. 68 69config RESET_HSDK 70 bool "Synopsys HSDK Reset Driver" 71 depends on HAS_IOMEM 72 depends on ARC_SOC_HSDK || COMPILE_TEST 73 help 74 This enables the reset controller driver for HSDK board. 75 76config RESET_IMX7 77 tristate "i.MX7/8 Reset Driver" 78 depends on HAS_IOMEM 79 depends on SOC_IMX7D || (ARM64 && ARCH_MXC) || COMPILE_TEST 80 default y if SOC_IMX7D 81 select MFD_SYSCON 82 help 83 This enables the reset controller driver for i.MX7 SoCs. 84 85config RESET_INTEL_GW 86 bool "Intel Reset Controller Driver" 87 depends on X86 || COMPILE_TEST 88 depends on OF && HAS_IOMEM 89 select REGMAP_MMIO 90 help 91 This enables the reset controller driver for Intel Gateway SoCs. 92 Say Y to control the reset signals provided by reset controller. 93 Otherwise, say N. 94 95config RESET_K210 96 bool "Reset controller driver for Canaan Kendryte K210 SoC" 97 depends on (SOC_CANAAN || COMPILE_TEST) && OF 98 select MFD_SYSCON 99 default SOC_CANAAN 100 help 101 Support for the Canaan Kendryte K210 RISC-V SoC reset controller. 102 Say Y if you want to control reset signals provided by this 103 controller. 104 105config RESET_LANTIQ 106 bool "Lantiq XWAY Reset Driver" if COMPILE_TEST 107 default SOC_TYPE_XWAY 108 help 109 This enables the reset controller driver for Lantiq / Intel XWAY SoCs. 110 111config RESET_LPC18XX 112 bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST 113 default ARCH_LPC18XX 114 help 115 This enables the reset controller driver for NXP LPC18xx/43xx SoCs. 116 117config RESET_MCHP_SPARX5 118 bool "Microchip Sparx5 reset driver" 119 depends on ARCH_SPARX5 || SOC_LAN966 || COMPILE_TEST 120 default y if SPARX5_SWITCH 121 select MFD_SYSCON 122 help 123 This driver supports switch core reset for the Microchip Sparx5 SoC. 124 125config RESET_MESON 126 tristate "Meson Reset Driver" 127 depends on ARCH_MESON || COMPILE_TEST 128 default ARCH_MESON 129 help 130 This enables the reset driver for Amlogic Meson SoCs. 131 132config RESET_MESON_AUDIO_ARB 133 tristate "Meson Audio Memory Arbiter Reset Driver" 134 depends on ARCH_MESON || COMPILE_TEST 135 help 136 This enables the reset driver for Audio Memory Arbiter of 137 Amlogic's A113 based SoCs 138 139config RESET_NPCM 140 bool "NPCM BMC Reset Driver" if COMPILE_TEST 141 default ARCH_NPCM 142 help 143 This enables the reset controller driver for Nuvoton NPCM 144 BMC SoCs. 145 146config RESET_PISTACHIO 147 bool "Pistachio Reset Driver" 148 depends on MIPS || COMPILE_TEST 149 help 150 This enables the reset driver for ImgTec Pistachio SoCs. 151 152config RESET_POLARFIRE_SOC 153 bool "Microchip PolarFire SoC (MPFS) Reset Driver" 154 depends on MCHP_CLK_MPFS 155 select AUXILIARY_BUS 156 default MCHP_CLK_MPFS 157 help 158 This driver supports peripheral reset for the Microchip PolarFire SoC 159 160config RESET_QCOM_AOSS 161 tristate "Qcom AOSS Reset Driver" 162 depends on ARCH_QCOM || COMPILE_TEST 163 help 164 This enables the AOSS (always on subsystem) reset driver 165 for Qualcomm SDM845 SoCs. Say Y if you want to control 166 reset signals provided by AOSS for Modem, Venus, ADSP, 167 GPU, Camera, Wireless, Display subsystem. Otherwise, say N. 168 169config RESET_QCOM_PDC 170 tristate "Qualcomm PDC Reset Driver" 171 depends on ARCH_QCOM || COMPILE_TEST 172 help 173 This enables the PDC (Power Domain Controller) reset driver 174 for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want 175 to control reset signals provided by PDC for Modem, Compute, 176 Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS. 177 178config RESET_RASPBERRYPI 179 tristate "Raspberry Pi 4 Firmware Reset Driver" 180 depends on RASPBERRYPI_FIRMWARE || (RASPBERRYPI_FIRMWARE=n && COMPILE_TEST) 181 default USB_XHCI_PCI 182 help 183 Raspberry Pi 4's co-processor controls some of the board's HW 184 initialization process, but it's up to Linux to trigger it when 185 relevant. This driver provides a reset controller capable of 186 interfacing with RPi4's co-processor and model these firmware 187 initialization routines as reset lines. 188 189config RESET_RZG2L_USBPHY_CTRL 190 tristate "Renesas RZ/G2L USBPHY control driver" 191 depends on ARCH_RZG2L || COMPILE_TEST 192 help 193 Support for USBPHY Control found on RZ/G2L family. It mainly 194 controls reset and power down of the USB/PHY. 195 196config RESET_SCMI 197 tristate "Reset driver controlled via ARM SCMI interface" 198 depends on ARM_SCMI_PROTOCOL || COMPILE_TEST 199 default ARM_SCMI_PROTOCOL 200 help 201 This driver provides support for reset signal/domains that are 202 controlled by firmware that implements the SCMI interface. 203 204 This driver uses SCMI Message Protocol to interact with the 205 firmware controlling all the reset signals. 206 207config RESET_SIMPLE 208 bool "Simple Reset Controller Driver" if COMPILE_TEST || EXPERT 209 default ARCH_ASPEED || ARCH_BCMBCA || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC 210 depends on HAS_IOMEM 211 help 212 This enables a simple reset controller driver for reset lines that 213 that can be asserted and deasserted by toggling bits in a contiguous, 214 exclusive register space. 215 216 Currently this driver supports: 217 - Altera SoCFPGAs 218 - ASPEED BMC SoCs 219 - Bitmain BM1880 SoC 220 - Realtek SoCs 221 - RCC reset controller in STM32 MCUs 222 - Allwinner SoCs 223 - SiFive FU740 SoCs 224 225config RESET_SOCFPGA 226 bool "SoCFPGA Reset Driver" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFPGA) 227 default ARM && ARCH_INTEL_SOCFPGA 228 select RESET_SIMPLE 229 help 230 This enables the reset driver for the SoCFPGA ARMv7 platforms. This 231 driver gets initialized early during platform init calls. 232 233config RESET_SUNPLUS 234 bool "Sunplus SoCs Reset Driver" if COMPILE_TEST 235 default ARCH_SUNPLUS 236 help 237 This enables the reset driver support for Sunplus SoCs. 238 The reset lines that can be asserted and deasserted by toggling bits 239 in a contiguous, exclusive register space. The register is HIWORD_MASKED, 240 which means each register holds 16 reset lines. 241 242config RESET_SUNXI 243 bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI 244 default ARCH_SUNXI 245 select RESET_SIMPLE 246 help 247 This enables the reset driver for Allwinner SoCs. 248 249config RESET_TI_SCI 250 tristate "TI System Control Interface (TI-SCI) reset driver" 251 depends on TI_SCI_PROTOCOL || (COMPILE_TEST && TI_SCI_PROTOCOL=n) 252 help 253 This enables the reset driver support over TI System Control Interface 254 available on some new TI's SoCs. If you wish to use reset resources 255 managed by the TI System Controller, say Y here. Otherwise, say N. 256 257config RESET_TI_SYSCON 258 tristate "TI SYSCON Reset Driver" 259 depends on HAS_IOMEM 260 select MFD_SYSCON 261 help 262 This enables the reset driver support for TI devices with 263 memory-mapped reset registers as part of a syscon device node. If 264 you wish to use the reset framework for such memory-mapped devices, 265 say Y here. Otherwise, say N. 266 267config RESET_TI_TPS380X 268 tristate "TI TPS380x Reset Driver" 269 select GPIOLIB 270 help 271 This enables the reset driver support for TI TPS380x devices. If 272 you wish to use the reset framework for such devices, say Y here. 273 Otherwise, say N. 274 275config RESET_TN48M_CPLD 276 tristate "Delta Networks TN48M switch CPLD reset controller" 277 depends on MFD_TN48M_CPLD || COMPILE_TEST 278 default MFD_TN48M_CPLD 279 help 280 This enables the reset controller driver for the Delta TN48M CPLD. 281 It provides reset signals for Armada 7040 and 385 SoC-s, Alleycat 3X 282 switch MAC-s, Alaska OOB ethernet PHY, Quad Alaska ethernet PHY-s and 283 Microchip PD69200 PoE PSE controller. 284 285 This driver can also be built as a module. If so, the module will be 286 called reset-tn48m. 287 288config RESET_UNIPHIER 289 tristate "Reset controller driver for UniPhier SoCs" 290 depends on ARCH_UNIPHIER || COMPILE_TEST 291 depends on OF && MFD_SYSCON 292 default ARCH_UNIPHIER 293 help 294 Support for reset controllers on UniPhier SoCs. 295 Say Y if you want to control reset signals provided by System Control 296 block, Media I/O block, Peripheral Block. 297 298config RESET_UNIPHIER_GLUE 299 tristate "Reset driver in glue layer for UniPhier SoCs" 300 depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF 301 default ARCH_UNIPHIER 302 select RESET_SIMPLE 303 help 304 Support for peripheral core reset included in its own glue layer 305 on UniPhier SoCs. Say Y if you want to control reset signals 306 provided by the glue layer. 307 308config RESET_ZYNQ 309 bool "ZYNQ Reset Driver" if COMPILE_TEST 310 default ARCH_ZYNQ 311 help 312 This enables the reset controller driver for Xilinx Zynq SoCs. 313 314source "drivers/reset/starfive/Kconfig" 315source "drivers/reset/sti/Kconfig" 316source "drivers/reset/hisilicon/Kconfig" 317source "drivers/reset/tegra/Kconfig" 318 319endif 320