xref: /linux/drivers/reset/Kconfig (revision f35f83208c7735a3ed03629f934bb7ebbcf2ddf9)
1# SPDX-License-Identifier: GPL-2.0-only
2config ARCH_HAS_RESET_CONTROLLER
3	bool
4
5menuconfig RESET_CONTROLLER
6	bool "Reset Controller Support"
7	default y if ARCH_HAS_RESET_CONTROLLER
8	help
9	  Generic Reset Controller support.
10
11	  This framework is designed to abstract reset handling of devices
12	  via GPIOs or SoC-internal reset controller modules.
13
14	  If unsure, say no.
15
16if RESET_CONTROLLER
17
18config RESET_A10SR
19	tristate "Altera Arria10 System Resource Reset"
20	depends on MFD_ALTERA_A10SR || COMPILE_TEST
21	help
22	  This option enables support for the external reset functions for
23	  peripheral PHYs on the Altera Arria10 System Resource Chip.
24
25config RESET_ASPEED
26	tristate "ASPEED Reset Driver"
27	depends on ARCH_ASPEED || COMPILE_TEST
28	select AUXILIARY_BUS
29	help
30	  This enables the reset controller driver for AST2700.
31
32config RESET_ATH79
33	bool "AR71xx Reset Driver" if COMPILE_TEST
34	default ATH79
35	help
36	  This enables the ATH79 reset controller driver that supports the
37	  AR71xx SoC reset controller.
38
39config RESET_AXS10X
40	bool "AXS10x Reset Driver" if COMPILE_TEST
41	default ARC_PLAT_AXS10X
42	help
43	  This enables the reset controller driver for AXS10x.
44
45config RESET_BCM6345
46	bool "BCM6345 Reset Controller"
47	depends on BMIPS_GENERIC || COMPILE_TEST
48	default BMIPS_GENERIC
49	help
50	  This enables the reset controller driver for BCM6345 SoCs.
51
52config RESET_BERLIN
53	tristate "Berlin Reset Driver"
54	depends on ARCH_BERLIN || COMPILE_TEST
55	default m if ARCH_BERLIN
56	help
57	  This enables the reset controller driver for Marvell Berlin SoCs.
58
59config RESET_BRCMSTB
60	tristate "Broadcom STB reset controller"
61	depends on ARCH_BRCMSTB || ARCH_BCM2835 || COMPILE_TEST
62	default ARCH_BRCMSTB || ARCH_BCM2835
63	help
64	  This enables the reset controller driver for Broadcom STB SoCs using
65	  a SUN_TOP_CTRL_SW_INIT style controller.
66
67config RESET_BRCMSTB_RESCAL
68	tristate "Broadcom STB RESCAL reset controller"
69	depends on HAS_IOMEM
70	depends on ARCH_BRCMSTB || ARCH_BCM2835 || COMPILE_TEST
71	default ARCH_BRCMSTB || ARCH_BCM2835
72	help
73	  This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on
74	  BCM7216 or the BCM2712.
75
76config RESET_EYEQ
77	bool "Mobileye EyeQ reset controller"
78	depends on MACH_EYEQ5 || MACH_EYEQ6H || COMPILE_TEST
79	select AUXILIARY_BUS
80	default MACH_EYEQ5 || MACH_EYEQ6H
81	help
82	  This enables the Mobileye EyeQ reset controller, used in EyeQ5, EyeQ6L
83	  and EyeQ6H SoCs.
84
85	  It has one or more domains, with a varying number of resets in each.
86	  Registers are located in a shared register region called OLB. EyeQ6H
87	  has multiple reset instances.
88
89config RESET_GPIO
90	tristate "GPIO reset controller"
91	depends on GPIOLIB
92	help
93	  This enables a generic reset controller for resets attached via
94	  GPIOs.  Typically for OF platforms this driver expects "reset-gpios"
95	  property.
96
97	  If compiled as module, it will be called reset-gpio.
98
99config RESET_HSDK
100	bool "Synopsys HSDK Reset Driver"
101	depends on HAS_IOMEM
102	depends on ARC_SOC_HSDK || COMPILE_TEST
103	help
104	  This enables the reset controller driver for HSDK board.
105
106config RESET_IMX_SCU
107	tristate "i.MX8Q Reset Driver"
108	depends on IMX_SCU && HAVE_ARM_SMCCC
109	depends on (ARM64 && ARCH_MXC) || COMPILE_TEST
110	help
111          This enables the reset controller driver for i.MX8QM/i.MX8QXP
112
113config RESET_IMX7
114	tristate "i.MX7/8 Reset Driver"
115	depends on HAS_IOMEM
116	depends on SOC_IMX7D || (ARM64 && ARCH_MXC) || COMPILE_TEST
117	default y if SOC_IMX7D
118	select MFD_SYSCON
119	help
120	  This enables the reset controller driver for i.MX7 SoCs.
121
122config RESET_IMX8MP_AUDIOMIX
123	tristate "i.MX8MP AudioMix Reset Driver"
124	depends on ARCH_MXC || COMPILE_TEST
125	select AUXILIARY_BUS
126	default CLK_IMX8MP
127	help
128	  This enables the reset controller driver for i.MX8MP AudioMix
129
130config RESET_INTEL_GW
131	bool "Intel Reset Controller Driver"
132	depends on X86 || COMPILE_TEST
133	depends on OF && HAS_IOMEM
134	select REGMAP_MMIO
135	help
136	  This enables the reset controller driver for Intel Gateway SoCs.
137	  Say Y to control the reset signals provided by reset controller.
138	  Otherwise, say N.
139
140config RESET_K210
141	bool "Reset controller driver for Canaan Kendryte K210 SoC"
142	depends on (SOC_CANAAN_K210 || COMPILE_TEST) && OF
143	select MFD_SYSCON
144	default SOC_CANAAN_K210
145	help
146	  Support for the Canaan Kendryte K210 RISC-V SoC reset controller.
147	  Say Y if you want to control reset signals provided by this
148	  controller.
149
150config RESET_K230
151	tristate "Reset controller driver for Canaan Kendryte K230 SoC"
152	depends on ARCH_CANAAN || COMPILE_TEST
153	depends on OF
154	help
155	  Support for the Canaan Kendryte K230 RISC-V SoC reset controller.
156	  Say Y if you want to control reset signals provided by this
157	  controller.
158
159config RESET_LANTIQ
160	bool "Lantiq XWAY Reset Driver" if COMPILE_TEST
161	default SOC_TYPE_XWAY
162	help
163	  This enables the reset controller driver for Lantiq / Intel XWAY SoCs.
164
165config RESET_LPC18XX
166	bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST
167	default ARCH_LPC18XX
168	help
169	  This enables the reset controller driver for NXP LPC18xx/43xx SoCs.
170
171config RESET_MCHP_SPARX5
172	tristate "Microchip Sparx5 reset driver"
173	depends on ARCH_SPARX5 || SOC_LAN966 || MCHP_LAN966X_PCI || COMPILE_TEST
174	default y if SPARX5_SWITCH
175	select MFD_SYSCON
176	help
177	  This driver supports switch core reset for the Microchip Sparx5 SoC.
178
179config RESET_NPCM
180	bool "NPCM BMC Reset Driver" if COMPILE_TEST
181	default ARCH_NPCM
182	select AUXILIARY_BUS
183	help
184	  This enables the reset controller driver for Nuvoton NPCM
185	  BMC SoCs.
186
187config RESET_NUVOTON_MA35D1
188	bool "Nuvoton MA35D1 Reset Driver"
189	depends on ARCH_MA35 || COMPILE_TEST
190	default ARCH_MA35
191	help
192	  This enables the reset controller driver for Nuvoton MA35D1 SoC.
193
194config RESET_PISTACHIO
195	bool "Pistachio Reset Driver"
196	depends on MIPS || COMPILE_TEST
197	help
198	  This enables the reset driver for ImgTec Pistachio SoCs.
199
200config RESET_POLARFIRE_SOC
201	bool "Microchip PolarFire SoC (MPFS) Reset Driver"
202	depends on MCHP_CLK_MPFS
203	select AUXILIARY_BUS
204	default MCHP_CLK_MPFS
205	help
206	  This driver supports peripheral reset for the Microchip PolarFire SoC
207
208config RESET_QCOM_AOSS
209	tristate "Qcom AOSS Reset Driver"
210	depends on ARCH_QCOM || COMPILE_TEST
211	help
212	  This enables the AOSS (always on subsystem) reset driver
213	  for Qualcomm SDM845 SoCs. Say Y if you want to control
214	  reset signals provided by AOSS for Modem, Venus, ADSP,
215	  GPU, Camera, Wireless, Display subsystem. Otherwise, say N.
216
217config RESET_QCOM_PDC
218	tristate "Qualcomm PDC Reset Driver"
219	depends on ARCH_QCOM || COMPILE_TEST
220	help
221	  This enables the PDC (Power Domain Controller) reset driver
222	  for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want
223	  to control reset signals provided by PDC for Modem, Compute,
224	  Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS.
225
226config RESET_RASPBERRYPI
227	tristate "Raspberry Pi 4 Firmware Reset Driver"
228	depends on RASPBERRYPI_FIRMWARE || (RASPBERRYPI_FIRMWARE=n && COMPILE_TEST)
229	default USB_XHCI_PCI
230	help
231	  Raspberry Pi 4's co-processor controls some of the board's HW
232	  initialization process, but it's up to Linux to trigger it when
233	  relevant. This driver provides a reset controller capable of
234	  interfacing with RPi4's co-processor and model these firmware
235	  initialization routines as reset lines.
236
237config RESET_RZG2L_USBPHY_CTRL
238	tristate "Renesas RZ/G2L USBPHY control driver"
239	depends on ARCH_RZG2L || COMPILE_TEST
240	help
241	  Support for USBPHY Control found on RZ/G2L family. It mainly
242	  controls reset and power down of the USB/PHY.
243
244config RESET_RZV2H_USB2PHY
245	tristate "Renesas RZ/V2H(P) (and similar SoCs) USB2PHY Reset driver"
246	depends on ARCH_RENESAS || COMPILE_TEST
247	help
248	  Support for USB2PHY Port reset Control found on the RZ/V2H(P) SoC
249	  (and similar SoCs).
250
251config RESET_SCMI
252	tristate "Reset driver controlled via ARM SCMI interface"
253	depends on ARM_SCMI_PROTOCOL || COMPILE_TEST
254	default ARM_SCMI_PROTOCOL
255	help
256	  This driver provides support for reset signal/domains that are
257	  controlled by firmware that implements the SCMI interface.
258
259	  This driver uses SCMI Message Protocol to interact with the
260	  firmware controlling all the reset signals.
261
262config RESET_SIMPLE
263	bool "Simple Reset Controller Driver" if COMPILE_TEST || EXPERT
264	default ARCH_ASPEED || ARCH_BCMBCA || ARCH_BITMAIN || ARCH_REALTEK || ARCH_SOPHGO || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC
265	depends on HAS_IOMEM
266	help
267	  This enables a simple reset controller driver for reset lines that
268	  that can be asserted and deasserted by toggling bits in a contiguous,
269	  exclusive register space.
270
271	  Currently this driver supports:
272	   - Altera SoCFPGAs
273	   - ASPEED BMC SoCs
274	   - Bitmain BM1880 SoC
275	   - Realtek SoCs
276	   - RCC reset controller in STM32 MCUs
277	   - Allwinner SoCs
278	   - SiFive FU740 SoCs
279	   - Sophgo SoCs
280
281config RESET_SOCFPGA
282	bool "SoCFPGA Reset Driver" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFPGA)
283	default ARM && ARCH_INTEL_SOCFPGA
284	select RESET_SIMPLE
285	help
286	  This enables the reset driver for the SoCFPGA ARMv7 platforms. This
287	  driver gets initialized early during platform init calls.
288
289config RESET_SPACEMIT
290	tristate "SpacemiT reset driver"
291	depends on ARCH_SPACEMIT || COMPILE_TEST
292	select AUXILIARY_BUS
293	default ARCH_SPACEMIT
294	help
295	  This enables the reset controller driver for SpacemiT SoCs,
296	  including the K1.
297
298config RESET_SUNPLUS
299	bool "Sunplus SoCs Reset Driver" if COMPILE_TEST
300	default ARCH_SUNPLUS
301	help
302	  This enables the reset driver support for Sunplus SoCs.
303	  The reset lines that can be asserted and deasserted by toggling bits
304	  in a contiguous, exclusive register space. The register is HIWORD_MASKED,
305	  which means each register holds 16 reset lines.
306
307config RESET_SUNXI
308	bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI
309	default ARCH_SUNXI
310	select RESET_SIMPLE
311	help
312	  This enables the reset driver for Allwinner SoCs.
313
314config RESET_TH1520
315	tristate "T-HEAD TH1520 reset controller"
316	depends on ARCH_THEAD || COMPILE_TEST
317	select REGMAP_MMIO
318	help
319	  This driver provides support for the T-HEAD TH1520 SoC reset controller,
320	  which manages hardware reset lines for SoC components such as the GPU.
321	  Enable this option if you need to control hardware resets on TH1520-based
322	  systems.
323
324config RESET_TI_SCI
325	tristate "TI System Control Interface (TI-SCI) reset driver"
326	depends on TI_SCI_PROTOCOL || (COMPILE_TEST && TI_SCI_PROTOCOL=n)
327	help
328	  This enables the reset driver support over TI System Control Interface
329	  available on some new TI's SoCs. If you wish to use reset resources
330	  managed by the TI System Controller, say Y here. Otherwise, say N.
331
332config RESET_TI_SYSCON
333	tristate "TI SYSCON Reset Driver"
334	depends on HAS_IOMEM
335	select MFD_SYSCON
336	help
337	  This enables the reset driver support for TI devices with
338	  memory-mapped reset registers as part of a syscon device node. If
339	  you wish to use the reset framework for such memory-mapped devices,
340	  say Y here. Otherwise, say N.
341
342config RESET_TI_TPS380X
343	tristate "TI TPS380x Reset Driver"
344	select GPIOLIB
345	help
346	  This enables the reset driver support for TI TPS380x devices. If
347	  you wish to use the reset framework for such devices, say Y here.
348	  Otherwise, say N.
349
350config RESET_TN48M_CPLD
351	tristate "Delta Networks TN48M switch CPLD reset controller"
352	depends on MFD_TN48M_CPLD || COMPILE_TEST
353	default MFD_TN48M_CPLD
354	help
355	  This enables the reset controller driver for the Delta TN48M CPLD.
356	  It provides reset signals for Armada 7040 and 385 SoC-s, Alleycat 3X
357	  switch MAC-s, Alaska OOB ethernet PHY, Quad Alaska ethernet PHY-s and
358	  Microchip PD69200 PoE PSE controller.
359
360	  This driver can also be built as a module. If so, the module will be
361	  called reset-tn48m.
362
363config RESET_UNIPHIER
364	tristate "Reset controller driver for UniPhier SoCs"
365	depends on ARCH_UNIPHIER || COMPILE_TEST
366	depends on OF && MFD_SYSCON
367	default ARCH_UNIPHIER
368	help
369	  Support for reset controllers on UniPhier SoCs.
370	  Say Y if you want to control reset signals provided by System Control
371	  block, Media I/O block, Peripheral Block.
372
373config RESET_UNIPHIER_GLUE
374	tristate "Reset driver in glue layer for UniPhier SoCs"
375	depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF
376	default ARCH_UNIPHIER
377	select RESET_SIMPLE
378	help
379	  Support for peripheral core reset included in its own glue layer
380	  on UniPhier SoCs. Say Y if you want to control reset signals
381	  provided by the glue layer.
382
383config RESET_ZYNQ
384	bool "ZYNQ Reset Driver" if COMPILE_TEST
385	default ARCH_ZYNQ
386	help
387	  This enables the reset controller driver for Xilinx Zynq SoCs.
388
389config RESET_ZYNQMP
390	bool "ZYNQMP Reset Driver" if COMPILE_TEST
391	default ARCH_ZYNQMP
392	help
393	  This enables the reset controller driver for Xilinx ZynqMP SoCs.
394
395source "drivers/reset/amlogic/Kconfig"
396source "drivers/reset/starfive/Kconfig"
397source "drivers/reset/sti/Kconfig"
398source "drivers/reset/hisilicon/Kconfig"
399source "drivers/reset/tegra/Kconfig"
400
401endif
402