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Searched refs:CCI_REG8 (Results 1 – 25 of 25) sorted by relevance

/linux/drivers/media/i2c/
H A Dov64a40.c40 #define OV64A40_PLL1_PRE_DIV0 CCI_REG8(0x0301)
41 #define OV64A40_PLL1_PRE_DIV CCI_REG8(0x0303)
43 #define OV64A40_PLL1_M_DIV CCI_REG8(0x0307)
44 #define OV64A40_PLL2_SEL_BAK_SA1 CCI_REG8(0x0320)
45 #define OV64A40_PLL2_PRE_DIV CCI_REG8(0x0323)
47 #define OV64A40_PLL2_PRE_DIV0 CCI_REG8(0x0326)
48 #define OV64A40_PLL2_DIVDAC CCI_REG8(0x0329)
49 #define OV64A40_PLL2_DIVSP CCI_REG8(0x032d)
50 #define OV64A40_PLL2_DACPREDIV CCI_REG8(0x032e)
80 #define OV64A40_REG_TIMING_CTRL14 CCI_REG8(0x3814)
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H A Dgc2145.c39 #define GC2145_REG_ANALOG_MODE1 CCI_REG8(0x17)
40 #define GC2145_REG_OUTPUT_FMT CCI_REG8(0x84)
41 #define GC2145_REG_SYNC_MODE CCI_REG8(0x86)
44 #define GC2145_REG_BYPASS_MODE CCI_REG8(0x89)
46 #define GC2145_REG_DEBUG_MODE2 CCI_REG8(0x8c)
47 #define GC2145_REG_DEBUG_MODE3 CCI_REG8(0x8d)
48 #define GC2145_REG_CROP_ENABLE CCI_REG8(0x90)
53 #define GC2145_REG_GLOBAL_GAIN CCI_REG8(0xb0)
55 #define GC2145_REG_PAD_IO CCI_REG8(0xf2)
56 #define GC2145_REG_PAGE_SELECT CCI_REG8(0xfe)
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H A Dgc05a2.c31 #define GC05A2_REG_TEST_PATTERN_EN CCI_REG8(0x008c)
32 #define GC05A2_REG_TEST_PATTERN_IDX CCI_REG8(0x008d)
35 #define GC05A2_STREAMING_REG CCI_REG8(0x0100)
37 #define GC05A2_FLIP_REG CCI_REG8(0x0101)
117 { CCI_REG8(0x0135), 0x01 },
118 { CCI_REG8(0x0084), 0x21 },
119 { CCI_REG8(0x0d05), 0xcc },
120 { CCI_REG8(0x0218), 0x00 },
121 { CCI_REG8(0x005e), 0x48 },
122 { CCI_REG8(0x0d06), 0x01 },
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H A Dgc08a3.c31 #define GC08A3_REG_TEST_PATTERN_EN CCI_REG8(0x008c)
32 #define GC08A3_REG_TEST_PATTERN_IDX CCI_REG8(0x008d)
35 #define GC08A3_STREAMING_REG CCI_REG8(0x0100)
37 #define GC08A3_FLIP_REG CCI_REG8(0x0101)
114 { CCI_REG8(0x0336), 0x70 },
115 { CCI_REG8(0x0383), 0xbb },
116 { CCI_REG8(0x0344), 0x00 },
117 { CCI_REG8(0x0345), 0x06 },
118 { CCI_REG8(0x0346), 0x00 },
119 { CCI_REG8(0x0347), 0x04 },
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H A Dgc0308.c26 #define GC0308_CHIP_ID CCI_REG8(0x000)
27 #define GC0308_HBLANK CCI_REG8(0x001)
28 #define GC0308_VBLANK CCI_REG8(0x002)
34 #define GC0308_VS_START_TIME CCI_REG8(0x00d) /* in rows */
35 #define GC0308_VS_END_TIME CCI_REG8(0x00e) /* in rows */
36 #define GC0308_VB_HB CCI_REG8(0x00f)
37 #define GC0308_RSH_WIDTH CCI_REG8(0x010)
38 #define GC0308_TSP_WIDTH CCI_REG8(0x011)
39 #define GC0308_SAMPLE_HOLD_DELAY CCI_REG8(0x012)
40 #define GC0308_ROW_TAIL_WIDTH CCI_REG8(0x013)
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H A Dov5693.c32 #define OV5693_SW_RESET_REG CCI_REG8(0x0103)
33 #define OV5693_SW_STREAM_REG CCI_REG8(0x0100)
85 #define OV5693_SUB_INC_X_REG CCI_REG8(0x3814)
86 #define OV5693_SUB_INC_Y_REG CCI_REG8(0x3815)
88 #define OV5693_FORMAT1_REG CCI_REG8(0x3820)
92 #define OV5693_FORMAT2_REG CCI_REG8(0x3821)
98 #define OV5693_ISP_CTRL2_REG CCI_REG8(0x5002)
114 #define OV5693_TEST_PATTERN_REG CCI_REG8(0x5e00)
176 {CCI_REG8(0x3016), 0xf0},
177 {CCI_REG8(0x3017), 0xf0},
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H A Dimx335.c22 #define IMX335_REG_MODE_SELECT CCI_REG8(0x3000)
27 #define IMX335_REG_HOLD CCI_REG8(0x3001)
29 #define IMX335_REG_MASTER_MODE CCI_REG8(0x3002)
30 #define IMX335_REG_BCWAIT_TIME CCI_REG8(0x300c)
31 #define IMX335_REG_CPWAIT_TIME CCI_REG8(0x300d)
32 #define IMX335_REG_WINMODE CCI_REG8(0x3018)
34 #define IMX335_REG_HNUM CCI_REG8(0x302e)
39 #define IMX335_REG_OPB_SIZE_V CCI_REG8(0x304c)
40 #define IMX335_REG_ADBIT CCI_REG8(0x3050)
53 #define IMX335_REG_GAIN CCI_REG8(0x30e8)
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H A Dov4689.c23 #define OV4689_REG_CTRL_MODE CCI_REG8(0x0100)
61 #define OV4689_REG_TIMING_FORMAT1 CCI_REG8(0x3820) /* Vertical */
62 #define OV4689_REG_TIMING_FORMAT2 CCI_REG8(0x3821) /* Horizontal */
78 #define OV4689_REG_VFIFO_CTRL_01 CCI_REG8(0x4601)
87 #define OV4689_REG_TEST_PATTERN CCI_REG8(0x5040)
160 { CCI_REG8(0x0103), 0x01 }, /* SC_CTRL0103 software_reset = 1 */
161 { CCI_REG8(0x3000), 0x20 }, /* SC_CMMN_PAD_OEN0 FSIN_output_enable = 1 */
162 { CCI_REG8(0x3021), 0x03 }, /*
168 { CCI_REG8(0x3503), 0x04 }, /* AEC_MANUAL gain_input_as_sensor_gain_format = 1 */
171 { CCI_REG8(0x3603), 0x40 },
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H A Dimx415.c32 #define IMX415_MODE CCI_REG8(0x3000)
35 #define IMX415_REGHOLD CCI_REG8(0x3001)
38 #define IMX415_XMSTA CCI_REG8(0x3002)
43 #define IMX415_WINMODE CCI_REG8(0x301c)
44 #define IMX415_ADDMODE CCI_REG8(0x3022)
45 #define IMX415_REVERSE CCI_REG8(0x3030)
48 #define IMX415_ADBIT CCI_REG8(0x3031)
49 #define IMX415_MDBIT CCI_REG8(0x3032)
50 #define IMX415_SYS_MODE CCI_REG8(0x3033)
51 #define IMX415_OUTSEL CCI_REG8(0x30c0)
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H A Dimx258.c17 #define IMX258_REG_MODE_SELECT CCI_REG8(0x0100)
21 #define IMX258_REG_RESET CCI_REG8(0x0103)
62 #define IMX258_REG_HDR CCI_REG8(0x0220)
64 #define IMX258_REG_HDR_RATIO CCI_REG8(0x0222)
73 #define IMX258_CLK_BLANK_STOP CCI_REG8(0x4040)
76 #define REG_MIRROR_FLIP_CONTROL CCI_REG8(0x0101)
89 #define IMX258_REG_PLL_MULT_DRIV CCI_REG8(0x0310)
90 #define IMX258_REG_IVTPXCK_DIV CCI_REG8(0x0301)
91 #define IMX258_REG_IVTSYCK_DIV CCI_REG8(0x0303)
92 #define IMX258_REG_PREPLLCK_VT_DIV CCI_REG8(0x0305)
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H A Dimx290.c31 #define IMX290_STANDBY CCI_REG8(0x3000)
32 #define IMX290_REGHOLD CCI_REG8(0x3001)
33 #define IMX290_XMSTA CCI_REG8(0x3002)
34 #define IMX290_ADBIT CCI_REG8(0x3005)
37 #define IMX290_CTRL_07 CCI_REG8(0x3007)
43 #define IMX290_FR_FDG_SEL CCI_REG8(0x3009)
45 #define IMX290_GAIN CCI_REG8(0x3014)
51 #define IMX290_WINWV_OB CCI_REG8(0x303a)
56 #define IMX290_OUT_CTRL CCI_REG8(0x3046)
63 #define IMX290_XSOUTSEL CCI_REG8(0x304b)
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H A Dimx219.c37 #define IMX219_REG_MODE_SELECT CCI_REG8(0x0100)
41 #define IMX219_REG_CSI_LANE_MODE CCI_REG8(0x0114)
45 #define IMX219_REG_DPHY_CTRL CCI_REG8(0x0128)
53 #define IMX219_REG_ANALOG_GAIN CCI_REG8(0x0157)
89 #define IMX219_REG_X_ODD_INC_A CCI_REG8(0x0170)
90 #define IMX219_REG_Y_ODD_INC_A CCI_REG8(0x0171)
91 #define IMX219_REG_ORIENTATION CCI_REG8(0x0172)
94 #define IMX219_REG_BINNING_MODE_H CCI_REG8(0x0174)
95 #define IMX219_REG_BINNING_MODE_V CCI_REG8(0x0175)
103 #define IMX219_REG_VTPXCK_DIV CCI_REG8(0x0301)
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H A Dimx283.c40 #define IMX283_REG_CHIP_ID CCI_REG8(0x3000)
43 #define IMX283_REG_STANDBY CCI_REG8(0x3000)
51 #define IMX283_REG_CLAMP CCI_REG8(0x3001)
54 #define IMX283_REG_PLSTMG08 CCI_REG8(0x3003)
57 #define IMX283_REG_MDSEL1 CCI_REG8(0x3004)
58 #define IMX283_REG_MDSEL2 CCI_REG8(0x3005)
59 #define IMX283_REG_MDSEL3 CCI_REG8(0x3006)
61 #define IMX283_REG_MDSEL4 CCI_REG8(0x3007)
66 #define IMX283_REG_HTRIMMING CCI_REG8(0x300b)
76 #define IMX283_REG_TCLKPOST CCI_REG8(0x3018)
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H A Dmt9m114.c78 #define MT9M114_AE_TRACK_AE_TRACKING_DAMPENING_SPEED CCI_REG8(0xa80a)
83 #define MT9M114_CCM_DELTA_GAIN CCI_REG8(0xb42a)
116 #define MT9M114_CAM_MODE_SELECT CCI_REG8(0xc84c)
120 #define MT9M114_CAM_MODE_TEST_PATTERN_SELECT CCI_REG8(0xc84d)
134 #define MT9M114_CAM_CROP_CROPMODE CCI_REG8(0xc85c)
169 #define MT9M114_CAM_OUTPUT_Y_OFFSET CCI_REG8(0xc870)
170 #define MT9M114_CAM_AET_AEMODE CCI_REG8(0xc878)
175 #define MT9M114_CAM_AET_SKIP_FRAMES CCI_REG8(0xc879)
176 #define MT9M114_CAM_AET_TARGET_AVERAGE_LUMA CCI_REG8(0xc87a)
177 #define MT9M114_CAM_AET_TARGET_AVERAGE_LUMA_DARK CCI_REG8(0xc87b)
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H A Dmax96717.c33 #define MAX96717_REG3 CCI_REG8(0x3)
35 #define RCLKSEL_REF_PLL CCI_REG8(0x3)
36 #define MAX96717_REG6 CCI_REG8(0x6)
38 #define MAX96717_DEV_ID CCI_REG8(0xd)
39 #define MAX96717_DEV_REV CCI_REG8(0xe)
43 #define MAX96717_VIDEO_TX0 CCI_REG8(0x110)
45 #define MAX96717_VIDEO_TX2 CCI_REG8(0x112)
49 #define MAX96717_VTX0 CCI_REG8(0x24e)
50 #define MAX96717_VTX1 CCI_REG8(0x24f)
63 #define MAX96717_VTX29 CCI_REG8(0x26b)
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H A Dmax96714.c31 #define MAX96714_REG13 CCI_REG8(0x0d)
32 #define MAX96714_DEV_REV CCI_REG8(0x0e)
34 #define MAX96714_LINK_LOCK CCI_REG8(0x13)
36 #define MAX96714_IO_CHK0 CCI_REG8(0x38)
39 #define MAX96714_VIDEO_RX8 CCI_REG8(0x11a)
43 #define MAX96714_PATGEN_0 CCI_REG8(0x240)
44 #define MAX96714_PATGEN_1 CCI_REG8(0x241)
57 #define MAX96714_PATGEN_GRAD_INC CCI_REG8(0x25d)
60 #define MAX96714_PATGEN_CHKB_RPT_CNT_A CCI_REG8(0x264)
61 #define MAX96714_PATGEN_CHKB_RPT_CNT_B CCI_REG8(0x265)
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H A Dthp7312.c38 #define THP7312_REG_FIRMWARE_VERSION_1 CCI_REG8(0xf000)
39 #define THP7312_REG_CAMERA_STATUS CCI_REG8(0xf001)
40 #define THP7312_REG_FIRMWARE_VERSION_2 CCI_REG8(0xf005)
41 #define THP7312_REG_SET_OUTPUT_ENABLE CCI_REG8(0xf008)
44 #define THP7312_REG_SET_OUTPUT_COLOR_COMPRESSION CCI_REG8(0xf009)
47 #define THP7312_REG_FLIP_MIRROR CCI_REG8(0xf00c)
50 #define THP7312_REG_VIDEO_IMAGE_SIZE CCI_REG8(0xf00d)
59 #define THP7312_REG_VIDEO_FRAME_RATE_MODE CCI_REG8(0xf00f)
63 #define THP7312_REG_SET_DRIVING_MODE CCI_REG8(0xf010)
64 #define THP7312_REG_DRIVING_MODE_STATUS CCI_REG8(0xf011)
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H A Dst-mipid02.c27 #define MIPID02_CLK_LANE_WR_REG1 CCI_REG8(0x01)
28 #define MIPID02_CLK_LANE_REG1 CCI_REG8(0x02)
29 #define MIPID02_CLK_LANE_REG3 CCI_REG8(0x04)
30 #define MIPID02_DATA_LANE0_REG1 CCI_REG8(0x05)
31 #define MIPID02_DATA_LANE0_REG2 CCI_REG8(0x06)
32 #define MIPID02_DATA_LANE1_REG1 CCI_REG8(0x09)
33 #define MIPID02_DATA_LANE1_REG2 CCI_REG8(0x0a)
34 #define MIPID02_MODE_REG1 CCI_REG8(0x14)
35 #define MIPID02_MODE_REG2 CCI_REG8(0x15)
36 #define MIPID02_DATA_ID_RREG CCI_REG8(0x17)
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H A Dvgxy61.c35 #define VGXY61_REG_FWPATCH_START_ADDR CCI_REG8(0x2000)
36 #define VGXY61_REG_SYSTEM_FSM CCI_REG8(0x0020)
39 #define VGXY61_REG_NVM CCI_REG8(0x0023)
41 #define VGXY61_REG_STBY CCI_REG8(0x0201)
44 #define VGXY61_REG_STREAMING CCI_REG8(0x0202)
49 #define VGXY61_REG_CLK_PLL_PREDIV CCI_REG8(0x0224)
50 #define VGXY61_REG_CLK_SYS_PLL_MULT CCI_REG8(0x0225)
51 #define VGXY61_REG_GPIO_0_CTRL CCI_REG8(0x0236)
52 #define VGXY61_REG_GPIO_1_CTRL CCI_REG8(0x0237)
53 #define VGXY61_REG_GPIO_2_CTRL CCI_REG8(0x0238)
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H A Dalvium-csi2.h23 #define REG_BCRM_V4L2_8BIT(n) (REG_BCRM_V4L2 | CCI_REG8(n))
185 #define REG_BCRM_HEARTBEAT_RW CCI_REG8(0x021f)
188 #define REG_GENCP_CHANGEMODE_W CCI_REG8(0x021c)
189 #define REG_GENCP_CURRENTMODE_R CCI_REG8(0x021d)
190 #define REG_GENCP_IN_HANDSHAKE_RW CCI_REG8(0x001c)
H A Ddw9719.c24 #define DW9719_INFO CCI_REG8(0)
27 #define DW9719_CONTROL CCI_REG8(2)
32 #define DW9719_MODE CCI_REG8(6)
36 #define DW9719_VCM_FREQ CCI_REG8(7)
H A Dov2680.c33 #define OV2680_REG_STREAM_CTRL CCI_REG8(0x0100)
34 #define OV2680_REG_SOFT_RESET CCI_REG8(0x0103)
37 #define OV2680_REG_SC_CMMN_SUB_ID CCI_REG8(0x302a)
41 #define OV2680_REG_R_MANUAL CCI_REG8(0x3503)
44 #define OV2680_REG_SENSOR_CTRL_0A CCI_REG8(0x370a)
56 #define OV2680_REG_X_INC CCI_REG8(0x3814)
57 #define OV2680_REG_Y_INC CCI_REG8(0x3815)
58 #define OV2680_REG_FORMAT1 CCI_REG8(0x3820)
59 #define OV2680_REG_FORMAT2 CCI_REG8(0x3821)
61 #define OV2680_REG_ISP_CTRL00 CCI_REG8(0x5080)
/linux/drivers/media/i2c/ccs/
H A Dsmiapp-reg-defs.h20 #define SMIAPP_REG_U8_REVISION_NUMBER_MAJOR CCI_REG8(0x0002)
21 #define SMIAPP_REG_U8_MANUFACTURER_ID CCI_REG8(0x0003)
22 #define SMIAPP_REG_U8_SMIA_VERSION CCI_REG8(0x0004)
23 #define SMIAPP_REG_U8_FRAME_COUNT CCI_REG8(0x0005)
24 #define SMIAPP_REG_U8_PIXEL_ORDER CCI_REG8(0x0006)
26 #define SMIAPP_REG_U8_PIXEL_DEPTH CCI_REG8(0x000c)
27 #define SMIAPP_REG_U8_REVISION_NUMBER_MINOR CCI_REG8(0x0010)
28 #define SMIAPP_REG_U8_SMIAPP_VERSION CCI_REG8(0x0011)
29 #define SMIAPP_REG_U8_MODULE_DATE_YEAR CCI_REG8(0x0012)
30 #define SMIAPP_REG_U8_MODULE_DATE_MONTH CCI_REG8(0x0013)
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H A Dccs-regs.h21 #define CCS_R_MODULE_REVISION_NUMBER_MAJOR CCI_REG8(0x0002)
22 #define CCS_R_FRAME_COUNT CCI_REG8(0x0005)
23 #define CCS_R_PIXEL_ORDER CCI_REG8(0x0006)
28 #define CCS_R_MIPI_CCS_VERSION CCI_REG8(0x0007)
37 #define CCS_R_MODULE_REVISION_NUMBER_MINOR CCI_REG8(0x0010)
38 #define CCS_R_MODULE_DATE_YEAR CCI_REG8(0x0012)
39 #define CCS_R_MODULE_DATE_MONTH CCI_REG8(0x0013)
40 #define CCS_R_MODULE_DATE_DAY CCI_REG8(0x0014)
41 #define CCS_R_MODULE_DATE_PHASE CCI_REG8(0x0015)
49 #define CCS_R_SENSOR_REVISION_NUMBER CCI_REG8(0x0018)
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/linux/include/media/
H A Dv4l2-cci.h48 #define CCI_REG8(x) ((1 << CCI_REG_WIDTH_SHIFT) | (x)) macro