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Searched refs:CCI_REG8 (Results 1 – 13 of 13) sorted by relevance

/linux/drivers/media/i2c/
H A Dov64a40.c38 #define OV64A40_PLL1_PRE_DIV0 CCI_REG8(0x0301)
39 #define OV64A40_PLL1_PRE_DIV CCI_REG8(0x0303)
41 #define OV64A40_PLL1_M_DIV CCI_REG8(0x0307)
42 #define OV64A40_PLL2_SEL_BAK_SA1 CCI_REG8(0x0320)
43 #define OV64A40_PLL2_PRE_DIV CCI_REG8(0x0323)
45 #define OV64A40_PLL2_PRE_DIV0 CCI_REG8(0x0326)
46 #define OV64A40_PLL2_DIVDAC CCI_REG8(0x0329)
47 #define OV64A40_PLL2_DIVSP CCI_REG8(0x032d)
48 #define OV64A40_PLL2_DACPREDIV CCI_REG8(0x032e)
78 #define OV64A40_REG_TIMING_CTRL14 CCI_REG8(0x3814)
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H A Dgc05a2.c29 #define GC05A2_REG_TEST_PATTERN_EN CCI_REG8(0x008c)
30 #define GC05A2_REG_TEST_PATTERN_IDX CCI_REG8(0x008d)
33 #define GC05A2_STREAMING_REG CCI_REG8(0x0100)
35 #define GC05A2_FLIP_REG CCI_REG8(0x0101)
115 { CCI_REG8(0x0135), 0x01 },
116 { CCI_REG8(0x0084), 0x21 },
117 { CCI_REG8(0x0d05), 0xcc },
118 { CCI_REG8(0x0218), 0x00 },
119 { CCI_REG8(0x005e), 0x48 },
120 { CCI_REG8(0x0d06), 0x01 },
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H A Dgc08a3.c29 #define GC08A3_REG_TEST_PATTERN_EN CCI_REG8(0x008c)
30 #define GC08A3_REG_TEST_PATTERN_IDX CCI_REG8(0x008d)
33 #define GC08A3_STREAMING_REG CCI_REG8(0x0100)
35 #define GC08A3_FLIP_REG CCI_REG8(0x0101)
112 { CCI_REG8(0x0336), 0x70 },
113 { CCI_REG8(0x0383), 0xbb },
114 { CCI_REG8(0x0344), 0x00 },
115 { CCI_REG8(0x0345), 0x06 },
116 { CCI_REG8(0x0346), 0x00 },
117 { CCI_REG8(0x0347), 0x04 },
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H A Dgc0308.c24 #define GC0308_CHIP_ID CCI_REG8(0x000)
25 #define GC0308_HBLANK CCI_REG8(0x001)
26 #define GC0308_VBLANK CCI_REG8(0x002)
32 #define GC0308_VS_START_TIME CCI_REG8(0x00d) /* in rows */
33 #define GC0308_VS_END_TIME CCI_REG8(0x00e) /* in rows */
34 #define GC0308_VB_HB CCI_REG8(0x00f)
35 #define GC0308_RSH_WIDTH CCI_REG8(0x010)
36 #define GC0308_TSP_WIDTH CCI_REG8(0x011)
37 #define GC0308_SAMPLE_HOLD_DELAY CCI_REG8(0x012)
38 #define GC0308_ROW_TAIL_WIDTH CCI_REG8(0x013)
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H A Dt4ka3.c64 #define T4KA3_REG_PRODUCT_ID_HIGH CCI_REG8(0x0000)
65 #define T4KA3_REG_PRODUCT_ID_LOW CCI_REG8(0x0001)
68 #define T4KA3_REG_STREAM CCI_REG8(0x0100)
69 #define T4KA3_REG_IMG_ORIENTATION CCI_REG8(0x0101)
72 #define T4KA3_REG_PARAM_HOLD CCI_REG8(0x0104)
102 #define T4KA3_REG_TEST_PATTERN_MODE CCI_REG8(0x0601)
104 #define T4KA3_REG_0900 CCI_REG8(0x0900)
105 #define T4KA3_REG_BINNING CCI_REG8(0x0901)
156 { CCI_REG8(0x4136), 0x13 },
157 { CCI_REG8(0x4137), 0x33 },
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H A Dmt9m114.c83 #define MT9M114_AE_TRACK_AE_TRACKING_DAMPENING_SPEED CCI_REG8(0xa80a)
88 #define MT9M114_CCM_DELTA_GAIN CCI_REG8(0xb42a)
121 #define MT9M114_CAM_MODE_SELECT CCI_REG8(0xc84c)
125 #define MT9M114_CAM_MODE_TEST_PATTERN_SELECT CCI_REG8(0xc84d)
139 #define MT9M114_CAM_CROP_CROPMODE CCI_REG8(0xc85c)
174 #define MT9M114_CAM_OUTPUT_Y_OFFSET CCI_REG8(0xc870)
175 #define MT9M114_CAM_AET_AEMODE CCI_REG8(0xc878)
180 #define MT9M114_CAM_AET_SKIP_FRAMES CCI_REG8(0xc879)
181 #define MT9M114_CAM_AET_TARGET_AVERAGE_LUMA CCI_REG8(0xc87a)
182 #define MT9M114_CAM_AET_TARGET_AVERAGE_LUMA_DARK CCI_REG8(0xc87b)
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H A Dthp7312.c37 #define THP7312_REG_FIRMWARE_VERSION_1 CCI_REG8(0xf000)
38 #define THP7312_REG_CAMERA_STATUS CCI_REG8(0xf001)
39 #define THP7312_REG_FIRMWARE_VERSION_2 CCI_REG8(0xf005)
40 #define THP7312_REG_SET_OUTPUT_ENABLE CCI_REG8(0xf008)
43 #define THP7312_REG_SET_OUTPUT_COLOR_COMPRESSION CCI_REG8(0xf009)
46 #define THP7312_REG_FLIP_MIRROR CCI_REG8(0xf00c)
49 #define THP7312_REG_VIDEO_IMAGE_SIZE CCI_REG8(0xf00d)
58 #define THP7312_REG_VIDEO_FRAME_RATE_MODE CCI_REG8(0xf00f)
62 #define THP7312_REG_SET_DRIVING_MODE CCI_REG8(0xf010)
63 #define THP7312_REG_DRIVING_MODE_STATUS CCI_REG8(0xf011)
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H A Dalvium-csi2.h23 #define REG_BCRM_V4L2_8BIT(n) (REG_BCRM_V4L2 | CCI_REG8(n))
185 #define REG_BCRM_HEARTBEAT_RW CCI_REG8(0x021f)
188 #define REG_GENCP_CHANGEMODE_W CCI_REG8(0x021c)
189 #define REG_GENCP_CURRENTMODE_R CCI_REG8(0x021d)
190 #define REG_GENCP_IN_HANDSHAKE_RW CCI_REG8(0x001c)
H A Dov2680.c32 #define OV2680_REG_STREAM_CTRL CCI_REG8(0x0100)
33 #define OV2680_REG_SOFT_RESET CCI_REG8(0x0103)
36 #define OV2680_REG_SC_CMMN_SUB_ID CCI_REG8(0x302a)
40 #define OV2680_REG_R_MANUAL CCI_REG8(0x3503)
43 #define OV2680_REG_SENSOR_CTRL_0A CCI_REG8(0x370a)
55 #define OV2680_REG_X_INC CCI_REG8(0x3814)
56 #define OV2680_REG_Y_INC CCI_REG8(0x3815)
57 #define OV2680_REG_FORMAT1 CCI_REG8(0x3820)
58 #define OV2680_REG_FORMAT2 CCI_REG8(0x3821)
60 #define OV2680_REG_ISP_CTRL00 CCI_REG8(0x5080)
H A Dov02c10.c24 #define OV02C10_REG_STREAM_CONTROL CCI_REG8(0x0100)
53 #define OV02C10_ROTATE_CONTROL CCI_REG8(0x3820)
59 #define OV02C10_REG_TEST_PATTERN CCI_REG8(0x4503)
/linux/drivers/media/i2c/ccs/
H A Dsmiapp-reg-defs.h20 #define SMIAPP_REG_U8_REVISION_NUMBER_MAJOR CCI_REG8(0x0002)
21 #define SMIAPP_REG_U8_MANUFACTURER_ID CCI_REG8(0x0003)
22 #define SMIAPP_REG_U8_SMIA_VERSION CCI_REG8(0x0004)
23 #define SMIAPP_REG_U8_FRAME_COUNT CCI_REG8(0x0005)
24 #define SMIAPP_REG_U8_PIXEL_ORDER CCI_REG8(0x0006)
26 #define SMIAPP_REG_U8_PIXEL_DEPTH CCI_REG8(0x000c)
27 #define SMIAPP_REG_U8_REVISION_NUMBER_MINOR CCI_REG8(0x0010)
28 #define SMIAPP_REG_U8_SMIAPP_VERSION CCI_REG8(0x0011)
29 #define SMIAPP_REG_U8_MODULE_DATE_YEAR CCI_REG8(0x0012)
30 #define SMIAPP_REG_U8_MODULE_DATE_MONTH CCI_REG8(0x0013)
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H A Dccs-regs.h21 #define CCS_R_MODULE_REVISION_NUMBER_MAJOR CCI_REG8(0x0002)
22 #define CCS_R_FRAME_COUNT CCI_REG8(0x0005)
23 #define CCS_R_PIXEL_ORDER CCI_REG8(0x0006)
28 #define CCS_R_MIPI_CCS_VERSION CCI_REG8(0x0007)
37 #define CCS_R_MODULE_REVISION_NUMBER_MINOR CCI_REG8(0x0010)
38 #define CCS_R_MODULE_DATE_YEAR CCI_REG8(0x0012)
39 #define CCS_R_MODULE_DATE_MONTH CCI_REG8(0x0013)
40 #define CCS_R_MODULE_DATE_DAY CCI_REG8(0x0014)
41 #define CCS_R_MODULE_DATE_PHASE CCI_REG8(0x0015)
49 #define CCS_R_SENSOR_REVISION_NUMBER CCI_REG8(0x0018)
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/linux/include/media/
H A Dv4l2-cci.h48 #define CCI_REG8(x) ((1 << CCI_REG_WIDTH_SHIFT) | (x)) macro