Searched refs:CCI_REG8 (Results 1 – 7 of 7) sorted by relevance
20 #define SMIAPP_REG_U8_REVISION_NUMBER_MAJOR CCI_REG8(0x0002)21 #define SMIAPP_REG_U8_MANUFACTURER_ID CCI_REG8(0x0003)22 #define SMIAPP_REG_U8_SMIA_VERSION CCI_REG8(0x0004)23 #define SMIAPP_REG_U8_FRAME_COUNT CCI_REG8(0x0005)24 #define SMIAPP_REG_U8_PIXEL_ORDER CCI_REG8(0x0006)26 #define SMIAPP_REG_U8_PIXEL_DEPTH CCI_REG8(0x000c)27 #define SMIAPP_REG_U8_REVISION_NUMBER_MINOR CCI_REG8(0x0010)28 #define SMIAPP_REG_U8_SMIAPP_VERSION CCI_REG8(0x0011)29 #define SMIAPP_REG_U8_MODULE_DATE_YEAR CCI_REG8(0x0012)30 #define SMIAPP_REG_U8_MODULE_DATE_MONTH CCI_REG8(0x0013)[all …]
21 #define CCS_R_MODULE_REVISION_NUMBER_MAJOR CCI_REG8(0x0002)22 #define CCS_R_FRAME_COUNT CCI_REG8(0x0005)23 #define CCS_R_PIXEL_ORDER CCI_REG8(0x0006)28 #define CCS_R_MIPI_CCS_VERSION CCI_REG8(0x0007)37 #define CCS_R_MODULE_REVISION_NUMBER_MINOR CCI_REG8(0x0010)38 #define CCS_R_MODULE_DATE_YEAR CCI_REG8(0x0012)39 #define CCS_R_MODULE_DATE_MONTH CCI_REG8(0x0013)40 #define CCS_R_MODULE_DATE_DAY CCI_REG8(0x0014)41 #define CCS_R_MODULE_DATE_PHASE CCI_REG8(0x0015)49 #define CCS_R_SENSOR_REVISION_NUMBER CCI_REG8(0x0018)[all …]
25 #define GC0308_CHIP_ID CCI_REG8(0x000)26 #define GC0308_HBLANK CCI_REG8(0x001)27 #define GC0308_VBLANK CCI_REG8(0x002)33 #define GC0308_VS_START_TIME CCI_REG8(0x00d) /* in rows */34 #define GC0308_VS_END_TIME CCI_REG8(0x00e) /* in rows */35 #define GC0308_VB_HB CCI_REG8(0x00f)36 #define GC0308_RSH_WIDTH CCI_REG8(0x010)37 #define GC0308_TSP_WIDTH CCI_REG8(0x011)38 #define GC0308_SAMPLE_HOLD_DELAY CCI_REG8(0x012)39 #define GC0308_ROW_TAIL_WIDTH CCI_REG8(0x013)[all …]
37 #define THP7312_REG_FIRMWARE_VERSION_1 CCI_REG8(0xf000)38 #define THP7312_REG_CAMERA_STATUS CCI_REG8(0xf001)39 #define THP7312_REG_FIRMWARE_VERSION_2 CCI_REG8(0xf005)40 #define THP7312_REG_SET_OUTPUT_ENABLE CCI_REG8(0xf008)43 #define THP7312_REG_SET_OUTPUT_COLOR_COMPRESSION CCI_REG8(0xf009)46 #define THP7312_REG_FLIP_MIRROR CCI_REG8(0xf00c)49 #define THP7312_REG_VIDEO_IMAGE_SIZE CCI_REG8(0xf00d)58 #define THP7312_REG_VIDEO_FRAME_RATE_MODE CCI_REG8(0xf00f)62 #define THP7312_REG_SET_DRIVING_MODE CCI_REG8(0xf010)63 #define THP7312_REG_DRIVING_MODE_STATUS CCI_REG8(0xf011)[all …]
23 #define REG_BCRM_V4L2_8BIT(n) (REG_BCRM_V4L2 | CCI_REG8(n))185 #define REG_BCRM_HEARTBEAT_RW CCI_REG8(0x021f)188 #define REG_GENCP_CHANGEMODE_W CCI_REG8(0x021c)189 #define REG_GENCP_CURRENTMODE_R CCI_REG8(0x021d)190 #define REG_GENCP_IN_HANDSHAKE_RW CCI_REG8(0x001c)
24 #define OV02C10_REG_STREAM_CONTROL CCI_REG8(0x0100)53 #define OV02C10_ROTATE_CONTROL CCI_REG8(0x3820)59 #define OV02C10_REG_TEST_PATTERN CCI_REG8(0x4503)
48 #define CCI_REG8(x) ((1 << CCI_REG_WIDTH_SHIFT) | (x)) macro