Lines Matching refs:CCI_REG8
32 #define IMX415_MODE CCI_REG8(0x3000)
35 #define IMX415_REGHOLD CCI_REG8(0x3001)
38 #define IMX415_XMSTA CCI_REG8(0x3002)
43 #define IMX415_WINMODE CCI_REG8(0x301c)
44 #define IMX415_ADDMODE CCI_REG8(0x3022)
45 #define IMX415_REVERSE CCI_REG8(0x3030)
48 #define IMX415_ADBIT CCI_REG8(0x3031)
49 #define IMX415_MDBIT CCI_REG8(0x3032)
50 #define IMX415_SYS_MODE CCI_REG8(0x3033)
51 #define IMX415_OUTSEL CCI_REG8(0x30c0)
52 #define IMX415_DRV CCI_REG8(0x30c1)
62 #define IMX415_TPG_EN_DUOUT CCI_REG8(0x30e4)
63 #define IMX415_TPG_PATSEL_DUOUT CCI_REG8(0x30e6)
64 #define IMX415_TPG_COLORWIDTH CCI_REG8(0x30e8)
65 #define IMX415_TESTCLKEN_MIPI CCI_REG8(0x3110)
66 #define IMX415_INCKSEL1 CCI_REG8(0x3115)
67 #define IMX415_INCKSEL2 CCI_REG8(0x3116)
70 #define IMX415_INCKSEL5 CCI_REG8(0x311e)
71 #define IMX415_DIG_CLP_MODE CCI_REG8(0x32c8)
72 #define IMX415_WRJ_OPEN CCI_REG8(0x3390)
80 #define IMX415_INCKSEL6 CCI_REG8(0x400c)
90 #define IMX415_INCKSEL7 CCI_REG8(0x4074)
625 { CCI_REG8(0x32D4), 0x21 },
626 { CCI_REG8(0x32EC), 0xA1 },
627 { CCI_REG8(0x3452), 0x7F },
628 { CCI_REG8(0x3453), 0x03 },
629 { CCI_REG8(0x358A), 0x04 },
630 { CCI_REG8(0x35A1), 0x02 },
631 { CCI_REG8(0x36BC), 0x0C },
632 { CCI_REG8(0x36CC), 0x53 },
633 { CCI_REG8(0x36CD), 0x00 },
634 { CCI_REG8(0x36CE), 0x3C },
635 { CCI_REG8(0x36D0), 0x8C },
636 { CCI_REG8(0x36D1), 0x00 },
637 { CCI_REG8(0x36D2), 0x71 },
638 { CCI_REG8(0x36D4), 0x3C },
639 { CCI_REG8(0x36D6), 0x53 },
640 { CCI_REG8(0x36D7), 0x00 },
641 { CCI_REG8(0x36D8), 0x71 },
642 { CCI_REG8(0x36DA), 0x8C },
643 { CCI_REG8(0x36DB), 0x00 },
644 { CCI_REG8(0x3724), 0x02 },
645 { CCI_REG8(0x3726), 0x02 },
646 { CCI_REG8(0x3732), 0x02 },
647 { CCI_REG8(0x3734), 0x03 },
648 { CCI_REG8(0x3736), 0x03 },
649 { CCI_REG8(0x3742), 0x03 },
650 { CCI_REG8(0x3862), 0xE0 },
651 { CCI_REG8(0x38CC), 0x30 },
652 { CCI_REG8(0x38CD), 0x2F },
653 { CCI_REG8(0x395C), 0x0C },
654 { CCI_REG8(0x3A42), 0xD1 },
655 { CCI_REG8(0x3A4C), 0x77 },
656 { CCI_REG8(0x3AE0), 0x02 },
657 { CCI_REG8(0x3AEC), 0x0C },
658 { CCI_REG8(0x3B00), 0x2E },
659 { CCI_REG8(0x3B06), 0x29 },
660 { CCI_REG8(0x3B98), 0x25 },
661 { CCI_REG8(0x3B99), 0x21 },
662 { CCI_REG8(0x3B9B), 0x13 },
663 { CCI_REG8(0x3B9C), 0x13 },
664 { CCI_REG8(0x3B9D), 0x13 },
665 { CCI_REG8(0x3B9E), 0x13 },
666 { CCI_REG8(0x3BA1), 0x00 },
667 { CCI_REG8(0x3BA2), 0x06 },
668 { CCI_REG8(0x3BA3), 0x0B },
669 { CCI_REG8(0x3BA4), 0x10 },
670 { CCI_REG8(0x3BA5), 0x14 },
671 { CCI_REG8(0x3BA6), 0x18 },
672 { CCI_REG8(0x3BA7), 0x1A },
673 { CCI_REG8(0x3BA8), 0x1A },
674 { CCI_REG8(0x3BA9), 0x1A },
675 { CCI_REG8(0x3BAC), 0xED },
676 { CCI_REG8(0x3BAD), 0x01 },
677 { CCI_REG8(0x3BAE), 0xF6 },
678 { CCI_REG8(0x3BAF), 0x02 },
679 { CCI_REG8(0x3BB0), 0xA2 },
680 { CCI_REG8(0x3BB1), 0x03 },
681 { CCI_REG8(0x3BB2), 0xE0 },
682 { CCI_REG8(0x3BB3), 0x03 },
683 { CCI_REG8(0x3BB4), 0xE0 },
684 { CCI_REG8(0x3BB5), 0x03 },
685 { CCI_REG8(0x3BB6), 0xE0 },
686 { CCI_REG8(0x3BB7), 0x03 },
687 { CCI_REG8(0x3BB8), 0xE0 },
688 { CCI_REG8(0x3BBA), 0xE0 },
689 { CCI_REG8(0x3BBC), 0xDA },
690 { CCI_REG8(0x3BBE), 0x88 },
691 { CCI_REG8(0x3BC0), 0x44 },
692 { CCI_REG8(0x3BC2), 0x7B },
693 { CCI_REG8(0x3BC4), 0xA2 },
694 { CCI_REG8(0x3BC8), 0xBD },
695 { CCI_REG8(0x3BCA), 0xBD },