Lines Matching refs:CCI_REG8
37 #define IMX219_REG_MODE_SELECT CCI_REG8(0x0100)
41 #define IMX219_REG_CSI_LANE_MODE CCI_REG8(0x0114)
45 #define IMX219_REG_DPHY_CTRL CCI_REG8(0x0128)
53 #define IMX219_REG_ANALOG_GAIN CCI_REG8(0x0157)
89 #define IMX219_REG_X_ODD_INC_A CCI_REG8(0x0170)
90 #define IMX219_REG_Y_ODD_INC_A CCI_REG8(0x0171)
91 #define IMX219_REG_ORIENTATION CCI_REG8(0x0172)
94 #define IMX219_REG_BINNING_MODE_H CCI_REG8(0x0174)
95 #define IMX219_REG_BINNING_MODE_V CCI_REG8(0x0175)
103 #define IMX219_REG_VTPXCK_DIV CCI_REG8(0x0301)
104 #define IMX219_REG_VTSYCK_DIV CCI_REG8(0x0303)
105 #define IMX219_REG_PREPLLCK_VT_DIV CCI_REG8(0x0304)
106 #define IMX219_REG_PREPLLCK_OP_DIV CCI_REG8(0x0305)
108 #define IMX219_REG_OPPXCK_DIV CCI_REG8(0x0309)
109 #define IMX219_REG_OPSYCK_DIV CCI_REG8(0x030b)
165 { CCI_REG8(0x30eb), 0x05 },
166 { CCI_REG8(0x30eb), 0x0c },
167 { CCI_REG8(0x300a), 0xff },
168 { CCI_REG8(0x300b), 0xff },
169 { CCI_REG8(0x30eb), 0x05 },
170 { CCI_REG8(0x30eb), 0x09 },
182 { CCI_REG8(0x455e), 0x00 },
183 { CCI_REG8(0x471e), 0x4b },
184 { CCI_REG8(0x4767), 0x0f },
185 { CCI_REG8(0x4750), 0x14 },
186 { CCI_REG8(0x4540), 0x00 },
187 { CCI_REG8(0x47b4), 0x14 },
188 { CCI_REG8(0x4713), 0x30 },
189 { CCI_REG8(0x478b), 0x10 },
190 { CCI_REG8(0x478f), 0x10 },
191 { CCI_REG8(0x4793), 0x10 },
192 { CCI_REG8(0x4797), 0x0e },
193 { CCI_REG8(0x479b), 0x0e },