Lines Matching refs:CCI_REG8
17 #define IMX258_REG_MODE_SELECT CCI_REG8(0x0100)
21 #define IMX258_REG_RESET CCI_REG8(0x0103)
62 #define IMX258_REG_HDR CCI_REG8(0x0220)
64 #define IMX258_REG_HDR_RATIO CCI_REG8(0x0222)
73 #define IMX258_CLK_BLANK_STOP CCI_REG8(0x4040)
76 #define REG_MIRROR_FLIP_CONTROL CCI_REG8(0x0101)
89 #define IMX258_REG_PLL_MULT_DRIV CCI_REG8(0x0310)
90 #define IMX258_REG_IVTPXCK_DIV CCI_REG8(0x0301)
91 #define IMX258_REG_IVTSYCK_DIV CCI_REG8(0x0303)
92 #define IMX258_REG_PREPLLCK_VT_DIV CCI_REG8(0x0305)
93 #define IMX258_REG_IOPPXCK_DIV CCI_REG8(0x0309)
94 #define IMX258_REG_IOPSYCK_DIV CCI_REG8(0x030b)
95 #define IMX258_REG_PREPLLCK_OP_DIV CCI_REG8(0x030d)
96 #define IMX258_REG_PHASE_PIX_OUTEN CCI_REG8(0x3030)
97 #define IMX258_REG_PDPIX_DATA_RATE CCI_REG8(0x3032)
98 #define IMX258_REG_SCALE_MODE CCI_REG8(0x0401)
99 #define IMX258_REG_SCALE_MODE_EXT CCI_REG8(0x3038)
100 #define IMX258_REG_AF_WINDOW_MODE CCI_REG8(0x7bcd)
101 #define IMX258_REG_FRM_LENGTH_CTL CCI_REG8(0x0350)
102 #define IMX258_REG_CSI_LANE_MODE CCI_REG8(0x0114)
103 #define IMX258_REG_X_EVN_INC CCI_REG8(0x0381)
104 #define IMX258_REG_X_ODD_INC CCI_REG8(0x0383)
105 #define IMX258_REG_Y_EVN_INC CCI_REG8(0x0385)
106 #define IMX258_REG_Y_ODD_INC CCI_REG8(0x0387)
107 #define IMX258_REG_BINNING_MODE CCI_REG8(0x0900)
108 #define IMX258_REG_BINNING_TYPE_V CCI_REG8(0x0901)
109 #define IMX258_REG_FORCE_FD_SUM CCI_REG8(0x300d)
126 #define IMX258_REG_FINE_INTEG_TIME CCI_REG8(0x0200)
318 { CCI_REG8(0x3051), 0x00 },
319 { CCI_REG8(0x6B11), 0xCF },
320 { CCI_REG8(0x7FF0), 0x08 },
321 { CCI_REG8(0x7FF1), 0x0F },
322 { CCI_REG8(0x7FF2), 0x08 },
323 { CCI_REG8(0x7FF3), 0x1B },
324 { CCI_REG8(0x7FF4), 0x23 },
325 { CCI_REG8(0x7FF5), 0x60 },
326 { CCI_REG8(0x7FF6), 0x00 },
327 { CCI_REG8(0x7FF7), 0x01 },
328 { CCI_REG8(0x7FF8), 0x00 },
329 { CCI_REG8(0x7FF9), 0x78 },
330 { CCI_REG8(0x7FFA), 0x00 },
331 { CCI_REG8(0x7FFB), 0x00 },
332 { CCI_REG8(0x7FFC), 0x00 },
333 { CCI_REG8(0x7FFD), 0x00 },
334 { CCI_REG8(0x7FFE), 0x00 },
335 { CCI_REG8(0x7FFF), 0x03 },
336 { CCI_REG8(0x7F76), 0x03 },
337 { CCI_REG8(0x7F77), 0xFE },
338 { CCI_REG8(0x7FA8), 0x03 },
339 { CCI_REG8(0x7FA9), 0xFE },
340 { CCI_REG8(0x7B24), 0x81 },
341 { CCI_REG8(0x6564), 0x07 },
342 { CCI_REG8(0x6B0D), 0x41 },
343 { CCI_REG8(0x653D), 0x04 },
344 { CCI_REG8(0x6B05), 0x8C },
345 { CCI_REG8(0x6B06), 0xF9 },
346 { CCI_REG8(0x6B08), 0x65 },
347 { CCI_REG8(0x6B09), 0xFC },
348 { CCI_REG8(0x6B0A), 0xCF },
349 { CCI_REG8(0x6B0B), 0xD2 },
350 { CCI_REG8(0x6700), 0x0E },
351 { CCI_REG8(0x6707), 0x0E },
352 { CCI_REG8(0x9104), 0x00 },
353 { CCI_REG8(0x4648), 0x7F },
354 { CCI_REG8(0x7420), 0x00 },
355 { CCI_REG8(0x7421), 0x1C },
356 { CCI_REG8(0x7422), 0x00 },
357 { CCI_REG8(0x7423), 0xD7 },
358 { CCI_REG8(0x5F04), 0x00 },
359 { CCI_REG8(0x5F05), 0xED },
383 { CCI_REG8(0x94DC), 0x20 },
384 { CCI_REG8(0x94DD), 0x20 },
385 { CCI_REG8(0x94DE), 0x20 },
386 { CCI_REG8(0x95DC), 0x20 },
387 { CCI_REG8(0x95DD), 0x20 },
388 { CCI_REG8(0x95DE), 0x20 },
389 { CCI_REG8(0x7FB0), 0x00 },
390 { CCI_REG8(0x9010), 0x3E },
391 { CCI_REG8(0x9419), 0x50 },
392 { CCI_REG8(0x941B), 0x50 },
393 { CCI_REG8(0x9519), 0x50 },
394 { CCI_REG8(0x951B), 0x50 },
436 { CCI_REG8(0x3052), 0x00 },
437 { CCI_REG8(0x4E21), 0x14 },
438 { CCI_REG8(0x7B25), 0x00 },
447 { CCI_REG8(0x3052), 0x01 },
448 { CCI_REG8(0x4E21), 0x10 },
449 { CCI_REG8(0x7B25), 0x01 },