Lines Matching refs:CCI_REG8
33 #define MAX96717_REG3 CCI_REG8(0x3)
35 #define RCLKSEL_REF_PLL CCI_REG8(0x3)
36 #define MAX96717_REG6 CCI_REG8(0x6)
38 #define MAX96717_DEV_ID CCI_REG8(0xd)
39 #define MAX96717_DEV_REV CCI_REG8(0xe)
43 #define MAX96717_VIDEO_TX0 CCI_REG8(0x110)
45 #define MAX96717_VIDEO_TX2 CCI_REG8(0x112)
49 #define MAX96717_VTX0 CCI_REG8(0x24e)
50 #define MAX96717_VTX1 CCI_REG8(0x24f)
63 #define MAX96717_VTX29 CCI_REG8(0x26b)
65 #define MAX96717_VTX_GRAD_INC CCI_REG8(0x26c)
68 #define MAX96717_VTX_CHKB_RPT_CNT_A CCI_REG8(0x273)
69 #define MAX96717_VTX_CHKB_RPT_CNT_B CCI_REG8(0x274)
70 #define MAX96717_VTX_CHKB_ALT CCI_REG8(0x275)
74 #define MAX96717_GPIO_REG_A(gpio) CCI_REG8(0x2be + (gpio) * 3)
83 #define MAX96717_FRONTOP0 CCI_REG8(0x308)
87 #define MAX96717_MIPI_RX1 CCI_REG8(0x331)
89 #define MAX96717_MIPI_RX2 CCI_REG8(0x332) /* phy1 Lanes map */
91 #define MAX96717_MIPI_RX3 CCI_REG8(0x333) /* phy2 Lanes map */
93 #define MAX96717_MIPI_RX4 CCI_REG8(0x334) /* phy1 lane polarities */
95 #define MAX96717_MIPI_RX5 CCI_REG8(0x335) /* phy2 lane polarities */
99 #define MAX96717_MIPI_RX_EXT11 CCI_REG8(0x383)
103 #define REF_VTG0 CCI_REG8(0x3f0)
111 #define PIO_SLEW_1 CCI_REG8(0x570)