Lines Matching refs:CCI_REG8
35 #define VGXY61_REG_FWPATCH_START_ADDR CCI_REG8(0x2000)
36 #define VGXY61_REG_SYSTEM_FSM CCI_REG8(0x0020)
39 #define VGXY61_REG_NVM CCI_REG8(0x0023)
41 #define VGXY61_REG_STBY CCI_REG8(0x0201)
44 #define VGXY61_REG_STREAMING CCI_REG8(0x0202)
49 #define VGXY61_REG_CLK_PLL_PREDIV CCI_REG8(0x0224)
50 #define VGXY61_REG_CLK_SYS_PLL_MULT CCI_REG8(0x0225)
51 #define VGXY61_REG_GPIO_0_CTRL CCI_REG8(0x0236)
52 #define VGXY61_REG_GPIO_1_CTRL CCI_REG8(0x0237)
53 #define VGXY61_REG_GPIO_2_CTRL CCI_REG8(0x0238)
54 #define VGXY61_REG_GPIO_3_CTRL CCI_REG8(0x0239)
55 #define VGXY61_REG_SIGNALS_POLARITY_CTRL CCI_REG8(0x023b)
57 #define VGXY61_REG_ORIENTATION CCI_REG8(0x0302)
58 #define VGXY61_REG_VT_CTRL CCI_REG8(0x0304)
59 #define VGXY61_REG_FORMAT_CTRL CCI_REG8(0x0305)
61 #define VGXY61_REG_OIF_ROI0_CTRL CCI_REG8(0x030a)
71 #define VGXY61_REG_FRAME_CONTENT_CTRL CCI_REG8(0x0478)
74 #define VGXY61_REG_ANALOG_GAIN CCI_REG8(0x0508)
80 #define VGXY61_REG_READOUT_CTRL CCI_REG8(0x0530)
81 #define VGXY61_REG_HDR_CTRL CCI_REG8(0x0532)
90 #define VGXY61_REG_BYPASS_CTRL CCI_REG8(0x0a60)