Lines Matching refs:CCI_REG8
22 #define IMX335_REG_MODE_SELECT CCI_REG8(0x3000)
27 #define IMX335_REG_HOLD CCI_REG8(0x3001)
29 #define IMX335_REG_MASTER_MODE CCI_REG8(0x3002)
30 #define IMX335_REG_BCWAIT_TIME CCI_REG8(0x300c)
31 #define IMX335_REG_CPWAIT_TIME CCI_REG8(0x300d)
32 #define IMX335_REG_WINMODE CCI_REG8(0x3018)
34 #define IMX335_REG_HNUM CCI_REG8(0x302e)
39 #define IMX335_REG_OPB_SIZE_V CCI_REG8(0x304c)
40 #define IMX335_REG_ADBIT CCI_REG8(0x3050)
53 #define IMX335_REG_GAIN CCI_REG8(0x30e8)
59 #define IMX335_REG_TPG_TESTCLKEN CCI_REG8(0x3148)
62 #define IMX335_REG_INCLKSEL2 CCI_REG8(0x315a)
63 #define IMX335_REG_INCLKSEL3 CCI_REG8(0x3168)
64 #define IMX335_REG_INCLKSEL4 CCI_REG8(0x316a)
66 #define IMX335_REG_MDBIT CCI_REG8(0x319d)
67 #define IMX335_REG_SYSMODE CCI_REG8(0x319e)
69 #define IMX335_REG_XVS_XHS_DRV CCI_REG8(0x31a1)
72 #define IMX335_REG_TPG_DIG_CLP_MODE CCI_REG8(0x3280)
73 #define IMX335_REG_TPG_EN_DUOUT CCI_REG8(0x329c)
74 #define IMX335_REG_TPG CCI_REG8(0x329e)
87 #define IMX335_REG_TPG_COLORWIDTH CCI_REG8(0x32a0)
91 #define IMX335_REG_WRJ_OPEN CCI_REG8(0x336c)
96 #define IMX335_REG_ID CCI_REG8(0x3912)
100 #define IMX335_REG_LANEMODE CCI_REG8(0x3a01)
266 { CCI_REG8(0x3288), 0x21 },
267 { CCI_REG8(0x328a), 0x02 },
268 { CCI_REG8(0x3414), 0x05 },
269 { CCI_REG8(0x3416), 0x18 },
270 { CCI_REG8(0x3648), 0x01 },
271 { CCI_REG8(0x364a), 0x04 },
272 { CCI_REG8(0x364c), 0x04 },
273 { CCI_REG8(0x3678), 0x01 },
274 { CCI_REG8(0x367c), 0x31 },
275 { CCI_REG8(0x367e), 0x31 },
276 { CCI_REG8(0x3706), 0x10 },
277 { CCI_REG8(0x3708), 0x03 },
278 { CCI_REG8(0x3714), 0x02 },
279 { CCI_REG8(0x3715), 0x02 },
280 { CCI_REG8(0x3716), 0x01 },
281 { CCI_REG8(0x3717), 0x03 },
282 { CCI_REG8(0x371c), 0x3d },
283 { CCI_REG8(0x371d), 0x3f },
284 { CCI_REG8(0x372c), 0x00 },
285 { CCI_REG8(0x372d), 0x00 },
286 { CCI_REG8(0x372e), 0x46 },
287 { CCI_REG8(0x372f), 0x00 },
288 { CCI_REG8(0x3730), 0x89 },
289 { CCI_REG8(0x3731), 0x00 },
290 { CCI_REG8(0x3732), 0x08 },
291 { CCI_REG8(0x3733), 0x01 },
292 { CCI_REG8(0x3734), 0xfe },
293 { CCI_REG8(0x3735), 0x05 },
294 { CCI_REG8(0x3740), 0x02 },
295 { CCI_REG8(0x375d), 0x00 },
296 { CCI_REG8(0x375e), 0x00 },
297 { CCI_REG8(0x375f), 0x11 },
298 { CCI_REG8(0x3760), 0x01 },
299 { CCI_REG8(0x3768), 0x1b },
300 { CCI_REG8(0x3769), 0x1b },
301 { CCI_REG8(0x376a), 0x1b },
302 { CCI_REG8(0x376b), 0x1b },
303 { CCI_REG8(0x376c), 0x1a },
304 { CCI_REG8(0x376d), 0x17 },
305 { CCI_REG8(0x376e), 0x0f },
306 { CCI_REG8(0x3776), 0x00 },
307 { CCI_REG8(0x3777), 0x00 },
308 { CCI_REG8(0x3778), 0x46 },
309 { CCI_REG8(0x3779), 0x00 },
310 { CCI_REG8(0x377a), 0x89 },
311 { CCI_REG8(0x377b), 0x00 },
312 { CCI_REG8(0x377c), 0x08 },
313 { CCI_REG8(0x377d), 0x01 },
314 { CCI_REG8(0x377e), 0x23 },
315 { CCI_REG8(0x377f), 0x02 },
316 { CCI_REG8(0x3780), 0xd9 },
317 { CCI_REG8(0x3781), 0x03 },
318 { CCI_REG8(0x3782), 0xf5 },
319 { CCI_REG8(0x3783), 0x06 },
320 { CCI_REG8(0x3784), 0xa5 },
321 { CCI_REG8(0x3788), 0x0f },
322 { CCI_REG8(0x378a), 0xd9 },
323 { CCI_REG8(0x378b), 0x03 },
324 { CCI_REG8(0x378c), 0xeb },
325 { CCI_REG8(0x378d), 0x05 },
326 { CCI_REG8(0x378e), 0x87 },
327 { CCI_REG8(0x378f), 0x06 },
328 { CCI_REG8(0x3790), 0xf5 },
329 { CCI_REG8(0x3792), 0x43 },
330 { CCI_REG8(0x3794), 0x7a },
331 { CCI_REG8(0x3796), 0xa1 },
332 { CCI_REG8(0x37b0), 0x36 },
333 { CCI_REG8(0x3a00), 0x00 },