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Searched refs:SrcReg (Results 1 – 25 of 212) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.h26 inline static unsigned getCRFromCRBit(unsigned SrcReg) { in getCRFromCRBit() argument
28 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT || in getCRFromCRBit()
29 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN) in getCRFromCRBit()
31 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT || in getCRFromCRBit()
32 SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN) in getCRFromCRBit()
34 else if (SrcReg in getCRFromCRBit()
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H A DPPCFastISel.cpp150 unsigned SrcReg, unsigned Flag = 0, in copyRegToRegClass() argument
154 TII.get(TargetOpcode::COPY), TmpReg).addReg(SrcReg, Flag, SubReg); in copyRegToRegClass()
163 bool PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr);
167 bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
178 unsigned SrcReg, bool IsSigned);
179 unsigned PPCMoveToFPReg(MVT VT, unsigned SrcReg, bool IsSigned);
618 bool PPCFastISel::PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr) { in PPCEmitStore() argument
619 assert(SrcReg && "Nothing to store!"); in PPCEmitStore()
623 const TargetRegisterClass *RC = MRI.getRegClass(SrcReg); in PPCEmitStore()
682 .addReg(SrcReg) in PPCEmitStore()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonPeephole.cpp136 Register SrcReg = Src.getReg(); in runOnMachineFunction() local
138 if (DstReg.isVirtual() && SrcReg.isVirtual()) { in runOnMachineFunction()
142 PeepholeMap[DstReg] = SrcReg; in runOnMachineFunction()
156 Register SrcReg = Src2.getReg(); in runOnMachineFunction() local
157 PeepholeMap[DstReg] = SrcReg; in runOnMachineFunction()
173 Register SrcReg = Src1.getReg(); in runOnMachineFunction() local
175 std::make_pair(*&SrcReg, Hexagon::isub_hi); in runOnMachineFunction()
184 Register SrcReg = Src.getReg(); in runOnMachineFunction() local
186 if (DstReg.isVirtual() && SrcReg.isVirtual()) { in runOnMachineFunction()
190 PeepholeMap[DstReg] = SrcReg; in runOnMachineFunction()
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H A DHexagonInstrInfo.cpp860 MCRegister SrcReg, bool KillSrc) const { in copyPhysReg() argument
864 if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) { in copyPhysReg()
866 .addReg(SrcReg, KillFlag); in copyPhysReg()
869 if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) { in copyPhysReg()
871 .addReg(SrcReg, KillFlag); in copyPhysReg()
874 if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) { in copyPhysReg()
877 .addReg(SrcReg).addReg(SrcReg, KillFlag); in copyPhysReg()
881 Hexagon::IntRegsRegClass.contains(SrcReg)) { in copyPhysReg()
883 .addReg(SrcReg, KillFlag); in copyPhysReg()
887 Hexagon::CtrRegsRegClass.contains(SrcReg)) { in copyPhysReg()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumb1InstrInfo.cpp45 MCRegister SrcReg, bool KillSrc) const { in copyPhysReg() argument
50 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) && in copyPhysReg()
53 if (st.hasV6Ops() || ARM::hGPRRegClass.contains(SrcReg) || in copyPhysReg()
56 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
71 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
96 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
107 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
116 Register SrcReg, bool isKill, int FI, in storeRegToStackSlot() argument
121 (SrcReg.isPhysical() && isARMLowRegister(SrcReg))) && in storeRegToStackSlot()
125 (SrcReg.isPhysical() && isARMLowRegister(SrcReg))) { in storeRegToStackSlot()
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizationArtifactCombiner.h68 Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg()); in tryCombineAnyExt() local
72 if (mi_match(SrcReg, MRI, m_GTrunc(m_Reg(TruncSrc)))) { in tryCombineAnyExt()
80 markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts); in tryCombineAnyExt()
87 if (mi_match(SrcReg, MRI, in tryCombineAnyExt()
98 auto *SrcMI = MRI.getVRegDef(SrcReg); in tryCombineAnyExt()
127 Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg()); in tryCombineZExt() local
133 if (mi_match(SrcReg, MRI, m_GTrunc(m_Reg(TruncSrc))) || in tryCombineZExt()
134 mi_match(SrcReg, MRI, m_GSExt(m_Reg(SextSrc)))) { in tryCombineZExt()
140 LLT SrcTy = MRI.getType(SrcReg); in tryCombineZExt()
161 markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts); in tryCombineZExt()
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/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchInstrInfo.cpp42 MCRegister SrcReg, bool KillSrc) const { in copyPhysReg() argument
43 if (LoongArch::GPRRegClass.contains(DstReg, SrcReg)) { in copyPhysReg()
45 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
51 if (LoongArch::LSX128RegClass.contains(DstReg, SrcReg)) { in copyPhysReg()
53 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
59 if (LoongArch::LASX256RegClass.contains(DstReg, SrcReg)) { in copyPhysReg()
61 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
68 LoongArch::GPRRegClass.contains(SrcReg)) { in copyPhysReg()
70 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
75 LoongArch::CFRRegClass.contains(SrcReg)) { in copyPhysReg()
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/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfo.cpp393 Register SrcReg, bool IsKill, int FI, in storeRegToStackSlot() argument
429 .addReg(SrcReg, getKillRegState(IsKill)) in storeRegToStackSlot()
481 MCRegister SrcReg, bool KillSrc) const { in copyPhysReg() argument
482 if (CSKY::GPRRegClass.contains(SrcReg) && in copyPhysReg()
486 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
489 assert(SrcReg < CSKY::R8); in copyPhysReg()
491 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
497 if (CSKY::CARRYRegClass.contains(SrcReg) && in copyPhysReg()
502 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
509 .addReg(SrcReg, RegState::Define) in copyPhysReg()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCDuplexInfo.cpp190 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg; in getDuplexCandidateGroup() local
202 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
206 if (HexagonMCInstrInfo::isIntReg(SrcReg) && in getDuplexCandidateGroup()
207 Hexagon::R29 == SrcReg && inRange<5, 2>(MCI, 2)) { in getDuplexCandidateGroup()
211 if (HexagonMCInstrInfo::isIntRegForSubInst(SrcReg) && in getDuplexCandidateGroup()
220 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
222 HexagonMCInstrInfo::isIntRegForSubInst(SrcReg) && in getDuplexCandidateGroup()
241 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
243 HexagonMCInstrInfo::isIntRegForSubInst(SrcReg) && in getDuplexCandidateGroup()
251 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
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/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFInstrInfo.cpp34 MCRegister SrcReg, bool KillSrc) const { in copyPhysReg() argument
35 if (BPF::GPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
37 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
38 else if (BPF::GPR32RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
40 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
47 Register SrcReg = MI->getOperand(1).getReg(); in expandMEMCPY() local
79 .addReg(ScratchReg, RegState::Define).addReg(SrcReg) in expandMEMCPY()
93 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset); in expandMEMCPY()
100 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset); in expandMEMCPY()
107 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset); in expandMEMCPY()
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H A DBPFMISimplifyPatchable.cpp66 MachineInstr &MI, Register &SrcReg, Register &DstReg,
69 Register &SrcReg, const GlobalValue *GVal,
191 MachineBasicBlock &MBB, MachineInstr &MI, Register &SrcReg, in processCandidate() argument
217 .addReg(SrcReg, 0, BPF::sub_32); in processCandidate()
222 processDstReg(MRI, DstReg, SrcReg, GVal, true, IsAma); in processCandidate()
226 Register &DstReg, Register &SrcReg, const GlobalValue *GVal, in processDstReg() argument
255 I->setReg(SrcReg); in processDstReg()
331 Register SrcReg = MI.getOperand(1).getReg(); in removeLD() local
333 MachineInstr *DefInst = MRI->getUniqueVRegDef(SrcReg); in removeLD()
356 processCandidate(MRI, MBB, MI, SrcReg, DstReg, GVal, IsAma); in removeLD()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp86 MCRegister SrcReg, bool KillSrc) const { in copyPhysReg() argument
91 if (Mips::GPR32RegClass.contains(SrcReg)) { in copyPhysReg()
96 } else if (Mips::CCRRegClass.contains(SrcReg)) in copyPhysReg()
98 else if (Mips::FGR32RegClass.contains(SrcReg)) in copyPhysReg()
100 else if (Mips::HI32RegClass.contains(SrcReg)) { in copyPhysReg()
102 SrcReg = 0; in copyPhysReg()
103 } else if (Mips::LO32RegClass.contains(SrcReg)) { in copyPhysReg()
105 SrcReg = 0; in copyPhysReg()
106 } else if (Mips::HI32DSPRegClass.contains(SrcReg)) in copyPhysReg()
108 else if (Mips::LO32DSPRegClass.contains(SrcReg)) in copyPhysReg()
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H A DMipsFastISel.cpp182 bool emitStore(MVT VT, unsigned SrcReg, Address &Addr);
183 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
184 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
187 bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
189 bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
190 bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
192 bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
215 MachineInstrBuilder emitInstStore(unsigned Opc, unsigned SrcReg, in emitInstStore() argument
217 return emitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset); in emitInstStore()
806 bool MipsFastISel::emitStore(MVT VT, unsigned SrcReg, Address &Addr) { in emitStore() argument
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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZCopyPhysRegs.cpp78 Register SrcReg = MI->getOperand(1).getReg(); in visitMBB() local
81 (SrcReg == SystemZ::CC || SystemZ::AR32BitRegClass.contains(SrcReg))) { in visitMBB()
83 if (SrcReg == SystemZ::CC) in visitMBB()
86 BuildMI(MBB, MI, DL, TII->get(SystemZ::EAR), Tmp).addReg(SrcReg); in visitMBB()
90 else if (SrcReg.isVirtual() && in visitMBB()
H A DSystemZInstrInfo.cpp173 Register SrcReg = MI.getOperand(1).getReg(); in expandRIEPseudo() local
175 bool SrcIsHigh = SystemZ::isHighReg(SrcReg); in expandRIEPseudo()
179 if (DestReg != SrcReg) { in expandRIEPseudo()
180 emitGRX32Move(*MI.getParent(), MI, MI.getDebugLoc(), DestReg, SrcReg, in expandRIEPseudo()
267 unsigned SrcReg, unsigned LowLowOpcode, in emitGRX32Move() argument
272 bool SrcIsHigh = SystemZ::isHighReg(SrcReg); in emitGRX32Move()
281 .addReg(SrcReg, getKillRegState(KillSrc) | getUndefRegState(UndefSrc)); in emitGRX32Move()
286 .addReg(SrcReg, getKillRegState(KillSrc) | getUndefRegState(UndefSrc)) in emitGRX32Move()
533 bool SystemZInstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg, in analyzeCompare() argument
540 SrcReg = MI.getOperand(0).getReg(); in analyzeCompare()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DOptimizePHIs.cpp112 Register SrcReg = MI->getOperand(i).getReg(); in IsSingleValuePHICycle() local
113 if (SrcReg == DstReg) in IsSingleValuePHICycle()
115 MachineInstr *SrcMI = MRI->getVRegDef(SrcReg); in IsSingleValuePHICycle()
121 SrcReg = SrcMI->getOperand(1).getReg(); in IsSingleValuePHICycle()
122 SrcMI = MRI->getVRegDef(SrcReg); in IsSingleValuePHICycle()
132 if (SingleValReg != 0 && SingleValReg != SrcReg) in IsSingleValuePHICycle()
134 SingleValReg = SrcReg; in IsSingleValuePHICycle()
H A DPHIElimination.cpp537 Register SrcReg = MPhi->getOperand(i * 2 + 1).getReg(); in LowerPHINode() local
540 isImplicitlyDefined(SrcReg, *MRI); in LowerPHINode()
541 assert(SrcReg.isVirtual() && in LowerPHINode()
554 MachineInstr *SrcRegDef = MRI->getVRegDef(SrcReg); in LowerPHINode()
561 assert(MRI->use_empty(SrcReg) && in LowerPHINode()
567 LiveVariables::VarInfo &SrcVI = LV->getVarInfo(SrcReg); in LowerPHINode()
579 findPHICopyInsertPoint(&opBlock, &MBB, SrcReg); in LowerPHINode()
593 if (MachineInstr *DefMI = MRI->getVRegDef(SrcReg)) in LowerPHINode()
600 SrcReg, SrcSubReg, IncomingReg); in LowerPHINode()
608 !VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)] && in LowerPHINode()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.cpp441 MCRegister SrcReg, bool KillSrc) const { in copyPhysReg() argument
454 if (SP::IntRegsRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
456 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
457 else if (SP::IntPairRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
462 } else if (SP::FPRegsRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
464 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
465 else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
468 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
475 } else if (SP::QFPRegsRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
479 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUPostLegalizerCombiner.cpp217 Register SrcReg = MI.getOperand(1).getReg(); in matchUCharToFloat() local
218 unsigned SrcSize = MRI.getType(SrcReg).getSizeInBits(); in matchUCharToFloat()
221 return Helper.getKnownBits()->maskedValueIsZero(SrcReg, Mask); in matchUCharToFloat()
232 Register SrcReg = MI.getOperand(1).getReg(); in applyUCharToFloat() local
234 LLT SrcTy = MRI.getType(SrcReg); in applyUCharToFloat()
236 SrcReg = B.buildAnyExtOrTrunc(S32, SrcReg).getReg(0); in applyUCharToFloat()
239 B.buildInstr(AMDGPU::G_AMDGPU_CVT_F32_UBYTE0, {DstReg}, {SrcReg}, in applyUCharToFloat()
242 auto Cvt0 = B.buildInstr(AMDGPU::G_AMDGPU_CVT_F32_UBYTE0, {S32}, {SrcReg}, in applyUCharToFloat()
319 Register SrcReg = MI.getOperand(1).getReg(); in matchCvtF32UByteN() local
322 bool IsShr = mi_match(SrcReg, MRI, m_GZExt(m_Reg(SrcReg))); in matchCvtF32UByteN()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstructionSelector.cpp
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRExpandPseudoInsts.cpp155 Register SrcReg = MI.getOperand(2).getReg(); in expandArith() local
160 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg); in expandArith()
188 Register SrcReg = MI.getOperand(2).getReg(); in expandLogic() local
193 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg); in expandLogic()
498 Register SrcReg = MI.getOperand(1).getReg(); in expand() local
504 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg); in expand()
531 Register SrcReg = MI.getOperand(1).getReg(); in expand() local
537 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg); in expand()
662 Register SrcReg = MI.getOperand(1).getReg(); in expand() local
669 assert(DstReg != SrcReg && "Dst and Src registers are the same!"); in expand()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86InstructionSelector.cpp113 const unsigned SrcReg,
124 bool emitInsertSubreg(unsigned DstReg, unsigned SrcReg, MachineInstr &I,
127 bool emitExtractSubreg(unsigned DstReg, unsigned SrcReg, MachineInstr &I,
283 Register SrcReg = I.getOperand(1).getReg(); in selectCopy() local
284 const unsigned SrcSize = RBI.getSizeInBits(SrcReg, MRI, TRI); in selectCopy()
285 const RegisterBank &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in selectCopy()
294 getRegClass(MRI.getType(SrcReg), SrcRegBank); in selectCopy()
304 .addReg(SrcReg) in selectCopy()
314 assert((!SrcReg.isPhysical() || I.isCopy()) && in selectCopy()
319 (SrcReg.isPhysical() && in selectCopy()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DInstructionSelect.cpp172 auto [DstReg, SrcReg] = MI.getFirst2Regs(); in runOnMachineFunction()
180 MRI.setRegClass(SrcReg, DstRC); in runOnMachineFunction()
181 assert(canReplaceReg(DstReg, SrcReg, MRI) && in runOnMachineFunction()
184 MRI.replaceRegWith(DstReg, SrcReg); in runOnMachineFunction()
237 Register SrcReg = MI.getOperand(1).getReg(); in runOnMachineFunction() local
239 if (SrcReg.isVirtual() && DstReg.isVirtual()) { in runOnMachineFunction()
240 auto SrcRC = MRI.getRegClass(SrcReg); in runOnMachineFunction()
243 MRI.replaceRegWith(DstReg, SrcReg); in runOnMachineFunction()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64MIPeepholeOpt.cpp212 unsigned Imm1, Register SrcReg, Register NewTmpReg, in visitAND()
217 .addReg(SrcReg) in visitAND()
277 Register SrcReg = MI.getOperand(2).getReg(); in visitORR() local
278 MRI->replaceRegWith(DefReg, SrcReg); in visitORR()
279 MRI->clearKillFlags(SrcReg); in visitORR()
385 unsigned Imm1, Register SrcReg, Register NewTmpReg, in visitADDSUB()
390 .addReg(SrcReg) in visitADDSUB()
431 unsigned Imm1, Register SrcReg, Register NewTmpReg, in visitADDSSUBS()
436 .addReg(SrcReg) in visitADDSSUBS()
535 Register SrcReg = MI.getOperand(1).getReg(); in splitTwoPartImm() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kInstrInfo.cpp666 MCRegister SrcReg, bool KillSrc) const { in copyPhysReg() argument
670 if (M68k::XR32RegClass.contains(DstReg, SrcReg)) in copyPhysReg()
672 else if (M68k::XR16RegClass.contains(DstReg, SrcReg)) in copyPhysReg()
674 else if (M68k::DR8RegClass.contains(DstReg, SrcReg)) in copyPhysReg()
679 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
690 if (M68k::DR8RegClass.contains(SrcReg)) { in copyPhysReg()
695 } else if (M68k::XR16RegClass.contains(SrcReg) && in copyPhysReg()
701 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
705 bool FromCCR = SrcReg == M68k::CCR; in copyPhysReg()
706 bool FromSR = SrcReg == M68k::SR; in copyPhysReg()
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