Lines Matching refs:SrcReg
155 Register SrcReg = MI.getOperand(2).getReg(); in expandArith() local
160 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg); in expandArith()
188 Register SrcReg = MI.getOperand(2).getReg(); in expandLogic() local
193 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg); in expandLogic()
498 Register SrcReg = MI.getOperand(1).getReg(); in expand() local
504 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg); in expand()
531 Register SrcReg = MI.getOperand(1).getReg(); in expand() local
537 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg); in expand()
662 Register SrcReg = MI.getOperand(1).getReg(); in expand() local
669 assert(DstReg != SrcReg && "Dst and Src registers are the same!"); in expand()
676 .addReg(SrcReg, getKillRegState(SrcIsKill)) in expand()
687 .addReg(SrcReg) in expand()
693 .addReg(SrcReg, getKillRegState(SrcIsKill)) in expand()
707 Register SrcReg = MI.getOperand(1).getReg(); in expand() local
714 assert(DstReg != SrcReg && "SrcReg and DstReg cannot be the same"); in expand()
719 .addReg(SrcReg, RegState::Define) in expand()
720 .addReg(SrcReg, RegState::Kill); in expand()
725 .addReg(SrcReg, RegState::Define | getDeadRegState(SrcIsDead)) in expand()
726 .addReg(SrcReg, RegState::Kill); in expand()
740 Register SrcReg = MI.getOperand(1).getReg(); in expand() local
747 assert(DstReg != SrcReg && "SrcReg and DstReg cannot be the same"); in expand()
752 .addReg(SrcReg, RegState::Define) in expand()
753 .addReg(SrcReg, RegState::Kill); in expand()
758 .addReg(SrcReg, RegState::Define | getDeadRegState(SrcIsDead)) in expand()
759 .addReg(SrcReg, RegState::Kill); in expand()
772 Register SrcReg = MI.getOperand(1).getReg(); in expand() local
784 assert(DstReg != SrcReg && "Dst and Src registers are the same!"); in expand()
794 buildMI(MBB, MBBI, AVR::SUBIWRdK, SrcReg) in expand()
795 .addReg(SrcReg) in expand()
803 .addReg(SrcReg, getKillRegState(SrcIsKill)) in expand()
811 buildMI(MBB, MBBI, AVR::SUBIWRdK, SrcReg).addReg(SrcReg).addImm(Imm + 2); in expand()
820 .addReg(SrcReg) in expand()
827 .addReg(SrcReg, getKillRegState(SrcIsKill)) in expand()
840 Register SrcReg = MI.getOperand(1).getReg(); in expandLPMWELPMW() local
847 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg); in expandLPMWELPMW()
857 assert(DstReg != SrcReg && "SrcReg and DstReg cannot be the same"); in expandLPMWELPMW()
865 .addReg(SrcReg); in expandLPMWELPMW()
869 .addReg(SrcReg, getKillRegState(SrcIsKill)); in expandLPMWELPMW()
884 .addReg(SrcReg, RegState::Define) in expandLPMWELPMW()
885 .addReg(SrcReg, getKillRegState(SrcIsKill)) in expandLPMWELPMW()
915 .addReg(SrcReg, RegState::Define) in expandLPMWELPMW()
916 .addReg(SrcReg, getKillRegState(SrcIsKill)) in expandLPMWELPMW()
952 Register SrcReg = MI.getOperand(1).getReg(); in expandLPMBELPMB() local
968 .addReg(SrcReg, getKillRegState(SrcIsKill)); in expandLPMBELPMB()
1084 Register SrcReg = MI.getOperand(1).getReg(); in expand() local
1086 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg); in expand()
1150 Register SrcReg = MI.getOperand(1).getReg(); in expand() local
1165 .addReg(SrcReg, getKillRegState(SrcIsKill)) in expand()
1170 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg); in expand()
1203 Register SrcReg = MI.getOperand(2).getReg(); in expand() local
1209 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg); in expand()
1211 assert(DstReg != SrcReg && "SrcReg and DstReg cannot be the same"); in expand()
1238 Register SrcReg = MI.getOperand(2).getReg(); in expand() local
1244 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg); in expand()
1246 assert(DstReg != SrcReg && "SrcReg and DstReg cannot be the same"); in expand()
1276 Register SrcReg = MI.getOperand(2).getReg(); in expand() local
1295 .addReg(SrcReg, getKillRegState(SrcIsKill)) in expand()
1309 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg); in expand()
1416 Register SrcReg = MI.getOperand(1).getReg(); in expand() local
1418 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg); in expand()
1446 Register SrcReg = MI.getOperand(0).getReg(); in expand() local
1451 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg); in expand()
2422 Register SrcReg = MI.getOperand(1).getReg(); in expand() local
2428 if (SrcReg != DstLoReg) in expand()
2431 .addReg(SrcReg); in expand()
2433 if (SrcReg != DstHiReg) { in expand()
2436 .addReg(SrcReg); in expand()
2437 if (SrcReg != DstLoReg && SrcIsKill) in expand()
2474 Register SrcReg = MI.getOperand(1).getReg(); in expand() local
2480 if (SrcReg != DstLoReg) { in expand()
2483 .addReg(SrcReg, getKillRegState(SrcIsKill)); in expand()
2531 Register SrcReg = MI.getOperand(1).getReg(); in expand() local
2534 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg); in expand()