Lines Matching refs:SrcReg

173   Register SrcReg = MI.getOperand(1).getReg();  in expandRIEPseudo()  local
175 bool SrcIsHigh = SystemZ::isHighReg(SrcReg); in expandRIEPseudo()
179 if (DestReg != SrcReg) { in expandRIEPseudo()
180 emitGRX32Move(*MI.getParent(), MI, MI.getDebugLoc(), DestReg, SrcReg, in expandRIEPseudo()
267 unsigned SrcReg, unsigned LowLowOpcode, in emitGRX32Move() argument
272 bool SrcIsHigh = SystemZ::isHighReg(SrcReg); in emitGRX32Move()
281 .addReg(SrcReg, getKillRegState(KillSrc) | getUndefRegState(UndefSrc)); in emitGRX32Move()
286 .addReg(SrcReg, getKillRegState(KillSrc) | getUndefRegState(UndefSrc)) in emitGRX32Move()
533 bool SystemZInstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg, in analyzeCompare() argument
540 SrcReg = MI.getOperand(0).getReg(); in analyzeCompare()
861 MCRegister SrcReg, bool KillSrc) const { in copyPhysReg() argument
865 if (SystemZ::GR128BitRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
867 RI.getSubReg(SrcReg, SystemZ::subreg_h64), KillSrc); in copyPhysReg()
869 .addReg(SrcReg, RegState::Implicit); in copyPhysReg()
871 RI.getSubReg(SrcReg, SystemZ::subreg_l64), KillSrc); in copyPhysReg()
873 .addReg(SrcReg, (getKillRegState(KillSrc) | RegState::Implicit)); in copyPhysReg()
877 if (SystemZ::GRX32BitRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
878 emitGRX32Move(MBB, MBBI, DL, DestReg, SrcReg, SystemZ::LR, 32, KillSrc, in copyPhysReg()
885 SystemZ::FP128BitRegClass.contains(SrcReg)) { in copyPhysReg()
887 RI.getMatchingSuperReg(RI.getSubReg(SrcReg, SystemZ::subreg_h64), in copyPhysReg()
890 RI.getMatchingSuperReg(RI.getSubReg(SrcReg, SystemZ::subreg_l64), in copyPhysReg()
899 SystemZ::VR128BitRegClass.contains(SrcReg)) { in copyPhysReg()
907 if (DestRegHi != SrcReg) in copyPhysReg()
908 copyPhysReg(MBB, MBBI, DL, DestRegHi, SrcReg, false); in copyPhysReg()
910 .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1); in copyPhysReg()
915 SystemZ::GR128BitRegClass.contains(SrcReg)) { in copyPhysReg()
918 MCRegister SrcRegHi = RI.getSubReg(SrcReg, SystemZ::subreg_h64); in copyPhysReg()
919 MCRegister SrcRegLo = RI.getSubReg(SrcReg, SystemZ::subreg_l64); in copyPhysReg()
933 SystemZ::GR32BitRegClass.contains(SrcReg) ? SystemZ::TMLH : SystemZ::TMHH; in copyPhysReg()
935 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
941 SystemZ::VR128BitRegClass.contains(SrcReg)) { in copyPhysReg()
946 .addReg(SrcReg) in copyPhysReg()
951 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
958 SystemZ::GR128BitRegClass.contains(SrcReg)) { in copyPhysReg()
960 .addReg(RI.getSubReg(SrcReg, SystemZ::subreg_h64)) in copyPhysReg()
961 .addReg(RI.getSubReg(SrcReg, SystemZ::subreg_l64)); in copyPhysReg()
967 if (SystemZ::GR64BitRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
969 else if (SystemZ::FP32BitRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
972 else if (SystemZ::FP64BitRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
974 else if (SystemZ::FP128BitRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
976 else if (SystemZ::VR32BitRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
978 else if (SystemZ::VR64BitRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
980 else if (SystemZ::VR128BitRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
982 else if (SystemZ::AR32BitRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
988 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
992 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, in storeRegToStackSlot() argument
1002 .addReg(SrcReg, getKillRegState(isKill)), in storeRegToStackSlot()
1445 Register SrcReg = (OpNum == 2 ? MI.getOperand(1).getReg() in foldMemoryOperandImpl() local
1449 if (DstPhys && !SystemZ::GRH32BitRegClass.contains(DstPhys) && SrcReg && in foldMemoryOperandImpl()
1450 SrcReg.isVirtual() && DstPhys == VRM->getPhys(SrcReg)) in foldMemoryOperandImpl()