Lines Matching refs:SrcReg
860 MCRegister SrcReg, bool KillSrc) const { in copyPhysReg() argument
864 if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) { in copyPhysReg()
866 .addReg(SrcReg, KillFlag); in copyPhysReg()
869 if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) { in copyPhysReg()
871 .addReg(SrcReg, KillFlag); in copyPhysReg()
874 if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) { in copyPhysReg()
877 .addReg(SrcReg).addReg(SrcReg, KillFlag); in copyPhysReg()
881 Hexagon::IntRegsRegClass.contains(SrcReg)) { in copyPhysReg()
883 .addReg(SrcReg, KillFlag); in copyPhysReg()
887 Hexagon::CtrRegsRegClass.contains(SrcReg)) { in copyPhysReg()
889 .addReg(SrcReg, KillFlag); in copyPhysReg()
893 Hexagon::IntRegsRegClass.contains(SrcReg)) { in copyPhysReg()
895 .addReg(SrcReg, KillFlag); in copyPhysReg()
898 if (Hexagon::PredRegsRegClass.contains(SrcReg) && in copyPhysReg()
901 .addReg(SrcReg, KillFlag); in copyPhysReg()
904 if (Hexagon::IntRegsRegClass.contains(SrcReg) && in copyPhysReg()
907 .addReg(SrcReg, KillFlag); in copyPhysReg()
910 if (Hexagon::PredRegsRegClass.contains(SrcReg) && in copyPhysReg()
913 .addReg(SrcReg, KillFlag); in copyPhysReg()
916 if (Hexagon::HvxVRRegClass.contains(SrcReg, DestReg)) { in copyPhysReg()
918 addReg(SrcReg, KillFlag); in copyPhysReg()
921 if (Hexagon::HvxWRRegClass.contains(SrcReg, DestReg)) { in copyPhysReg()
924 Register SrcLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo); in copyPhysReg()
925 Register SrcHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi); in copyPhysReg()
933 if (Hexagon::HvxQRRegClass.contains(SrcReg, DestReg)) { in copyPhysReg()
935 .addReg(SrcReg) in copyPhysReg()
936 .addReg(SrcReg, KillFlag); in copyPhysReg()
939 if (Hexagon::HvxQRRegClass.contains(SrcReg) && in copyPhysReg()
945 Hexagon::HvxVRRegClass.contains(SrcReg)) { in copyPhysReg()
953 << printReg(DestReg, &HRI) << " = " << printReg(SrcReg, &HRI) << '\n'; in copyPhysReg()
960 Register SrcReg, bool isKill, int FI, in storeRegToStackSlot() argument
976 .addReg(SrcReg, KillFlag).addMemOperand(MMO); in storeRegToStackSlot()
980 .addReg(SrcReg, KillFlag).addMemOperand(MMO); in storeRegToStackSlot()
984 .addReg(SrcReg, KillFlag).addMemOperand(MMO); in storeRegToStackSlot()
988 .addReg(SrcReg, KillFlag).addMemOperand(MMO); in storeRegToStackSlot()
992 .addReg(SrcReg, KillFlag).addMemOperand(MMO); in storeRegToStackSlot()
996 .addReg(SrcReg, KillFlag).addMemOperand(MMO); in storeRegToStackSlot()
1000 .addReg(SrcReg, KillFlag).addMemOperand(MMO); in storeRegToStackSlot()
1139 Register SrcReg = MI.getOperand(1).getReg(); in expandPostRAPseudo() local
1141 Register SrcLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo); in expandPostRAPseudo()
1142 Register SrcHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi); in expandPostRAPseudo()
1154 Register SrcReg = MI.getOperand(1).getReg(); in expandPostRAPseudo() local
1156 Register SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo); in expandPostRAPseudo()
1163 Register SrcReg = MI.getOperand(1).getReg(); in expandPostRAPseudo() local
1165 Register SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi); in expandPostRAPseudo()
1226 Register SrcReg = MI.getOperand(2).getReg(); in expandPostRAPseudo() local
1237 .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_lo)) in expandPostRAPseudo()
1242 .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_hi)) in expandPostRAPseudo()
1880 bool HexagonInstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg, in analyzeCompare() argument
1902 SrcReg = MI.getOperand(1).getReg(); in analyzeCompare()
1911 SrcReg = MI.getOperand(1).getReg(); in analyzeCompare()
1920 SrcReg = MI.getOperand(1).getReg(); in analyzeCompare()
3427 Register DstReg, SrcReg, Src1Reg, Src2Reg; in getCompoundCandidateGroup() local
3454 SrcReg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup()
3457 isIntRegForSubInst(SrcReg) && MI.getOperand(2).isImm() && in getCompoundCandidateGroup()
3465 SrcReg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup()
3466 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg)) in getCompoundCandidateGroup()
3925 Register DstReg, SrcReg, Src1Reg, Src2Reg; in getDuplexCandidateGroup() local
3939 SrcReg = MI.getOperand(1).getReg(); in getDuplexCandidateGroup()
3943 if (Hexagon::IntRegsRegClass.contains(SrcReg) && in getDuplexCandidateGroup()
3944 HRI.getStackRegister() == SrcReg && in getDuplexCandidateGroup()
3949 if (isIntRegForSubInst(SrcReg) && in getDuplexCandidateGroup()
3959 SrcReg = MI.getOperand(1).getReg(); in getDuplexCandidateGroup()
3960 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) && in getDuplexCandidateGroup()
3980 SrcReg = MI.getOperand(1).getReg(); in getDuplexCandidateGroup()
3981 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) && in getDuplexCandidateGroup()
3990 SrcReg = MI.getOperand(1).getReg(); in getDuplexCandidateGroup()
3991 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) && in getDuplexCandidateGroup()
4000 SrcReg = MI.getOperand(1).getReg(); in getDuplexCandidateGroup()
4002 Hexagon::IntRegsRegClass.contains(SrcReg) && in getDuplexCandidateGroup()
4003 HRI.getStackRegister() == SrcReg && in getDuplexCandidateGroup()
4036 SrcReg = MI.getOperand(0).getReg(); in getDuplexCandidateGroup()
4038 if ((Hexagon::PredRegsRegClass.contains(SrcReg) && in getDuplexCandidateGroup()
4039 (Hexagon::P0 == SrcReg)) && in getDuplexCandidateGroup()
4050 SrcReg = MI.getOperand(0).getReg(); in getDuplexCandidateGroup()
4051 if (Hexagon::PredRegsRegClass.contains(SrcReg) && (Hexagon::P0 == SrcReg)) in getDuplexCandidateGroup()
4160 SrcReg = MI.getOperand(1).getReg(); in getDuplexCandidateGroup()
4163 if (Hexagon::IntRegsRegClass.contains(SrcReg) && in getDuplexCandidateGroup()
4164 HRI.getStackRegister() == SrcReg && MI.getOperand(2).isImm() && in getDuplexCandidateGroup()
4168 if ((DstReg == SrcReg) && MI.getOperand(2).isImm() && in getDuplexCandidateGroup()
4173 if (isIntRegForSubInst(SrcReg) && MI.getOperand(2).isImm() && in getDuplexCandidateGroup()
4195 SrcReg = MI.getOperand(1).getReg(); in getDuplexCandidateGroup()
4196 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) && in getDuplexCandidateGroup()
4206 SrcReg = MI.getOperand(1).getReg(); in getDuplexCandidateGroup()
4207 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg)) in getDuplexCandidateGroup()
4232 SrcReg = MI.getOperand(1).getReg(); in getDuplexCandidateGroup()
4234 Hexagon::PredRegsRegClass.contains(SrcReg) && Hexagon::P0 == SrcReg && in getDuplexCandidateGroup()
4242 SrcReg = MI.getOperand(1).getReg(); in getDuplexCandidateGroup()
4244 Hexagon::P0 == DstReg && isIntRegForSubInst(SrcReg) && in getDuplexCandidateGroup()
4268 SrcReg = MI.getOperand(1).getReg(); in getDuplexCandidateGroup()
4269 if (isDblRegForSubInst(DstReg, HRI) && isIntRegForSubInst(SrcReg) && in getDuplexCandidateGroup()
4278 SrcReg = MI.getOperand(2).getReg(); in getDuplexCandidateGroup()
4279 if (isDblRegForSubInst(DstReg, HRI) && isIntRegForSubInst(SrcReg) && in getDuplexCandidateGroup()
4294 SrcReg = MI.getOperand(1).getReg(); in getDuplexCandidateGroup()
4295 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg)) in getDuplexCandidateGroup()