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Searched refs:RISCV (Results 1 – 25 of 96) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVOptWInstrs.cpp96 unsigned MCOpcode = RISCV::getRVVMCOpcode(MI.getOpcode()); in vectorPseudoHasAllNBitUsers()
112 RISCV::getVectorLowDemandedScalarBits(MCOpcode, Log2SEW); in vectorPseudoHasAllNBitUsers()
154 case RISCV::ADDIW: in hasAllNBitUsers()
155 case RISCV::ADDW: in hasAllNBitUsers()
156 case RISCV::DIVUW: in hasAllNBitUsers()
157 case RISCV::DIVW: in hasAllNBitUsers()
158 case RISCV::MULW: in hasAllNBitUsers()
159 case RISCV::REMUW: in hasAllNBitUsers()
160 case RISCV::REMW: in hasAllNBitUsers()
161 case RISCV::SLLIW: in hasAllNBitUsers()
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H A DRISCVInstrInfo.cpp15 #include "RISCV.h"
63 using namespace RISCV;
70 namespace llvm::RISCV { namespace
75 } // end namespace llvm::RISCV
78 : RISCVGenInstrInfo(RISCV::ADJCALLSTACKDOWN, RISCV::ADJCALLSTACKUP), in RISCVInstrInfo()
83 return MCInstBuilder(RISCV::C_NOP); in getNop()
84 return MCInstBuilder(RISCV::ADDI) in getNop()
85 .addReg(RISCV::X0) in getNop()
86 .addReg(RISCV in getNop()
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H A DRISCVExpandPseudoInsts.cpp108 case RISCV::PseudoRV32ZdinxSD: in expandMI()
110 case RISCV::PseudoRV32ZdinxLD: in expandMI()
112 case RISCV::PseudoCCMOVGPRNoX0: in expandMI()
113 case RISCV::PseudoCCMOVGPR: in expandMI()
114 case RISCV::PseudoCCADD: in expandMI()
115 case RISCV::PseudoCCSUB: in expandMI()
116 case RISCV::PseudoCCAND: in expandMI()
117 case RISCV::PseudoCCOR: in expandMI()
118 case RISCV::PseudoCCXOR: in expandMI()
119 case RISCV::PseudoCCADDW: in expandMI()
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H A DRISCVRegisterInfo.cpp41 static_assert(RISCV::X1 == RISCV::X0 + 1, "Register list not consecutive");
42 static_assert(RISCV::X31 == RISCV::X0 + 31, "Register list not consecutive");
43 static_assert(RISCV::F1_H == RISCV::F0_H + 1, "Register list not consecutive");
44 static_assert(RISCV::F31_H == RISCV::F0_H + 31,
46 static_assert(RISCV::F1_F == RISCV::F0_F + 1, "Register list not consecutive");
47 static_assert(RISCV::F31_F == RISCV::F0_F + 31,
49 static_assert(RISCV::F1_D == RISCV::F0_D + 1, "Register list not consecutive");
50 static_assert(RISCV::F31_D == RISCV::F0_D + 31,
52 static_assert(RISCV::V1 == RISCV::V0 + 1, "Register list not consecutive");
53 static_assert(RISCV::V31 == RISCV::V0 + 31, "Register list not consecutive");
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H A DRISCVMakeCompressible.cpp102 case RISCV::LBU: in log2LdstWidth()
103 case RISCV::SB: in log2LdstWidth()
105 case RISCV::LH: in log2LdstWidth()
106 case RISCV::LHU: in log2LdstWidth()
107 case RISCV::SH: in log2LdstWidth()
109 case RISCV::LW: in log2LdstWidth()
110 case RISCV::SW: in log2LdstWidth()
111 case RISCV::FLW: in log2LdstWidth()
112 case RISCV::FSW: in log2LdstWidth()
114 case RISCV::LD: in log2LdstWidth()
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H A DRISCVAsmPrinter.cpp53 extern const SubtargetFeatureKV RISCVFeatureKV[RISCV::NumSubtargetFeatures];
133 MII->getOpcode() == RISCV::DBG_VALUE || in LowerSTACKMAP()
168 RISCVMatInt::generateMCInstSeq(CallTarget, *STI, RISCV::X1, Seq); in LowerPATCHPOINT()
173 bool Compressed = EmitToStreamer(OutStreamer, MCInstBuilder(RISCV::JALR) in LowerPATCHPOINT()
174 .addReg(RISCV::X1) in LowerPATCHPOINT()
175 .addReg(RISCV::X1) in LowerPATCHPOINT()
183 MCInstBuilder(RISCV::PseudoCALL).addOperand(CallTargetMCOp)); in LowerPATCHPOINT()
215 MCInstBuilder(RISCV::PseudoCALL).addOperand(CallTargetMCOp)); in LowerSTATEPOINT()
219 EmitToStreamer(OutStreamer, MCInstBuilder(RISCV::JAL) in LowerSTATEPOINT()
220 .addReg(RISCV::X1) in LowerSTATEPOINT()
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H A DRISCVMergeBaseOffset.cpp87 if (Hi.getOpcode() != RISCV::LUI && Hi.getOpcode() != RISCV::AUIPC && in INITIALIZE_PASS()
88 Hi.getOpcode() != RISCV::PseudoMovAddr) in INITIALIZE_PASS()
93 Hi.getOpcode() == RISCV::AUIPC ? RISCVII::MO_PCREL_HI : RISCVII::MO_HI; in INITIALIZE_PASS()
101 if (Hi.getOpcode() == RISCV::PseudoMovAddr) { in INITIALIZE_PASS()
111 if (Lo->getOpcode() != RISCV::ADDI) in INITIALIZE_PASS()
116 if (Hi.getOpcode() == RISCV::LUI || Hi.getOpcode() == RISCV::PseudoMovAddr) { in INITIALIZE_PASS()
122 assert(Hi.getOpcode() == RISCV::AUIPC); in INITIALIZE_PASS()
150 if (Hi.getOpcode() != RISCV::AUIPC) in foldOffset()
185 assert((TailAdd.getOpcode() == RISCV::ADD) && "Expected ADD instruction!"); in foldLargeOffset()
195 if (OffsetTail.getOpcode() == RISCV::ADDI || in foldLargeOffset()
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H A DRISCVTargetTransformInfo.cpp54 case RISCV::VRGATHER_VI: in getRISCVInstructionCost()
57 case RISCV::VRGATHER_VV: in getRISCVInstructionCost()
60 case RISCV::VSLIDEUP_VI: in getRISCVInstructionCost()
61 case RISCV::VSLIDEDOWN_VI: in getRISCVInstructionCost()
64 case RISCV::VSLIDEUP_VX: in getRISCVInstructionCost()
65 case RISCV::VSLIDEDOWN_VX: in getRISCVInstructionCost()
68 case RISCV::VREDMAX_VS: in getRISCVInstructionCost()
69 case RISCV::VREDMIN_VS: in getRISCVInstructionCost()
70 case RISCV::VREDMAXU_VS: in getRISCVInstructionCost()
71 case RISCV::VREDMINU_VS: in getRISCVInstructionCost()
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H A DRISCVExpandAtomicPseudoInsts.cpp16 #include "RISCV.h"
114 case RISCV::PseudoAtomicLoadNand32: in expandMI()
117 case RISCV::PseudoAtomicLoadNand64: in expandMI()
120 case RISCV::PseudoMaskedAtomicSwap32: in expandMI()
123 case RISCV::PseudoMaskedAtomicLoadAdd32: in expandMI()
125 case RISCV::PseudoMaskedAtomicLoadSub32: in expandMI()
127 case RISCV::PseudoMaskedAtomicLoadNand32: in expandMI()
130 case RISCV::PseudoMaskedAtomicLoadMax32: in expandMI()
133 case RISCV::PseudoMaskedAtomicLoadMin32: in expandMI()
136 case RISCV in expandMI()
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H A DRISCVISelDAGToDAG.cpp37 namespace llvm::RISCV { namespace
67 SDValue VL = CurDAG->getRegister(RISCV::X0, Subtarget->getXLenVT()); in PreprocessISelDAG()
114 CurDAG->getRegister(RISCV::X0, MVT::i64), in PreprocessISelDAG()
177 SDValue SrcReg = CurDAG->getRegister(RISCV::X0, VT); in selectImmSeq()
187 CurDAG->getRegister(RISCV::X0, VT)); in selectImmSeq()
211 CurDAG->getMachineNode(RISCV::PseudoMovImm, DL, VT, in selectImm()
228 CurDAG->getMachineNode(RISCV::SLLI, DL, VT, Lo, in selectImm()
242 RISCV::VRN2M1RegClassID, RISCV::VRN3M1RegClassID, RISCV::VRN4M1RegClassID, in createTuple()
243 RISCV::VRN5M1RegClassID, RISCV::VRN6M1RegClassID, RISCV::VRN7M1RegClassID, in createTuple()
244 RISCV::VRN8M1RegClassID}; in createTuple()
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H A DRISCVVectorPeephole.cpp94 if (Def->getOpcode() == RISCV::SLLI) { in convertToVLMAX()
98 } else if (Def->getOpcode() == RISCV::SRLI) { in convertToVLMAX()
104 if (!Def || Def->getOpcode() != RISCV::PseudoReadVLENB) in convertToVLMAX()
126 VL.ChangeToImmediate(RISCV::VLMaxSentinel); in convertToVLMAX()
133 MaskDef->getOperand(0).getReg() == RISCV::V0); in isAllOnesMask()
145 case RISCV::PseudoVMSET_M_B1: in isAllOnesMask()
146 case RISCV::PseudoVMSET_M_B2: in isAllOnesMask()
147 case RISCV::PseudoVMSET_M_B4: in isAllOnesMask()
148 case RISCV::PseudoVMSET_M_B8: in isAllOnesMask()
149 case RISCV::PseudoVMSET_M_B16: in isAllOnesMask()
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H A DRISCVInsertVSETVLI.cpp68 return MI.getOpcode() == RISCV::PseudoVSETVLI || in isVectorConfigInstr()
69 MI.getOpcode() == RISCV::PseudoVSETVLIX0 || in isVectorConfigInstr()
70 MI.getOpcode() == RISCV::PseudoVSETIVLI; in isVectorConfigInstr()
76 if (MI.getOpcode() != RISCV::PseudoVSETVLIX0) in isVLPreservingConfig()
78 assert(RISCV::X0 == MI.getOperand(1).getReg()); in isVLPreservingConfig()
79 return RISCV::X0 == MI.getOperand(0).getReg(); in isVLPreservingConfig()
83 switch (RISCV::getRVVMCOpcode(MI.getOpcode())) { in isFloatScalarMoveOrScalarSplatInstr()
86 case RISCV::VFMV_S_F: in isFloatScalarMoveOrScalarSplatInstr()
87 case RISCV::VFMV_V_F: in isFloatScalarMoveOrScalarSplatInstr()
93 switch (RISCV::getRVVMCOpcode(MI.getOpcode())) { in isScalarExtractInstr()
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H A DRISCVInsertReadWriteCSR.cpp72 if (MI.getOpcode() == RISCV::SwapFRMImm || in INITIALIZE_PASS()
73 MI.getOpcode() == RISCV::WriteFRMImm) { in INITIALIZE_PASS()
79 if (MI.getOpcode() == RISCV::WriteFRM) { in INITIALIZE_PASS()
86 MI.readsRegister(RISCV::FRM, /*TRI=*/nullptr)) { in INITIALIZE_PASS()
89 BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(RISCV::WriteFRM)) in INITIALIZE_PASS()
96 assert(!MI.modifiesRegister(RISCV::FRM, /*TRI=*/nullptr) && in INITIALIZE_PASS()
107 MI.addOperand(MachineOperand::CreateReg(RISCV::FRM, /*IsDef*/ false, in INITIALIZE_PASS()
118 SavedFRM = MRI->createVirtualRegister(&RISCV::GPRRegClass); in INITIALIZE_PASS()
119 BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(RISCV::SwapFRMImm), SavedFRM) in INITIALIZE_PASS()
123 BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(RISCV::WriteFRMImm)) in INITIALIZE_PASS()
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H A DRISCVFrameLowering.cpp48 {/*ra*/ RISCV::X1, -1}, {/*s0*/ RISCV::X8, -2},
49 {/*s1*/ RISCV::X9, -3}, {/*s2*/ RISCV::X18, -4},
50 {/*s3*/ RISCV::X19, -5}, {/*s4*/ RISCV::X20, -6},
51 {/*s5*/ RISCV::X21, -7}, {/*s6*/ RISCV::X22, -8},
52 {/*s7*/ RISCV::X23, -9}, {/*s8*/ RISCV::X24, -10},
53 {/*s9*/ RISCV::X25, -11}, {/*s10*/ RISCV::X26, -12},
54 {/*s11*/ RISCV::X27, -13}};
77 BuildMI(MBB, MI, DL, TII->get(RISCV::SSPUSH)).addReg(RAReg); in emitSCSPrologue()
83 bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit); in emitSCSPrologue()
88 BuildMI(MBB, MI, DL, TII->get(RISCV::ADDI)) in emitSCSPrologue()
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVELFObjectWriter.cpp68 case RISCV::fixup_riscv_pcrel_hi20: in getRelocType()
70 case RISCV::fixup_riscv_pcrel_lo12_i: in getRelocType()
72 case RISCV::fixup_riscv_pcrel_lo12_s: in getRelocType()
74 case RISCV::fixup_riscv_got_hi20: in getRelocType()
76 case RISCV::fixup_riscv_tls_got_hi20: in getRelocType()
78 case RISCV::fixup_riscv_tls_gd_hi20: in getRelocType()
80 case RISCV::fixup_riscv_tlsdesc_hi20: in getRelocType()
82 case RISCV::fixup_riscv_tlsdesc_load_lo12: in getRelocType()
84 case RISCV::fixup_riscv_tlsdesc_add_lo12: in getRelocType()
86 case RISCV in getRelocType()
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H A DRISCVMCCodeEmitter.cpp126 if (MI.getOpcode() == RISCV::PseudoTAIL) { in expandFunctionCall()
128 Ra = RISCV::X6; in expandFunctionCall()
131 if (STI.hasFeature(RISCV::FeatureStdExtZicfilp)) in expandFunctionCall()
132 Ra = RISCV::X7; in expandFunctionCall()
133 } else if (MI.getOpcode() == RISCV::PseudoCALLReg) { in expandFunctionCall()
136 } else if (MI.getOpcode() == RISCV::PseudoCALL) { in expandFunctionCall()
138 Ra = RISCV::X1; in expandFunctionCall()
139 } else if (MI.getOpcode() == RISCV::PseudoJump) { in expandFunctionCall()
150 TmpInst = MCInstBuilder(RISCV::AUIPC).addReg(Ra).addExpr(CallExpr); in expandFunctionCall()
154 if (MI.getOpcode() == RISCV::PseudoTAIL || in expandFunctionCall()
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H A DRISCVMatInt.cpp25 case RISCV::SLLI: in getInstSeqCost()
26 case RISCV::SRLI: in getInstSeqCost()
29 case RISCV::ADDI: in getInstSeqCost()
30 case RISCV::ADDIW: in getInstSeqCost()
31 case RISCV::LUI: in getInstSeqCost()
51 bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit); in generateInstSeqImpl()
54 if (STI.hasFeature(RISCV::FeatureStdExtZbs) && isPowerOf2_64(Val) && in generateInstSeqImpl()
56 Res.emplace_back(RISCV::BSETI, Log2_64(Val)); in generateInstSeqImpl()
72 Res.emplace_back(RISCV::LUI, Hi20); in generateInstSeqImpl()
75 unsigned AddiOpc = (IsRV64 && Hi20) ? RISCV::ADDIW : RISCV::ADDI; in generateInstSeqImpl()
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H A DRISCVAsmBackend.cpp95 static_assert((std::size(Infos)) == RISCV::NumTargetFixupKinds, in getFixupKindInfo()
131 case RISCV::fixup_riscv_got_hi20: in shouldForceRelocation()
132 case RISCV::fixup_riscv_tls_got_hi20: in shouldForceRelocation()
133 case RISCV::fixup_riscv_tls_gd_hi20: in shouldForceRelocation()
134 case RISCV::fixup_riscv_tlsdesc_hi20: in shouldForceRelocation()
138 return STI->hasFeature(RISCV::FeatureRelax) || ForceRelocs; in shouldForceRelocation()
160 case RISCV::fixup_riscv_rvc_branch: in fixupNeedsRelaxationAdvanced()
164 case RISCV::fixup_riscv_rvc_jump: in fixupNeedsRelaxationAdvanced()
168 case RISCV::fixup_riscv_branch: in fixupNeedsRelaxationAdvanced()
181 case RISCV::C_BEQZ: in relaxInstruction()
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H A DRISCVMCTargetDesc.cpp48 using namespace RISCV;
65 InitRISCVMCRegisterInfo(X, RISCV::X1); in createRISCVMCRegisterInfo()
74 MCRegister SP = MRI.getDwarfRegNum(RISCV::X2, true); in createRISCVMCAsmInfo()
130 return Reg >= RISCV::X0 && Reg <= RISCV::X31; in isGPR()
134 assert(isGPR(Reg) && Reg != RISCV::X0 && "Invalid GPR reg"); in getRegIndex()
135 return Reg - RISCV::X1; in getRegIndex()
139 if (Reg == RISCV::X0) in setGPRState()
153 if (Reg == RISCV::X0) in getGPRState()
192 case RISCV::AUIPC: in updateState()
211 if (Inst.getOpcode() == RISCV::C_JAL || Inst.getOpcode() == RISCV::C_J) { in evaluateBranch()
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H A DRISCVFixupKinds.h16 #undef RISCV
18 namespace llvm::RISCV {
110 } // end namespace llvm::RISCV
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCA/
H A DRISCVCustomBehaviour.cpp105 if (Inst.getOpcode() == RISCV::VSETVLI || in createInstruments()
106 Inst.getOpcode() == RISCV::VSETIVLI) { in createInstruments()
172 case RISCV::VLM_V: in getEEWAndEMUL()
173 case RISCV::VSM_V: in getEEWAndEMUL()
174 case RISCV::VLE8_V: in getEEWAndEMUL()
175 case RISCV::VSE8_V: in getEEWAndEMUL()
176 case RISCV::VLSE8_V: in getEEWAndEMUL()
177 case RISCV::VSSE8_V: in getEEWAndEMUL()
180 case RISCV::VLE16_V: in getEEWAndEMUL()
181 case RISCV::VSE16_V: in getEEWAndEMUL()
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVRegisterBankInfo.cpp26 namespace RISCV { namespace
121 case RISCV::GPRRegClassID: in getRegBankFromRegClass()
122 case RISCV::GPRF16RegClassID: in getRegBankFromRegClass()
123 case RISCV::GPRF32RegClassID: in getRegBankFromRegClass()
124 case RISCV::GPRNoX0RegClassID: in getRegBankFromRegClass()
125 case RISCV::GPRNoX0X2RegClassID: in getRegBankFromRegClass()
126 case RISCV::GPRJALRRegClassID: in getRegBankFromRegClass()
127 case RISCV::GPRJALRNonX7RegClassID: in getRegBankFromRegClass()
128 case RISCV::GPRTCRegClassID: in getRegBankFromRegClass()
129 case RISCV::GPRTCNonX7RegClassID: in getRegBankFromRegClass()
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H A DRISCVInstructionSelector.cpp218 ShAmtReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); in selectShiftMask()
219 unsigned NegOpc = Subtarget->is64Bit() ? RISCV::SUBW : RISCV::SUB; in selectShiftMask()
222 .buildInstr(NegOpc, {ShAmtReg}, {Register(RISCV::X0), Reg}); in selectShiftMask()
229 ShAmtReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); in selectShiftMask()
232 .buildInstr(RISCV::XORI, {ShAmtReg}, {Reg}) in selectShiftMask()
278 Register DstReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); in selectSHXADDOp()
281 .buildInstr(RISCV::SRLI, {DstReg}, {RegY}) in selectSHXADDOp()
290 Register DstReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); in selectSHXADDOp()
293 .buildInstr(RISCV::SRLI, {DstReg}, {RegY}) in selectSHXADDOp()
329 Register DstReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); in selectSHXADDOp()
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/Disassembler/
H A DRISCVDisassembler.cpp74 bool IsRVE = Decoder->getSubtargetInfo().hasFeature(RISCV::FeatureStdExtE); in DecodeGPRRegisterClass()
79 MCRegister Reg = RISCV::X0 + RegNo; in DecodeGPRRegisterClass()
87 MCRegister Reg = RISCV::X0 + RegNo; in DecodeGPRX1X5RegisterClass()
88 if (Reg != RISCV::X1 && Reg != RISCV::X5) in DecodeGPRX1X5RegisterClass()
101 MCRegister Reg = RISCV::F0_H + RegNo; in DecodeFPR16RegisterClass()
112 MCRegister Reg = RISCV::F0_F + RegNo; in DecodeFPR32RegisterClass()
123 MCRegister Reg = RISCV::F8_F + RegNo; in DecodeFPR32CRegisterClass()
134 MCRegister Reg = RISCV::F0_D + RegNo; in DecodeFPR64RegisterClass()
145 MCRegister Reg = RISCV::F8_D + RegNo; in DecodeFPR64CRegisterClass()
176 MCRegister Reg = RISCV::X8 + RegNo; in DecodeGPRCRegisterClass()
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/
H A DRISCVAsmParser.cpp56 extern const SubtargetFeatureKV RISCVFeatureKV[RISCV::NumSubtargetFeatures];
85 bool isRV64() const { return getSTI().hasFeature(RISCV::Feature64Bit); } in isRV64()
86 bool isRVE() const { return getSTI().hasFeature(RISCV::FeatureStdExtE); } in isRVE()
88 return getSTI().hasFeature(RISCV::Experimental); in enableExperimentalExtension()
305 if (ABIName.ends_with("f") && !getSTI().hasFeature(RISCV::FeatureStdExtF)) { in RISCVAsmParser()
310 !getSTI().hasFeature(RISCV::FeatureStdExtD)) { in RISCVAsmParser()
456 return Kind == KindTy::Register && Reg.RegNum == RISCV::V0; in isV0Reg()
460 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg.RegNum) || in isAnyReg()
461 RISCVMCRegisterClasses[RISCV::FPR64RegClassID].contains(Reg.RegNum) || in isAnyReg()
462 RISCVMCRegisterClasses[RISCV::VRRegClassID].contains(Reg.RegNum)); in isAnyReg()
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