Lines Matching refs:RISCV
41 static_assert(RISCV::X1 == RISCV::X0 + 1, "Register list not consecutive");
42 static_assert(RISCV::X31 == RISCV::X0 + 31, "Register list not consecutive");
43 static_assert(RISCV::F1_H == RISCV::F0_H + 1, "Register list not consecutive");
44 static_assert(RISCV::F31_H == RISCV::F0_H + 31,
46 static_assert(RISCV::F1_F == RISCV::F0_F + 1, "Register list not consecutive");
47 static_assert(RISCV::F31_F == RISCV::F0_F + 31,
49 static_assert(RISCV::F1_D == RISCV::F0_D + 1, "Register list not consecutive");
50 static_assert(RISCV::F31_D == RISCV::F0_D + 31,
52 static_assert(RISCV::V1 == RISCV::V0 + 1, "Register list not consecutive");
53 static_assert(RISCV::V31 == RISCV::V0 + 31, "Register list not consecutive");
56 : RISCVGenRegisterInfo(RISCV::X1, /*DwarfFlavour*/0, /*EHFlavor*/0, in RISCVRegisterInfo()
118 markSuperRegs(Reserved, RISCV::X2); // sp in getReservedRegs()
119 markSuperRegs(Reserved, RISCV::X3); // gp in getReservedRegs()
120 markSuperRegs(Reserved, RISCV::X4); // tp in getReservedRegs()
122 markSuperRegs(Reserved, RISCV::X8); // fp in getReservedRegs()
130 markSuperRegs(Reserved, RISCV::DUMMY_REG_PAIR_WITH_X0); in getReservedRegs()
134 for (MCPhysReg Reg = RISCV::X16; Reg <= RISCV::X31; Reg++) in getReservedRegs()
138 markSuperRegs(Reserved, RISCV::VL); in getReservedRegs()
139 markSuperRegs(Reserved, RISCV::VTYPE); in getReservedRegs()
140 markSuperRegs(Reserved, RISCV::VXSAT); in getReservedRegs()
141 markSuperRegs(Reserved, RISCV::VXRM); in getReservedRegs()
144 markSuperRegs(Reserved, RISCV::FRM); in getReservedRegs()
145 markSuperRegs(Reserved, RISCV::FFLAGS); in getReservedRegs()
148 markSuperRegs(Reserved, RISCV::VCIX_STATE); in getReservedRegs()
153 markSuperRegs(Reserved, RISCV::X23); in getReservedRegs()
154 markSuperRegs(Reserved, RISCV::X27); in getReservedRegs()
158 markSuperRegs(Reserved, RISCV::SSP); in getReservedRegs()
191 unsigned ScalableAdjOpc = RISCV::ADD; in adjustReg()
195 ScalableAdjOpc = RISCV::SUB; in adjustReg()
200 ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); in adjustReg()
208 BuildMI(MBB, II, DL, TII->get(RISCV::PseudoReadVLENB), ScratchReg) in adjustReg()
211 if (ScalableAdjOpc == RISCV::ADD && ST.hasStdExtZba() && in adjustReg()
213 unsigned Opc = NumOfVReg == 2 ? RISCV::SH1ADD : in adjustReg()
214 (NumOfVReg == 4 ? RISCV::SH2ADD : RISCV::SH3ADD); in adjustReg()
235 BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), DestReg) in adjustReg()
253 BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), DestReg) in adjustReg()
257 BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), DestReg) in adjustReg()
272 Opc = RISCV::SH3ADD; in adjustReg()
275 Opc = RISCV::SH2ADD; in adjustReg()
279 Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); in adjustReg()
289 unsigned Opc = RISCV::ADD; in adjustReg()
292 Opc = RISCV::SUB; in adjustReg()
295 Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); in adjustReg()
314 auto ZvlssegInfo = RISCV::isRVVSpillForZvlsseg(II->getOpcode()); in lowerVSPILL()
323 Opcode = RISCV::VS1R_V; in lowerVSPILL()
324 SubRegIdx = RISCV::sub_vrm1_0; in lowerVSPILL()
327 Opcode = RISCV::VS2R_V; in lowerVSPILL()
328 SubRegIdx = RISCV::sub_vrm2_0; in lowerVSPILL()
331 Opcode = RISCV::VS4R_V; in lowerVSPILL()
332 SubRegIdx = RISCV::sub_vrm4_0; in lowerVSPILL()
335 static_assert(RISCV::sub_vrm1_7 == RISCV::sub_vrm1_0 + 7, in lowerVSPILL()
337 static_assert(RISCV::sub_vrm2_3 == RISCV::sub_vrm2_0 + 3, in lowerVSPILL()
339 static_assert(RISCV::sub_vrm4_1 == RISCV::sub_vrm4_0 + 1, in lowerVSPILL()
342 Register VL = MRI.createVirtualRegister(&RISCV::GPRRegClass); in lowerVSPILL()
349 BuildMI(MBB, II, DL, TII->get(RISCV::PseudoReadVLENB), VL); in lowerVSPILL()
352 BuildMI(MBB, II, DL, TII->get(RISCV::SLLI), VL) in lowerVSPILL()
360 Register NewBase = MRI.createVirtualRegister(&RISCV::GPRRegClass); in lowerVSPILL()
372 BuildMI(MBB, II, DL, TII->get(RISCV::ADD), NewBase) in lowerVSPILL()
391 auto ZvlssegInfo = RISCV::isRVVSpillForZvlsseg(II->getOpcode()); in lowerVRELOAD()
400 Opcode = RISCV::VL1RE8_V; in lowerVRELOAD()
401 SubRegIdx = RISCV::sub_vrm1_0; in lowerVRELOAD()
404 Opcode = RISCV::VL2RE8_V; in lowerVRELOAD()
405 SubRegIdx = RISCV::sub_vrm2_0; in lowerVRELOAD()
408 Opcode = RISCV::VL4RE8_V; in lowerVRELOAD()
409 SubRegIdx = RISCV::sub_vrm4_0; in lowerVRELOAD()
412 static_assert(RISCV::sub_vrm1_7 == RISCV::sub_vrm1_0 + 7, in lowerVRELOAD()
414 static_assert(RISCV::sub_vrm2_3 == RISCV::sub_vrm2_0 + 3, in lowerVRELOAD()
416 static_assert(RISCV::sub_vrm4_1 == RISCV::sub_vrm4_0 + 1, in lowerVRELOAD()
419 Register VL = MRI.createVirtualRegister(&RISCV::GPRRegClass); in lowerVRELOAD()
426 BuildMI(MBB, II, DL, TII->get(RISCV::PseudoReadVLENB), VL); in lowerVRELOAD()
429 BuildMI(MBB, II, DL, TII->get(RISCV::SLLI), VL) in lowerVRELOAD()
437 Register NewBase = MRI.createVirtualRegister(&RISCV::GPRRegClass); in lowerVRELOAD()
444 BuildMI(MBB, II, DL, TII->get(RISCV::ADD), NewBase) in lowerVRELOAD()
467 bool IsRVVSpill = RISCV::isRVVSpill(MI); in eliminateFrameIndex()
493 if (Opc == RISCV::ADDI && !isInt<12>(Val)) { in eliminateFrameIndex()
500 } else if ((Opc == RISCV::PREFETCH_I || Opc == RISCV::PREFETCH_R || in eliminateFrameIndex()
501 Opc == RISCV::PREFETCH_W) && in eliminateFrameIndex()
505 } else if ((Opc == RISCV::PseudoRV32ZdinxLD || in eliminateFrameIndex()
506 Opc == RISCV::PseudoRV32ZdinxSD) && in eliminateFrameIndex()
524 if (MI.getOpcode() == RISCV::ADDI) in eliminateFrameIndex()
527 DestReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); in eliminateFrameIndex()
540 if (MI.getOpcode() == RISCV::ADDI && in eliminateFrameIndex()
552 case RISCV::PseudoVSPILL2_M1: in eliminateFrameIndex()
553 case RISCV::PseudoVSPILL2_M2: in eliminateFrameIndex()
554 case RISCV::PseudoVSPILL2_M4: in eliminateFrameIndex()
555 case RISCV::PseudoVSPILL3_M1: in eliminateFrameIndex()
556 case RISCV::PseudoVSPILL3_M2: in eliminateFrameIndex()
557 case RISCV::PseudoVSPILL4_M1: in eliminateFrameIndex()
558 case RISCV::PseudoVSPILL4_M2: in eliminateFrameIndex()
559 case RISCV::PseudoVSPILL5_M1: in eliminateFrameIndex()
560 case RISCV::PseudoVSPILL6_M1: in eliminateFrameIndex()
561 case RISCV::PseudoVSPILL7_M1: in eliminateFrameIndex()
562 case RISCV::PseudoVSPILL8_M1: in eliminateFrameIndex()
565 case RISCV::PseudoVRELOAD2_M1: in eliminateFrameIndex()
566 case RISCV::PseudoVRELOAD2_M2: in eliminateFrameIndex()
567 case RISCV::PseudoVRELOAD2_M4: in eliminateFrameIndex()
568 case RISCV::PseudoVRELOAD3_M1: in eliminateFrameIndex()
569 case RISCV::PseudoVRELOAD3_M2: in eliminateFrameIndex()
570 case RISCV::PseudoVRELOAD4_M1: in eliminateFrameIndex()
571 case RISCV::PseudoVRELOAD4_M2: in eliminateFrameIndex()
572 case RISCV::PseudoVRELOAD5_M1: in eliminateFrameIndex()
573 case RISCV::PseudoVRELOAD6_M1: in eliminateFrameIndex()
574 case RISCV::PseudoVRELOAD7_M1: in eliminateFrameIndex()
575 case RISCV::PseudoVRELOAD8_M1: in eliminateFrameIndex()
624 if (RISCV::GPRRegClass.contains(Reg)) in needsFrameBaseReg()
625 CalleeSavedSize += getSpillSize(RISCV::GPRRegClass); in needsFrameBaseReg()
626 else if (RISCV::FPR64RegClass.contains(Reg)) in needsFrameBaseReg()
627 CalleeSavedSize += getSpillSize(RISCV::FPR64RegClass); in needsFrameBaseReg()
628 else if (RISCV::FPR32RegClass.contains(Reg)) in needsFrameBaseReg()
629 CalleeSavedSize += getSpillSize(RISCV::FPR32RegClass); in needsFrameBaseReg()
634 return !isFrameOffsetLegal(MI, RISCV::X8, MaxFPOffset); in needsFrameBaseReg()
643 return !isFrameOffsetLegal(MI, RISCV::X2, MaxSPOffset); in needsFrameBaseReg()
676 Register BaseReg = MFI.createVirtualRegister(&RISCV::GPRRegClass); in materializeFrameBaseRegister()
677 BuildMI(*MBB, MBBI, DL, TII->get(RISCV::ADDI), BaseReg) in materializeFrameBaseRegister()
715 return TFI->hasFP(MF) ? RISCV::X8 : RISCV::X2; in getFrameRegister()
752 if (RC == &RISCV::VMV0RegClass) in getLargestLegalSuperClass()
753 return &RISCV::VRRegClass; in getLargestLegalSuperClass()
754 if (RC == &RISCV::VRNoV0RegClass) in getLargestLegalSuperClass()
755 return &RISCV::VRRegClass; in getLargestLegalSuperClass()
756 if (RC == &RISCV::VRM2NoV0RegClass) in getLargestLegalSuperClass()
757 return &RISCV::VRM2RegClass; in getLargestLegalSuperClass()
758 if (RC == &RISCV::VRM4NoV0RegClass) in getLargestLegalSuperClass()
759 return &RISCV::VRM4RegClass; in getLargestLegalSuperClass()
760 if (RC == &RISCV::VRM8NoV0RegClass) in getLargestLegalSuperClass()
761 return &RISCV::VRM8RegClass; in getLargestLegalSuperClass()
775 unsigned VLENB = getDwarfRegNum(RISCV::VLENB, true); in getOffsetOpcodes()
825 if (PhysReg && (!NeedGPRC || RISCV::GPRCRegClass.contains(PhysReg)) && in getRegAllocationHints()
839 case RISCV::AND: in getRegAllocationHints()
840 case RISCV::OR: in getRegAllocationHints()
841 case RISCV::XOR: in getRegAllocationHints()
842 case RISCV::SUB: in getRegAllocationHints()
843 case RISCV::ADDW: in getRegAllocationHints()
844 case RISCV::SUBW: in getRegAllocationHints()
847 case RISCV::ANDI: { in getRegAllocationHints()
857 case RISCV::SRAI: in getRegAllocationHints()
858 case RISCV::SRLI: in getRegAllocationHints()
861 case RISCV::ADD: in getRegAllocationHints()
862 case RISCV::SLLI: in getRegAllocationHints()
864 case RISCV::ADDI: in getRegAllocationHints()
865 case RISCV::ADDIW: in getRegAllocationHints()
867 case RISCV::MUL: in getRegAllocationHints()
868 case RISCV::SEXT_B: in getRegAllocationHints()
869 case RISCV::SEXT_H: in getRegAllocationHints()
870 case RISCV::ZEXT_H_RV32: in getRegAllocationHints()
871 case RISCV::ZEXT_H_RV64: in getRegAllocationHints()
875 case RISCV::ADD_UW: in getRegAllocationHints()
879 MI.getOperand(2).getReg() == RISCV::X0; in getRegAllocationHints()
880 case RISCV::XORI: in getRegAllocationHints()
897 return PhysReg && RISCV::GPRCRegClass.contains(PhysReg); in getRegAllocationHints()
907 MI.getOpcode() == RISCV::ADD_UW || in getRegAllocationHints()