53 extern const SubtargetFeatureKV RISCVFeatureKV[RISCV::NumSubtargetFeatures];
133         MII->getOpcode() == RISCV::DBG_VALUE ||  in LowerSTACKMAP()
168       RISCVMatInt::generateMCInstSeq(CallTarget, *STI, RISCV::X1, Seq);  in LowerPATCHPOINT()
173       bool Compressed = EmitToStreamer(OutStreamer, MCInstBuilder(RISCV::JALR)  in LowerPATCHPOINT()
174                                                         .addReg(RISCV::X1)  in LowerPATCHPOINT()
175                                                         .addReg(RISCV::X1)  in LowerPATCHPOINT()
183                    MCInstBuilder(RISCV::PseudoCALL).addOperand(CallTargetMCOp));  in LowerPATCHPOINT()
215           MCInstBuilder(RISCV::PseudoCALL).addOperand(CallTargetMCOp));  in LowerSTATEPOINT()
219       EmitToStreamer(OutStreamer, MCInstBuilder(RISCV::JAL)  in LowerSTATEPOINT()
220                                       .addReg(RISCV::X1)  in LowerSTATEPOINT()
225       EmitToStreamer(OutStreamer, MCInstBuilder(RISCV::JALR)  in LowerSTATEPOINT()
226                                       .addReg(RISCV::X1)  in LowerSTATEPOINT()
276     Hint.setOpcode(RISCV::C_ADD_HINT);  in emitNTLHint()
278     Hint.setOpcode(RISCV::ADD);  in emitNTLHint()
280   Hint.addOperand(MCOperand::createReg(RISCV::X0));  in emitNTLHint()
281   Hint.addOperand(MCOperand::createReg(RISCV::X0));  in emitNTLHint()
282   Hint.addOperand(MCOperand::createReg(RISCV::X2 + NontemporalMode));  in emitNTLHint()
299   case RISCV::HWASAN_CHECK_MEMACCESS_SHORTGRANULES:  in emitInstruction()
302   case RISCV::KCFI_CHECK:  in emitInstruction()
305   case RISCV::PseudoRVVInitUndefM1:  in emitInstruction()
306   case RISCV::PseudoRVVInitUndefM2:  in emitInstruction()
307   case RISCV::PseudoRVVInitUndefM4:  in emitInstruction()
308   case RISCV::PseudoRVVInitUndefM8:  in emitInstruction()
339         OS << RISCVInstPrinter::getRegisterName(RISCV::X0);  in PrintAsmOperand()
520     std::string SymName = "__hwasan_check_x" + utostr(Reg - RISCV::X0) + "_" +  in LowerHWASAN_CHECK_MEMACCESS()
527   EmitToStreamer(*OutStreamer, MCInstBuilder(RISCV::PseudoCALL).addExpr(Expr));  in LowerHWASAN_CHECK_MEMACCESS()
542   unsigned ScratchRegs[] = {RISCV::X6, RISCV::X7};  in LowerKCFI_CHECK()
543   unsigned NextReg = RISCV::X28;  in LowerKCFI_CHECK()
553     if (Reg > RISCV::X31)  in LowerKCFI_CHECK()
557   if (AddrReg == RISCV::X0) {  in LowerKCFI_CHECK()
560     EmitToStreamer(*OutStreamer, MCInstBuilder(RISCV::ADDI)  in LowerKCFI_CHECK()
562                                      .addReg(RISCV::X0)  in LowerKCFI_CHECK()
576     EmitToStreamer(*OutStreamer, MCInstBuilder(RISCV::LW)  in LowerKCFI_CHECK()
589         MCInstBuilder(RISCV::LUI).addReg(ScratchRegs[1]).addImm(Hi20));  in LowerKCFI_CHECK()
593                    MCInstBuilder((STI->hasFeature(RISCV::Feature64Bit) && Hi20)  in LowerKCFI_CHECK()
594                                      ? RISCV::ADDIW  in LowerKCFI_CHECK()
595                                      : RISCV::ADDI)  in LowerKCFI_CHECK()
604                  MCInstBuilder(RISCV::BEQ)  in LowerKCFI_CHECK()
611   EmitToStreamer(*OutStreamer, MCInstBuilder(RISCV::EBREAK));  in LowerKCFI_CHECK()
658         MCInstBuilder(RISCV::SLLI).addReg(RISCV::X6).addReg(Reg).addImm(8),  in EmitHwasanMemaccessSymbols()
660     OutStreamer->emitInstruction(MCInstBuilder(RISCV::SRLI)  in EmitHwasanMemaccessSymbols()
661                                      .addReg(RISCV::X6)  in EmitHwasanMemaccessSymbols()
662                                      .addReg(RISCV::X6)  in EmitHwasanMemaccessSymbols()
666     OutStreamer->emitInstruction(MCInstBuilder(RISCV::ADD)  in EmitHwasanMemaccessSymbols()
667                                      .addReg(RISCV::X6)  in EmitHwasanMemaccessSymbols()
668                                      .addReg(RISCV::X5)  in EmitHwasanMemaccessSymbols()
669                                      .addReg(RISCV::X6),  in EmitHwasanMemaccessSymbols()
672         MCInstBuilder(RISCV::LBU).addReg(RISCV::X6).addReg(RISCV::X6).addImm(0),  in EmitHwasanMemaccessSymbols()
676         MCInstBuilder(RISCV::SRLI).addReg(RISCV::X7).addReg(Reg).addImm(56),  in EmitHwasanMemaccessSymbols()
681         MCInstBuilder(RISCV::BNE)  in EmitHwasanMemaccessSymbols()
682             .addReg(RISCV::X7)  in EmitHwasanMemaccessSymbols()
683             .addReg(RISCV::X6)  in EmitHwasanMemaccessSymbols()
689     OutStreamer->emitInstruction(MCInstBuilder(RISCV::JALR)  in EmitHwasanMemaccessSymbols()
690                                      .addReg(RISCV::X0)  in EmitHwasanMemaccessSymbols()
691                                      .addReg(RISCV::X1)  in EmitHwasanMemaccessSymbols()
696     OutStreamer->emitInstruction(MCInstBuilder(RISCV::ADDI)  in EmitHwasanMemaccessSymbols()
697                                      .addReg(RISCV::X28)  in EmitHwasanMemaccessSymbols()
698                                      .addReg(RISCV::X0)  in EmitHwasanMemaccessSymbols()
703         MCInstBuilder(RISCV::BGEU)  in EmitHwasanMemaccessSymbols()
704             .addReg(RISCV::X6)  in EmitHwasanMemaccessSymbols()
705             .addReg(RISCV::X28)  in EmitHwasanMemaccessSymbols()
710         MCInstBuilder(RISCV::ANDI).addReg(RISCV::X28).addReg(Reg).addImm(0xF),  in EmitHwasanMemaccessSymbols()
714       OutStreamer->emitInstruction(MCInstBuilder(RISCV::ADDI)  in EmitHwasanMemaccessSymbols()
715                                        .addReg(RISCV::X28)  in EmitHwasanMemaccessSymbols()
716                                        .addReg(RISCV::X28)  in EmitHwasanMemaccessSymbols()
720         MCInstBuilder(RISCV::BGE)  in EmitHwasanMemaccessSymbols()
721             .addReg(RISCV::X28)  in EmitHwasanMemaccessSymbols()
722             .addReg(RISCV::X6)  in EmitHwasanMemaccessSymbols()
727         MCInstBuilder(RISCV::ORI).addReg(RISCV::X6).addReg(Reg).addImm(0xF),  in EmitHwasanMemaccessSymbols()
730         MCInstBuilder(RISCV::LBU).addReg(RISCV::X6).addReg(RISCV::X6).addImm(0),  in EmitHwasanMemaccessSymbols()
733         MCInstBuilder(RISCV::BEQ)  in EmitHwasanMemaccessSymbols()
734             .addReg(RISCV::X6)  in EmitHwasanMemaccessSymbols()
735             .addReg(RISCV::X7)  in EmitHwasanMemaccessSymbols()
776     OutStreamer->emitInstruction(MCInstBuilder(RISCV::ADDI)  in EmitHwasanMemaccessSymbols()
777                                      .addReg(RISCV::X2)  in EmitHwasanMemaccessSymbols()
778                                      .addReg(RISCV::X2)  in EmitHwasanMemaccessSymbols()
783     OutStreamer->emitInstruction(MCInstBuilder(RISCV::SD)  in EmitHwasanMemaccessSymbols()
784                                      .addReg(RISCV::X10)  in EmitHwasanMemaccessSymbols()
785                                      .addReg(RISCV::X2)  in EmitHwasanMemaccessSymbols()
789     OutStreamer->emitInstruction(MCInstBuilder(RISCV::SD)  in EmitHwasanMemaccessSymbols()
790                                      .addReg(RISCV::X11)  in EmitHwasanMemaccessSymbols()
791                                      .addReg(RISCV::X2)  in EmitHwasanMemaccessSymbols()
797         MCInstBuilder(RISCV::SD).addReg(RISCV::X8).addReg(RISCV::X2).addImm(8 *  in EmitHwasanMemaccessSymbols()
802         MCInstBuilder(RISCV::SD).addReg(RISCV::X1).addReg(RISCV::X2).addImm(1 *  in EmitHwasanMemaccessSymbols()
805     if (Reg != RISCV::X10)  in EmitHwasanMemaccessSymbols()
806       OutStreamer->emitInstruction(MCInstBuilder(RISCV::ADDI)  in EmitHwasanMemaccessSymbols()
807                                        .addReg(RISCV::X10)  in EmitHwasanMemaccessSymbols()
812         MCInstBuilder(RISCV::ADDI)  in EmitHwasanMemaccessSymbols()
813             .addReg(RISCV::X11)  in EmitHwasanMemaccessSymbols()
814             .addReg(RISCV::X0)  in EmitHwasanMemaccessSymbols()
818     OutStreamer->emitInstruction(MCInstBuilder(RISCV::PseudoCALL).addExpr(Expr),  in EmitHwasanMemaccessSymbols()
971   bool hasVLOutput = RISCV::isFaultFirstLoad(*MI);  in lowerRISCVVMachineInstrToMCInst()
998       if (RISCV::VRM2RegClass.contains(Reg) ||  in lowerRISCVVMachineInstrToMCInst()
999           RISCV::VRM4RegClass.contains(Reg) ||  in lowerRISCVVMachineInstrToMCInst()
1000           RISCV::VRM8RegClass.contains(Reg)) {  in lowerRISCVVMachineInstrToMCInst()
1001         Reg = TRI->getSubReg(Reg, RISCV::sub_vrm1_0);  in lowerRISCVVMachineInstrToMCInst()
1003       } else if (RISCV::FPR16RegClass.contains(Reg)) {  in lowerRISCVVMachineInstrToMCInst()
1005             TRI->getMatchingSuperReg(Reg, RISCV::sub_16, &RISCV::FPR32RegClass);  in lowerRISCVVMachineInstrToMCInst()
1007       } else if (RISCV::FPR64RegClass.contains(Reg)) {  in lowerRISCVVMachineInstrToMCInst()
1008         Reg = TRI->getSubReg(Reg, RISCV::sub_32);  in lowerRISCVVMachineInstrToMCInst()
1010       } else if (RISCV::VRN2M1RegClass.contains(Reg) ||  in lowerRISCVVMachineInstrToMCInst()
1011                  RISCV::VRN2M2RegClass.contains(Reg) ||  in lowerRISCVVMachineInstrToMCInst()
1012                  RISCV::VRN2M4RegClass.contains(Reg) ||  in lowerRISCVVMachineInstrToMCInst()
1013                  RISCV::VRN3M1RegClass.contains(Reg) ||  in lowerRISCVVMachineInstrToMCInst()
1014                  RISCV::VRN3M2RegClass.contains(Reg) ||  in lowerRISCVVMachineInstrToMCInst()
1015                  RISCV::VRN4M1RegClass.contains(Reg) ||  in lowerRISCVVMachineInstrToMCInst()
1016                  RISCV::VRN4M2RegClass.contains(Reg) ||  in lowerRISCVVMachineInstrToMCInst()
1017                  RISCV::VRN5M1RegClass.contains(Reg) ||  in lowerRISCVVMachineInstrToMCInst()
1018                  RISCV::VRN6M1RegClass.contains(Reg) ||  in lowerRISCVVMachineInstrToMCInst()
1019                  RISCV::VRN7M1RegClass.contains(Reg) ||  in lowerRISCVVMachineInstrToMCInst()
1020                  RISCV::VRN8M1RegClass.contains(Reg)) {  in lowerRISCVVMachineInstrToMCInst()
1021         Reg = TRI->getSubReg(Reg, RISCV::sub_vrm1_0);  in lowerRISCVVMachineInstrToMCInst()
1040                RISCV::VMV0RegClassID &&  in lowerRISCVVMachineInstrToMCInst()
1042     OutMI.addOperand(MCOperand::createReg(RISCV::NoRegister));  in lowerRISCVVMachineInstrToMCInst()