108   case RISCV::PseudoRV32ZdinxSD:  in expandMI()
110   case RISCV::PseudoRV32ZdinxLD:  in expandMI()
112   case RISCV::PseudoCCMOVGPRNoX0:  in expandMI()
113   case RISCV::PseudoCCMOVGPR:  in expandMI()
114   case RISCV::PseudoCCADD:  in expandMI()
115   case RISCV::PseudoCCSUB:  in expandMI()
116   case RISCV::PseudoCCAND:  in expandMI()
117   case RISCV::PseudoCCOR:  in expandMI()
118   case RISCV::PseudoCCXOR:  in expandMI()
119   case RISCV::PseudoCCADDW:  in expandMI()
120   case RISCV::PseudoCCSUBW:  in expandMI()
121   case RISCV::PseudoCCSLL:  in expandMI()
122   case RISCV::PseudoCCSRL:  in expandMI()
123   case RISCV::PseudoCCSRA:  in expandMI()
124   case RISCV::PseudoCCADDI:  in expandMI()
125   case RISCV::PseudoCCSLLI:  in expandMI()
126   case RISCV::PseudoCCSRLI:  in expandMI()
127   case RISCV::PseudoCCSRAI:  in expandMI()
128   case RISCV::PseudoCCANDI:  in expandMI()
129   case RISCV::PseudoCCORI:  in expandMI()
130   case RISCV::PseudoCCXORI:  in expandMI()
131   case RISCV::PseudoCCSLLW:  in expandMI()
132   case RISCV::PseudoCCSRLW:  in expandMI()
133   case RISCV::PseudoCCSRAW:  in expandMI()
134   case RISCV::PseudoCCADDIW:  in expandMI()
135   case RISCV::PseudoCCSLLIW:  in expandMI()
136   case RISCV::PseudoCCSRLIW:  in expandMI()
137   case RISCV::PseudoCCSRAIW:  in expandMI()
138   case RISCV::PseudoCCANDN:  in expandMI()
139   case RISCV::PseudoCCORN:  in expandMI()
140   case RISCV::PseudoCCXNOR:  in expandMI()
142   case RISCV::PseudoVSETVLI:  in expandMI()
143   case RISCV::PseudoVSETVLIX0:  in expandMI()
144   case RISCV::PseudoVSETIVLI:  in expandMI()
146   case RISCV::PseudoVMCLR_M_B1:  in expandMI()
147   case RISCV::PseudoVMCLR_M_B2:  in expandMI()
148   case RISCV::PseudoVMCLR_M_B4:  in expandMI()
149   case RISCV::PseudoVMCLR_M_B8:  in expandMI()
150   case RISCV::PseudoVMCLR_M_B16:  in expandMI()
151   case RISCV::PseudoVMCLR_M_B32:  in expandMI()
152   case RISCV::PseudoVMCLR_M_B64:  in expandMI()
154     return expandVMSET_VMCLR(MBB, MBBI, RISCV::VMXOR_MM);  in expandMI()
155   case RISCV::PseudoVMSET_M_B1:  in expandMI()
156   case RISCV::PseudoVMSET_M_B2:  in expandMI()
157   case RISCV::PseudoVMSET_M_B4:  in expandMI()
158   case RISCV::PseudoVMSET_M_B8:  in expandMI()
159   case RISCV::PseudoVMSET_M_B16:  in expandMI()
160   case RISCV::PseudoVMSET_M_B32:  in expandMI()
161   case RISCV::PseudoVMSET_M_B64:  in expandMI()
163     return expandVMSET_VMCLR(MBB, MBBI, RISCV::VMXNOR_MM);  in expandMI()
198   if (MI.getOpcode() == RISCV::PseudoCCMOVGPR ||  in expandCCOp()
199       MI.getOpcode() == RISCV::PseudoCCMOVGPRNoX0) {  in expandCCOp()
201     BuildMI(TrueBB, DL, TII->get(RISCV::ADDI), DestReg)  in expandCCOp()
209     case RISCV::PseudoCCADD:   NewOpc = RISCV::ADD;   break;  in expandCCOp()
210     case RISCV::PseudoCCSUB:   NewOpc = RISCV::SUB;   break;  in expandCCOp()
211     case RISCV::PseudoCCSLL:   NewOpc = RISCV::SLL;   break;  in expandCCOp()
212     case RISCV::PseudoCCSRL:   NewOpc = RISCV::SRL;   break;  in expandCCOp()
213     case RISCV::PseudoCCSRA:   NewOpc = RISCV::SRA;   break;  in expandCCOp()
214     case RISCV::PseudoCCAND:   NewOpc = RISCV::AND;   break;  in expandCCOp()
215     case RISCV::PseudoCCOR:    NewOpc = RISCV::OR;    break;  in expandCCOp()
216     case RISCV::PseudoCCXOR:   NewOpc = RISCV::XOR;   break;  in expandCCOp()
217     case RISCV::PseudoCCADDI:  NewOpc = RISCV::ADDI;  break;  in expandCCOp()
218     case RISCV::PseudoCCSLLI:  NewOpc = RISCV::SLLI;  break;  in expandCCOp()
219     case RISCV::PseudoCCSRLI:  NewOpc = RISCV::SRLI;  break;  in expandCCOp()
220     case RISCV::PseudoCCSRAI:  NewOpc = RISCV::SRAI;  break;  in expandCCOp()
221     case RISCV::PseudoCCANDI:  NewOpc = RISCV::ANDI;  break;  in expandCCOp()
222     case RISCV::PseudoCCORI:   NewOpc = RISCV::ORI;   break;  in expandCCOp()
223     case RISCV::PseudoCCXORI:  NewOpc = RISCV::XORI;  break;  in expandCCOp()
224     case RISCV::PseudoCCADDW:  NewOpc = RISCV::ADDW;  break;  in expandCCOp()
225     case RISCV::PseudoCCSUBW:  NewOpc = RISCV::SUBW;  break;  in expandCCOp()
226     case RISCV::PseudoCCSLLW:  NewOpc = RISCV::SLLW;  break;  in expandCCOp()
227     case RISCV::PseudoCCSRLW:  NewOpc = RISCV::SRLW;  break;  in expandCCOp()
228     case RISCV::PseudoCCSRAW:  NewOpc = RISCV::SRAW;  break;  in expandCCOp()
229     case RISCV::PseudoCCADDIW: NewOpc = RISCV::ADDIW; break;  in expandCCOp()
230     case RISCV::PseudoCCSLLIW: NewOpc = RISCV::SLLIW; break;  in expandCCOp()
231     case RISCV::PseudoCCSRLIW: NewOpc = RISCV::SRLIW; break;  in expandCCOp()
232     case RISCV::PseudoCCSRAIW: NewOpc = RISCV::SRAIW; break;  in expandCCOp()
233     case RISCV::PseudoCCANDN:  NewOpc = RISCV::ANDN;  break;  in expandCCOp()
234     case RISCV::PseudoCCORN:   NewOpc = RISCV::ORN;   break;  in expandCCOp()
235     case RISCV::PseudoCCXNOR:  NewOpc = RISCV::XNOR;  break;  in expandCCOp()
268   assert((MBBI->getOpcode() == RISCV::PseudoVSETVLI ||  in expandVSetVL()
269           MBBI->getOpcode() == RISCV::PseudoVSETVLIX0 ||  in expandVSetVL()
270           MBBI->getOpcode() == RISCV::PseudoVSETIVLI) &&  in expandVSetVL()
273   if (MBBI->getOpcode() == RISCV::PseudoVSETIVLI)  in expandVSetVL()
274     Opcode = RISCV::VSETIVLI;  in expandVSetVL()
276     Opcode = RISCV::VSETVLI;  in expandVSetVL()
312       TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_even);  in expandRV32ZdinxStore()
314       TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_odd);  in expandRV32ZdinxStore()
322   BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))  in expandRV32ZdinxStore()
334     BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))  in expandRV32ZdinxStore()
341     BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))  in expandRV32ZdinxStore()
359       TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_even);  in expandRV32ZdinxLoad()
361       TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_odd);  in expandRV32ZdinxLoad()
374     BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Lo)  in expandRV32ZdinxLoad()
384     BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Hi)  in expandRV32ZdinxLoad()
391     BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Hi)  in expandRV32ZdinxLoad()
399     BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Lo)  in expandRV32ZdinxLoad()
501   case RISCV::PseudoLLA:  in expandMI()
503   case RISCV::PseudoLGA:  in expandMI()
505   case RISCV::PseudoLA_TLS_IE:  in expandMI()
507   case RISCV::PseudoLA_TLS_GD:  in expandMI()
509   case RISCV::PseudoLA_TLSDESC:  in expandMI()
525       MF->getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);  in expandAuipcInstPair()
532       BuildMI(MBB, MBBI, DL, TII->get(RISCV::AUIPC), ScratchReg).add(Symbol);  in expandAuipcInstPair()
551                              RISCV::ADDI);  in expandLoadLocalAddress()
557   unsigned SecondOpcode = STI->is64Bit() ? RISCV::LD : RISCV::LW;  in expandLoadGlobalAddress()
565   unsigned SecondOpcode = STI->is64Bit() ? RISCV::LD : RISCV::LW;  in expandLoadTLSIEAddress()
574                              RISCV::ADDI);  in expandLoadTLSGDAddress()
585   unsigned SecondOpcode = STI.is64Bit() ? RISCV::LD : RISCV::LW;  in expandLoadTLSDescAddress()
589       MF->getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);  in expandLoadTLSDescAddress()
591       MF->getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);  in expandLoadTLSDescAddress()
598       BuildMI(MBB, MBBI, DL, TII->get(RISCV::AUIPC), ScratchReg).add(Symbol);  in expandLoadTLSDescAddress()
605   BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), RISCV::X10)  in expandLoadTLSDescAddress()
609   BuildMI(MBB, MBBI, DL, TII->get(RISCV::PseudoTLSDESCCall), RISCV::X5)  in expandLoadTLSDescAddress()
614   BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADD), FinalReg)  in expandLoadTLSDescAddress()
615       .addReg(RISCV::X10)  in expandLoadTLSDescAddress()
616       .addReg(RISCV::X4);  in expandLoadTLSDescAddress()