48     {/*ra*/ RISCV::X1, -1},   {/*s0*/ RISCV::X8, -2},
49     {/*s1*/ RISCV::X9, -3},   {/*s2*/ RISCV::X18, -4},
50     {/*s3*/ RISCV::X19, -5},  {/*s4*/ RISCV::X20, -6},
51     {/*s5*/ RISCV::X21, -7},  {/*s6*/ RISCV::X22, -8},
52     {/*s7*/ RISCV::X23, -9},  {/*s8*/ RISCV::X24, -10},
53     {/*s9*/ RISCV::X25, -11}, {/*s10*/ RISCV::X26, -12},
54     {/*s11*/ RISCV::X27, -13}};
77     BuildMI(MBB, MI, DL, TII->get(RISCV::SSPUSH)).addReg(RAReg);  in emitSCSPrologue()
83   bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit);  in emitSCSPrologue()
88   BuildMI(MBB, MI, DL, TII->get(RISCV::ADDI))  in emitSCSPrologue()
93   BuildMI(MBB, MI, DL, TII->get(IsRV64 ? RISCV::SD : RISCV::SW))  in emitSCSPrologue()
137     BuildMI(MBB, MI, DL, TII->get(RISCV::SSPOPCHK)).addReg(RAReg);  in emitSCSEpilogue()
143   bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit);  in emitSCSEpilogue()
148   BuildMI(MBB, MI, DL, TII->get(IsRV64 ? RISCV::LD : RISCV::LW))  in emitSCSEpilogue()
153   BuildMI(MBB, MI, DL, TII->get(RISCV::ADDI))  in emitSCSEpilogue()
177   Register MaxReg = RISCV::NoRegister;  in getLibCallID()
184   if (MaxReg == RISCV::NoRegister)  in getLibCallID()
190   case /*s11*/ RISCV::X27: return 12;  in getLibCallID()
191   case /*s10*/ RISCV::X26: return 11;  in getLibCallID()
192   case /*s9*/  RISCV::X25: return 10;  in getLibCallID()
193   case /*s8*/  RISCV::X24: return 9;  in getLibCallID()
194   case /*s7*/  RISCV::X23: return 8;  in getLibCallID()
195   case /*s6*/  RISCV::X22: return 7;  in getLibCallID()
196   case /*s5*/  RISCV::X21: return 6;  in getLibCallID()
197   case /*s4*/  RISCV::X20: return 5;  in getLibCallID()
198   case /*s3*/  RISCV::X19: return 4;  in getLibCallID()
199   case /*s2*/  RISCV::X18: return 3;  in getLibCallID()
200   case /*s1*/  RISCV::X9:  return 2;  in getLibCallID()
201   case /*s0*/  RISCV::X8:  return 1;  in getLibCallID()
202   case /*ra*/  RISCV::X1:  return 0;  in getLibCallID()
267   case RISCV::X27: /*s11*/  in getPushPopEncodingAndNum()
269   case RISCV::X25: /*s9*/  in getPushPopEncodingAndNum()
271   case RISCV::X24: /*s8*/  in getPushPopEncodingAndNum()
273   case RISCV::X23: /*s7*/  in getPushPopEncodingAndNum()
275   case RISCV::X22: /*s6*/  in getPushPopEncodingAndNum()
277   case RISCV::X21: /*s5*/  in getPushPopEncodingAndNum()
279   case RISCV::X20: /*s4*/  in getPushPopEncodingAndNum()
281   case RISCV::X19: /*s3*/  in getPushPopEncodingAndNum()
283   case RISCV::X18: /*s2*/  in getPushPopEncodingAndNum()
285   case RISCV::X9: /*s1*/  in getPushPopEncodingAndNum()
287   case RISCV::X8: /*s0*/  in getPushPopEncodingAndNum()
289   case RISCV::X1: /*ra*/  in getPushPopEncodingAndNum()
297   Register MaxPushPopReg = RISCV::NoRegister;  in getMaxPushPopReg()
304   assert(MaxPushPopReg != RISCV::X26 && "x26 requires x27 to also be pushed");  in getMaxPushPopReg()
376 static Register getFPReg(const RISCVSubtarget &STI) { return RISCV::X8; }  in getFPReg()
379 static Register getSPReg(const RISCVSubtarget &STI) { return RISCV::X2; }  in getSPReg()
447   unsigned DwarfVLenB = TRI.getDwarfRegNum(RISCV::VLENB, true);  in appendScalableVectorExpression()
482   if (Reg == RISCV::X2)  in createDefCFAExpression()
610       FirstFrameSetup->getOpcode() == RISCV::CM_PUSH) {  in emitPrologue()
727         BuildMI(MBB, MBBI, DL, TII->get(RISCV::ANDI), SPReg)  in emitPrologue()
734             MF.getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);  in emitPrologue()
735         BuildMI(MBB, MBBI, DL, TII->get(RISCV::SRLI), VR)  in emitPrologue()
739         BuildMI(MBB, MBBI, DL, TII->get(RISCV::SLLI), SPReg)  in emitPrologue()
749         BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), BPReg)  in emitPrologue()
841       MBBI->getOpcode() == RISCV::CM_POP) {  in emitEpilogue()
896     FrameReg = RISCV::X2;  in getFrameIndexReference()
943       FrameReg = RISCV::X2;  in getFrameIndexReference()
1041     SavedRegs.set(RISCV::X1);  in determineCalleeSaves()
1042     SavedRegs.set(RISCV::X8);  in determineCalleeSaves()
1050   if (RVFI->isPushable(MF) && SavedRegs.test(RISCV::X26))  in determineCalleeSaves()
1051     SavedRegs.set(RISCV::X27);  in determineCalleeSaves()
1139       bool IsRVVSpill = RISCV::isRVVSpill(MI);  in getScavSlotsNumForRVV()
1150         } else if (MI.getOpcode() == RISCV::ADDI && IsScalableVectorID) {  in getScavSlotsNumForRVV()
1224   const TargetRegisterClass *RC = &RISCV::GPRRegClass;  in processFunctionBeforeFrameFinalized()
1292   Register SPReg = RISCV::X2;  in eliminateCallFramePseudoInstr()
1307       if (MI->getOpcode() == RISCV::ADJCALLSTACKDOWN)  in eliminateCallFramePseudoInstr()
1411     if (MaxReg != RISCV::NoRegister) {  in assignCalleeSavedSpillSlots()
1494           BuildMI(MBB, MI, DL, TII.get(RISCV::CM_PUSH))  in spillCalleeSavedRegisters()
1504     BuildMI(MBB, MI, DL, TII.get(RISCV::PseudoCALLReg), RISCV::X5)  in spillCalleeSavedRegisters()
1606           BuildMI(MBB, MI, DL, TII.get(RISCV::CM_POP))  in restoreCalleeSavedRegisters()
1620           BuildMI(MBB, MI, DL, TII.get(RISCV::PseudoTAIL))  in restoreCalleeSavedRegisters()
1626       if (MI != MBB.end() && MI->getOpcode() == RISCV::PseudoRET) {  in restoreCalleeSavedRegisters()
1657   return !RS.isRegUsed(RISCV::X5);  in canUseAsPrologue()