37 namespace llvm::RISCV {  namespace
67       SDValue VL = CurDAG->getRegister(RISCV::X0, Subtarget->getXLenVT());  in PreprocessISelDAG()
114                        CurDAG->getRegister(RISCV::X0, MVT::i64),  in PreprocessISelDAG()
177   SDValue SrcReg = CurDAG->getRegister(RISCV::X0, VT);  in selectImmSeq()
187                                       CurDAG->getRegister(RISCV::X0, VT));  in selectImmSeq()
211         CurDAG->getMachineNode(RISCV::PseudoMovImm, DL, VT,  in selectImm()
228           CurDAG->getMachineNode(RISCV::SLLI, DL, VT, Lo,  in selectImm()
242       RISCV::VRN2M1RegClassID, RISCV::VRN3M1RegClassID, RISCV::VRN4M1RegClassID,  in createTuple()
243       RISCV::VRN5M1RegClassID, RISCV::VRN6M1RegClassID, RISCV::VRN7M1RegClassID,  in createTuple()
244       RISCV::VRN8M1RegClassID};  in createTuple()
245   static const unsigned M2TupleRegClassIDs[] = {RISCV::VRN2M2RegClassID,  in createTuple()
246                                                 RISCV::VRN3M2RegClassID,  in createTuple()
247                                                 RISCV::VRN4M2RegClassID};  in createTuple()
260     static_assert(RISCV::sub_vrm1_7 == RISCV::sub_vrm1_0 + 7,  in createTuple()
262     SubReg0 = RISCV::sub_vrm1_0;  in createTuple()
266     static_assert(RISCV::sub_vrm2_3 == RISCV::sub_vrm2_0 + 3,  in createTuple()
268     SubReg0 = RISCV::sub_vrm2_0;  in createTuple()
272     static_assert(RISCV::sub_vrm4_1 == RISCV::sub_vrm4_0 + 1,  in createTuple()
274     SubReg0 = RISCV::sub_vrm4_0;  in createTuple()
275     RegClassID = RISCV::VRN2M4RegClassID;  in createTuple()
311     Chain = CurDAG->getCopyToReg(Chain, DL, RISCV::V0, Mask, SDValue());  in addVectorLoadStoreOperands()
313     Operands.push_back(CurDAG->getRegister(RISCV::V0, Mask.getValueType()));  in addVectorLoadStoreOperands()
359   const RISCV::VLSEGPseudo *P =  in selectVLSEG()
360       RISCV::getVLSEGPseudo(NF, IsMasked, IsStrided, /*FF*/ false, Log2SEW,  in selectVLSEG()
400   const RISCV::VLSEGPseudo *P =  in selectVLSEGFF()
401       RISCV::getVLSEGPseudo(NF, IsMasked, /*Strided*/ false, /*FF*/ true,  in selectVLSEGFF()
452   const RISCV::VLXSEGPseudo *P = RISCV::getVLXSEGPseudo(  in selectVLXSEG()
493   const RISCV::VSSEGPseudo *P = RISCV::getVSSEGPseudo(  in selectVSSEG()
534   const RISCV::VSXSEGPseudo *P = RISCV::getVSXSEGPseudo(  in selectVSXSEG()
577   unsigned Opcode = RISCV::PseudoVSETVLI;  in selectVSETVLI()
584     VLOperand = CurDAG->getRegister(RISCV::X0, XLenVT);  in selectVSETVLI()
585     Opcode = RISCV::PseudoVSETVLIX0;  in selectVSETVLI()
593         ReplaceNode(Node, CurDAG->getMachineNode(RISCV::PseudoVSETIVLI, DL,  in selectVSETVLI()
665   case ISD::AND: BinOpc = RISCV::ANDI; break;  in tryShrinkShlLogicImm()
666   case ISD::OR:  BinOpc = RISCV::ORI;  break;  in tryShrinkShlLogicImm()
667   case ISD::XOR: BinOpc = RISCV::XORI; break;  in tryShrinkShlLogicImm()
670   unsigned ShOpc = SignExt ? RISCV::SLLIW : RISCV::SLLI;  in tryShrinkShlLogicImm()
697     return CurDAG->getMachineNode(RISCV::TH_EXT, DL, VT, N0.getOperand(0),  in trySignedBitfieldExtract()
784     Opcode = IsZExt ? RISCV::TH_LBUIB : RISCV::TH_LBIB;  in tryIndexedLoad()
786     Opcode = IsZExt ? RISCV::TH_LBUIA : RISCV::TH_LBIA;  in tryIndexedLoad()
788     Opcode = IsZExt ? RISCV::TH_LHUIB : RISCV::TH_LHIB;  in tryIndexedLoad()
790     Opcode = IsZExt ? RISCV::TH_LHUIA : RISCV::TH_LHIA;  in tryIndexedLoad()
792     Opcode = IsZExt ? RISCV::TH_LWUIB : RISCV::TH_LWIB;  in tryIndexedLoad()
794     Opcode = IsZExt ? RISCV::TH_LWUIA : RISCV::TH_LWIA;  in tryIndexedLoad()
796     Opcode = RISCV::TH_LDIB;  in tryIndexedLoad()
798     Opcode = RISCV::TH_LDIA;  in tryIndexedLoad()
844     Opcode = IntNo == Intrinsic::riscv_sf_vc_x_se ? RISCV::PseudoVC_X_SE_MF8  in selectSF_VC_X_SE()
845                                                   : RISCV::PseudoVC_I_SE_MF8;  in selectSF_VC_X_SE()
848     Opcode = IntNo == Intrinsic::riscv_sf_vc_x_se ? RISCV::PseudoVC_X_SE_MF4  in selectSF_VC_X_SE()
849                                                   : RISCV::PseudoVC_I_SE_MF4;  in selectSF_VC_X_SE()
852     Opcode = IntNo == Intrinsic::riscv_sf_vc_x_se ? RISCV::PseudoVC_X_SE_MF2  in selectSF_VC_X_SE()
853                                                   : RISCV::PseudoVC_I_SE_MF2;  in selectSF_VC_X_SE()
856     Opcode = IntNo == Intrinsic::riscv_sf_vc_x_se ? RISCV::PseudoVC_X_SE_M1  in selectSF_VC_X_SE()
857                                                   : RISCV::PseudoVC_I_SE_M1;  in selectSF_VC_X_SE()
860     Opcode = IntNo == Intrinsic::riscv_sf_vc_x_se ? RISCV::PseudoVC_X_SE_M2  in selectSF_VC_X_SE()
861                                                   : RISCV::PseudoVC_I_SE_M2;  in selectSF_VC_X_SE()
864     Opcode = IntNo == Intrinsic::riscv_sf_vc_x_se ? RISCV::PseudoVC_X_SE_M4  in selectSF_VC_X_SE()
865                                                   : RISCV::PseudoVC_I_SE_M4;  in selectSF_VC_X_SE()
868     Opcode = IntNo == Intrinsic::riscv_sf_vc_x_se ? RISCV::PseudoVC_X_SE_M8  in selectSF_VC_X_SE()
869                                                   : RISCV::PseudoVC_I_SE_M8;  in selectSF_VC_X_SE()
900           CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL, RISCV::X0, VT);  in Select()
935         Opc = RISCV::FLI_H;  in Select()
936         FNegOpc = RISCV::FSGNJN_H;  in Select()
939         Opc = RISCV::FLI_S;  in Select()
940         FNegOpc = RISCV::FSGNJN_S;  in Select()
943         Opc = RISCV::FLI_D;  in Select()
944         FNegOpc = RISCV::FSGNJN_D;  in Select()
962       Imm = CurDAG->getRegister(RISCV::X0, XLenVT);  in Select()
975       Opc = RISCV::FMV_H_X;  in Select()
978       Opc = Subtarget->hasStdExtZhinxmin() ? RISCV::COPY : RISCV::FMV_H_X;  in Select()
981       Opc = Subtarget->hasStdExtZfinx() ? RISCV::COPY : RISCV::FMV_W_X;  in Select()
988         Opc = HasZdinx ? RISCV::COPY : RISCV::FMV_D_X;  in Select()
990         Opc = HasZdinx ? RISCV::FCVT_D_W_IN32X : RISCV::FCVT_D_W;  in Select()
995     if (Opc == RISCV::FCVT_D_W_IN32X || Opc == RISCV::FCVT_D_W)  in Select()
1004       Opc = RISCV::FSGNJN_D;  in Select()
1006         Opc = Is64Bit ? RISCV::FSGNJN_D_INX : RISCV::FSGNJN_D_IN32X;  in Select()
1021         CurDAG->getTargetConstant(RISCV::GPRPairRegClassID, DL, MVT::i32),  in Select()
1023         CurDAG->getTargetConstant(RISCV::sub_gpr_even, DL, MVT::i32),  in Select()
1025         CurDAG->getTargetConstant(RISCV::sub_gpr_odd, DL, MVT::i32)};  in Select()
1037         SDValue Lo = CurDAG->getTargetExtractSubreg(RISCV::sub_gpr_even, DL, VT,  in Select()
1043         SDValue Hi = CurDAG->getTargetExtractSubreg(RISCV::sub_gpr_odd, DL, VT,  in Select()
1059       SDNode *Lo = CurDAG->getMachineNode(RISCV::FMV_X_W_FPR64, DL, VT,  in Select()
1064       SDNode *Hi = CurDAG->getMachineNode(RISCV::FMVH_X_D, DL, VT,  in Select()
1091             RISCV::SRLIW, DL, VT, N0->getOperand(0),  in Select()
1094             RISCV::SLLI, DL, VT, SDValue(SRLIW, 0),  in Select()
1120             RISCV::SRLIW, DL, VT, N0->getOperand(0),  in Select()
1123             RISCV::SLLI, DL, VT, SDValue(SRLIW, 0),  in Select()
1146           Subtarget->is64Bit() ? RISCV::SRLIW : RISCV::SRLI, DL, VT,  in Select()
1159           Subtarget->hasStdExtZbs() ? RISCV::BEXTI : RISCV::TH_TST, DL, VT,  in Select()
1167         CurDAG->getMachineNode(RISCV::SLLI, DL, VT, N0->getOperand(0),  in Select()
1170         RISCV::SRLI, DL, VT, SDValue(SLLI, 0),  in Select()
1201         CurDAG->getMachineNode(RISCV::SLLI, DL, VT, N0->getOperand(0),  in Select()
1204         RISCV::SRAI, DL, VT, SDValue(SLLI, 0),  in Select()
1232           RISCV::TH_EXTU, DL, VT, X, CurDAG->getTargetConstant(Msb, DL, VT),  in Select()
1275                 RISCV::SRLIW, DL, VT, X, CurDAG->getTargetConstant(C2, DL, VT));  in Select()
1289                 CurDAG->getMachineNode(RISCV::SRAIW, DL, VT, X.getOperand(0),  in Select()
1292                 RISCV::SRLIW, DL, VT, SDValue(SRAIW, 0),  in Select()
1319                 RISCV::SLLI, DL, VT, X,  in Select()
1322                 RISCV::SRLI, DL, VT, SDValue(SLLI, 0),  in Select()
1340                 CurDAG->getMachineNode(RISCV::SLLI_UW, DL, VT, X,  in Select()
1349                 RISCV::SLLI, DL, VT, X,  in Select()
1352                 RISCV::SRLI, DL, VT, SDValue(SLLI, 0),  in Select()
1367           unsigned SrliOpc = RISCV::SRLI;  in Select()
1372             SrliOpc = RISCV::SRLIW;  in Select()
1379               RISCV::SLLI, DL, VT, SDValue(SRLI, 0),  in Select()
1388               RISCV::SRLIW, DL, VT, X,  in Select()
1391               RISCV::SLLI, DL, VT, SDValue(SRLIW, 0),  in Select()
1405               RISCV::SRLI, DL, VT, X,  in Select()
1408               RISCV::SLLI, DL, VT, SDValue(SRLI, 0),  in Select()
1416               RISCV::SRLIW, DL, VT, X,  in Select()
1419               RISCV::SLLI, DL, VT, SDValue(SRLIW, 0),  in Select()
1429               RISCV::SRLI, DL, VT, X,  in Select()
1432               RISCV::SLLI_UW, DL, VT, SDValue(SRLI, 0),  in Select()
1520         CurDAG->getMachineNode(RISCV::SLLI, DL, VT, N0.getOperand(0),  in Select()
1522     SDNode *MULHU = CurDAG->getMachineNode(RISCV::MULHU, DL, VT,  in Select()
1556           Opcode = RISCV::CV_LB_ri_inc;  in Select()
1558           Opcode = RISCV::CV_LBU_ri_inc;  in Select()
1560           Opcode = RISCV::CV_LB_rr_inc;  in Select()
1562           Opcode = RISCV::CV_LBU_rr_inc;  in Select()
1566           Opcode = RISCV::CV_LH_ri_inc;  in Select()
1568           Opcode = RISCV::CV_LHU_ri_inc;  in Select()
1570           Opcode = RISCV::CV_LH_rr_inc;  in Select()
1572           Opcode = RISCV::CV_LHU_rr_inc;  in Select()
1576           Opcode = RISCV::CV_LW_ri_inc;  in Select()
1578           Opcode = RISCV::CV_LW_rr_inc;  in Select()
1624     VMSLTOpcode = IsUnsigned ? RISCV::PseudoVMSLTU_VX_##suffix                 \  in Select()
1625                              : RISCV::PseudoVMSLT_VX_##suffix;                 \  in Select()
1626     VMNANDOpcode = RISCV::PseudoVMNAND_MM_##suffix;                            \  in Select()
1627     VMSetOpcode = RISCV::PseudoVMSET_M_##suffix_b;                             \  in Select()
1684     VMSLTOpcode = IsUnsigned ? RISCV::PseudoVMSLTU_VX_##suffix                 \  in Select()
1685                              : RISCV::PseudoVMSLT_VX_##suffix;                 \  in Select()
1686     VMSLTMaskOpcode = IsUnsigned ? RISCV::PseudoVMSLTU_VX_##suffix##_MASK      \  in Select()
1687                                  : RISCV::PseudoVMSLT_VX_##suffix##_MASK;      \  in Select()
1704     VMXOROpcode = RISCV::PseudoVMXOR_MM_##suffix;                              \  in Select()
1705     VMANDNOpcode = RISCV::PseudoVMANDN_MM_##suffix;                            \  in Select()
1706     VMOROpcode = RISCV::PseudoVMOR_MM_##suffix;                                \  in Select()
1753                                            RISCV::V0, Mask, SDValue());  in Select()
1755       SDValue V0 = CurDAG->getRegister(RISCV::V0, VT);  in Select()
1910       const RISCV::VLX_VSXPseudo *P = RISCV::getVLXPseudo(  in Select()
1957       const RISCV::VLEPseudo *P =  in Select()
1958           RISCV::getVLEPseudo(IsMasked, IsStrided, /*FF*/ false, Log2SEW,  in Select()
1984       const RISCV::VLEPseudo *P =  in Select()
1985           RISCV::getVLEPseudo(IsMasked, /*Strided*/ false, /*FF*/ true,  in Select()
2108       const RISCV::VLX_VSXPseudo *P = RISCV::getVSXPseudo(  in Select()
2141       const RISCV::VSEPseudo *P = RISCV::getVSEPseudo(  in Select()
2182       TypeSize VecRegSize = TypeSize::getScalable(RISCV::RVVBitsPerBlock);  in Select()
2217     if (SubRegIdx == RISCV::NoSubRegister) {  in Select()
2264     if (SubRegIdx == RISCV::NoSubRegister) {  in Select()
2328       Operands.push_back(CurDAG->getRegister(RISCV::X0, XLenVT));  in Select()
2334     const RISCV::VLEPseudo *P = RISCV::getVLEPseudo(  in Select()
2467           CurDAG->getMachineNode(RISCV::LUI, DL, VT,  in selectConstantAddr()
2471       Base = CurDAG->getRegister(RISCV::X0, VT);  in selectConstantAddr()
2482   if (Seq.back().getOpcode() != RISCV::ADDI)  in selectConstantAddr()
2553         Base = SDValue(CurDAG->getMachineNode(RISCV::ADDI, SDLoc(Addr), VT,  in SelectAddrRegRegScale()
2568     Base = CurDAG->getRegister(RISCV::X0, VT);  in SelectAddrRegRegScale()
2635           CurDAG->getMachineNode(RISCV::ADDI, DL, VT, Addr.getOperand(0),  in SelectAddrRegImm()
2653           CurDAG->getMachineNode(RISCV::ADD, DL, VT, Addr.getOperand(0), Base),  in SelectAddrRegImm()
2708                          RISCV::ADDI, DL, VT, Addr.getOperand(0),  in SelectAddrRegImmLsb00000()
2719           CurDAG->getMachineNode(RISCV::ADD, DL, VT, Addr.getOperand(0), Base),  in SelectAddrRegImmLsb00000()
2795       SDValue Zero = CurDAG->getRegister(RISCV::X0, VT);  in selectShiftMask()
2796       unsigned NegOpc = VT == MVT::i64 ? RISCV::SUBW : RISCV::SUB;  in selectShiftMask()
2808           CurDAG->getMachineNode(RISCV::XORI, DL, VT, ShAmt.getOperand(1),  in selectShiftMask()
2858                       RISCV::XORI, DL, N->getValueType(0), LHS,  in selectSETCC()
2868                       RISCV::ADDI, DL, N->getValueType(0), LHS,  in selectSETCC()
2878       CurDAG->getMachineNode(RISCV::XOR, DL, N->getValueType(0), LHS, RHS), 0);  in selectSETCC()
2959                             RISCV::SRLI, DL, VT, N0.getOperand(0),  in selectSHXADDOp()
2972                   RISCV::SRLI, DL, VT, N0.getOperand(0),  in selectSHXADDOp()
3000                             RISCV::SRLIW, DL, VT, N0.getOperand(0),  in selectSHXADDOp()
3012                             RISCV::SRLIW, DL, VT, N0.getOperand(0),  in selectSHXADDOp()
3049                             RISCV::SLLI, DL, VT, N0.getOperand(0),  in selectSHXADD_UWOp()
3064   unsigned MCOpcode = RISCV::getRVVMCOpcode(User->getMachineOpcode());  in vectorPseudoHasAllNBitUsers()
3087       RISCV::getVectorLowDemandedScalarBits(MCOpcode, Log2SEW);  in vectorPseudoHasAllNBitUsers()
3130     case RISCV::ADDW:  in hasAllNBitUsers()
3131     case RISCV::ADDIW:  in hasAllNBitUsers()
3132     case RISCV::SUBW:  in hasAllNBitUsers()
3133     case RISCV::MULW:  in hasAllNBitUsers()
3134     case RISCV::SLLW:  in hasAllNBitUsers()
3135     case RISCV::SLLIW:  in hasAllNBitUsers()
3136     case RISCV::SRAW:  in hasAllNBitUsers()
3137     case RISCV::SRAIW:  in hasAllNBitUsers()
3138     case RISCV::SRLW:  in hasAllNBitUsers()
3139     case RISCV::SRLIW:  in hasAllNBitUsers()
3140     case RISCV::DIVW:  in hasAllNBitUsers()
3141     case RISCV::DIVUW:  in hasAllNBitUsers()
3142     case RISCV::REMW:  in hasAllNBitUsers()
3143     case RISCV::REMUW:  in hasAllNBitUsers()
3144     case RISCV::ROLW:  in hasAllNBitUsers()
3145     case RISCV::RORW:  in hasAllNBitUsers()
3146     case RISCV::RORIW:  in hasAllNBitUsers()
3147     case RISCV::CLZW:  in hasAllNBitUsers()
3148     case RISCV::CTZW:  in hasAllNBitUsers()
3149     case RISCV::CPOPW:  in hasAllNBitUsers()
3150     case RISCV::SLLI_UW:  in hasAllNBitUsers()
3151     case RISCV::FMV_W_X:  in hasAllNBitUsers()
3152     case RISCV::FCVT_H_W:  in hasAllNBitUsers()
3153     case RISCV::FCVT_H_WU:  in hasAllNBitUsers()
3154     case RISCV::FCVT_S_W:  in hasAllNBitUsers()
3155     case RISCV::FCVT_S_WU:  in hasAllNBitUsers()
3156     case RISCV::FCVT_D_W:  in hasAllNBitUsers()
3157     case RISCV::FCVT_D_WU:  in hasAllNBitUsers()
3158     case RISCV::TH_REVW:  in hasAllNBitUsers()
3159     case RISCV::TH_SRRIW:  in hasAllNBitUsers()
3163     case RISCV::SLL:  in hasAllNBitUsers()
3164     case RISCV::SRA:  in hasAllNBitUsers()
3165     case RISCV::SRL:  in hasAllNBitUsers()
3166     case RISCV::ROL:  in hasAllNBitUsers()
3167     case RISCV::ROR:  in hasAllNBitUsers()
3168     case RISCV::BSET:  in hasAllNBitUsers()
3169     case RISCV::BCLR:  in hasAllNBitUsers()
3170     case RISCV::BINV:  in hasAllNBitUsers()
3175     case RISCV::SLLI:  in hasAllNBitUsers()
3180     case RISCV::ANDI:  in hasAllNBitUsers()
3184     case RISCV::ORI: {  in hasAllNBitUsers()
3190     case RISCV::AND:  in hasAllNBitUsers()
3191     case RISCV::OR:  in hasAllNBitUsers()
3192     case RISCV::XOR:  in hasAllNBitUsers()
3193     case RISCV::XORI:  in hasAllNBitUsers()
3194     case RISCV::ANDN:  in hasAllNBitUsers()
3195     case RISCV::ORN:  in hasAllNBitUsers()
3196     case RISCV::XNOR:  in hasAllNBitUsers()
3197     case RISCV::SH1ADD:  in hasAllNBitUsers()
3198     case RISCV::SH2ADD:  in hasAllNBitUsers()
3199     case RISCV::SH3ADD:  in hasAllNBitUsers()
3204     case RISCV::SRLI: {  in hasAllNBitUsers()
3213     case RISCV::SEXT_B:  in hasAllNBitUsers()
3214     case RISCV::PACKH:  in hasAllNBitUsers()
3218     case RISCV::SEXT_H:  in hasAllNBitUsers()
3219     case RISCV::FMV_H_X:  in hasAllNBitUsers()
3220     case RISCV::ZEXT_H_RV32:  in hasAllNBitUsers()
3221     case RISCV::ZEXT_H_RV64:  in hasAllNBitUsers()
3222     case RISCV::PACKW:  in hasAllNBitUsers()
3226     case RISCV::PACK:  in hasAllNBitUsers()
3230     case RISCV::ADD_UW:  in hasAllNBitUsers()
3231     case RISCV::SH1ADD_UW:  in hasAllNBitUsers()
3232     case RISCV::SH2ADD_UW:  in hasAllNBitUsers()
3233     case RISCV::SH3ADD_UW:  in hasAllNBitUsers()
3239     case RISCV::SB:  in hasAllNBitUsers()
3243     case RISCV::SH:  in hasAllNBitUsers()
3247     case RISCV::SW:  in hasAllNBitUsers()
3289     VL = CurDAG->getTargetConstant(RISCV::VLMaxSentinel, SDLoc(N),  in selectVLOp()
3292              cast<RegisterSDNode>(N)->getReg() == RISCV::X0) {  in selectVLOp()
3297     VL = CurDAG->getTargetConstant(RISCV::VLMaxSentinel, SDLoc(N),  in selectVLOp()
3461   if (N->getMachineOpcode() != RISCV::ADDIW ||  in doPeepholeSExtW()
3472   case RISCV::ADD:  in doPeepholeSExtW()
3473   case RISCV::ADDI:  in doPeepholeSExtW()
3474   case RISCV::SUB:  in doPeepholeSExtW()
3475   case RISCV::MUL:  in doPeepholeSExtW()
3476   case RISCV::SLLI: {  in doPeepholeSExtW()
3483     case RISCV::ADD:  Opc = RISCV::ADDW;  break;  in doPeepholeSExtW()
3484     case RISCV::ADDI: Opc = RISCV::ADDIW; break;  in doPeepholeSExtW()
3485     case RISCV::SUB:  Opc = RISCV::SUBW;  break;  in doPeepholeSExtW()
3486     case RISCV::MUL:  Opc = RISCV::MULW;  break;  in doPeepholeSExtW()
3487     case RISCV::SLLI: Opc = RISCV::SLLIW; break;  in doPeepholeSExtW()
3494     if (N0.getMachineOpcode() == RISCV::SLLI &&  in doPeepholeSExtW()
3504   case RISCV::ADDW:  in doPeepholeSExtW()
3505   case RISCV::ADDIW:  in doPeepholeSExtW()
3506   case RISCV::SUBW:  in doPeepholeSExtW()
3507   case RISCV::MULW:  in doPeepholeSExtW()
3508   case RISCV::SLLIW:  in doPeepholeSExtW()
3509   case RISCV::PACKW:  in doPeepholeSExtW()
3510   case RISCV::TH_MULAW:  in doPeepholeSExtW()
3511   case RISCV::TH_MULAH:  in doPeepholeSExtW()
3512   case RISCV::TH_MULSW:  in doPeepholeSExtW()
3513   case RISCV::TH_MULSH:  in doPeepholeSExtW()
3532       cast<RegisterSDNode>(MaskOp)->getReg() != RISCV::V0)  in getMaskSetter()
3543       cast<RegisterSDNode>(Glued->getOperand(1))->getReg() != RISCV::V0)  in getMaskSetter()
3551       MaskSetter->getMachineOpcode() == RISCV::COPY_TO_REGCLASS)  in getMaskSetter()
3564     return Opc == RISCV::PseudoVMSET_M_B1 || Opc == RISCV::PseudoVMSET_M_B16 ||  in usesAllOnesMask()
3565            Opc == RISCV::PseudoVMSET_M_B2 || Opc == RISCV::PseudoVMSET_M_B32 ||  in usesAllOnesMask()
3566            Opc == RISCV::PseudoVMSET_M_B4 || Opc == RISCV::PseudoVMSET_M_B64 ||  in usesAllOnesMask()
3567            Opc == RISCV::PseudoVMSET_M_B8;  in usesAllOnesMask()
3600   const RISCV::RISCVMaskedPseudoInfo *I =  in doPeepholeMaskedRVV()
3601       RISCV::getMaskedPseudoInfo(N->getMachineOpcode());  in doPeepholeMaskedRVV()
3651   return RISCV::getRVVMCOpcode(N->getMachineOpcode()) == RISCV::VMERGE_VVM;  in IsVMerge()
3655   return RISCV::getRVVMCOpcode(N->getMachineOpcode()) == RISCV::VMV_V_V;  in IsVMv()
3661     return RISCV::PseudoVMSET_M_B1;  in GetVMSetForLMul()
3663     return RISCV::PseudoVMSET_M_B2;  in GetVMSetForLMul()
3665     return RISCV::PseudoVMSET_M_B4;  in GetVMSetForLMul()
3667     return RISCV::PseudoVMSET_M_B8;  in GetVMSetForLMul()
3669     return RISCV::PseudoVMSET_M_B16;  in GetVMSetForLMul()
3671     return RISCV::PseudoVMSET_M_B32;  in GetVMSetForLMul()
3673     return RISCV::PseudoVMSET_M_B64;  in GetVMSetForLMul()
3721   assert(!Mask || cast<RegisterSDNode>(Mask)->getReg() == RISCV::V0);  in performCombineVMergeAndVOps()
3749   const RISCV::RISCVMaskedPseudoInfo *Info =  in performCombineVMergeAndVOps()
3750       RISCV::lookupMaskedIntrinsicByUnmasked(TrueOpc);  in performCombineVMergeAndVOps()
3752     Info = RISCV::getMaskedPseudoInfo(TrueOpc);  in performCombineVMergeAndVOps()
3875                                             RISCV::V0, AllOnesMask, SDValue());  in performCombineVMergeAndVOps()
3876     Mask = CurDAG->getRegister(RISCV::V0, MaskVT);  in performCombineVMergeAndVOps()
3984     Ops.push_back(CurDAG->getRegister(RISCV::NoRegister, N->getValueType(0)));  in doPeepholeNoRegPassThru()