Lines Matching refs:RISCV
56 extern const SubtargetFeatureKV RISCVFeatureKV[RISCV::NumSubtargetFeatures];
85 bool isRV64() const { return getSTI().hasFeature(RISCV::Feature64Bit); } in isRV64()
86 bool isRVE() const { return getSTI().hasFeature(RISCV::FeatureStdExtE); } in isRVE()
88 return getSTI().hasFeature(RISCV::Experimental); in enableExperimentalExtension()
305 if (ABIName.ends_with("f") && !getSTI().hasFeature(RISCV::FeatureStdExtF)) { in RISCVAsmParser()
310 !getSTI().hasFeature(RISCV::FeatureStdExtD)) { in RISCVAsmParser()
456 return Kind == KindTy::Register && Reg.RegNum == RISCV::V0; in isV0Reg()
460 (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg.RegNum) || in isAnyReg()
461 RISCVMCRegisterClasses[RISCV::FPR64RegClassID].contains(Reg.RegNum) || in isAnyReg()
462 RISCVMCRegisterClasses[RISCV::VRRegClassID].contains(Reg.RegNum)); in isAnyReg()
466 (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains( in isAnyRegC()
468 RISCVMCRegisterClasses[RISCV::FPR64CRegClassID].contains( in isAnyRegC()
480 RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg.RegNum); in isGPR()
487 RISCVMCRegisterClasses[RISCV::GPRPairRegClassID].contains( in isGPRPair()
1294 assert(Reg >= RISCV::F0_D && Reg <= RISCV::F31_D && "Invalid register"); in convertFPR64ToFPR16()
1295 return Reg - RISCV::F0_D + RISCV::F0_H; in convertFPR64ToFPR16()
1299 assert(Reg >= RISCV::F0_D && Reg <= RISCV::F31_D && "Invalid register"); in convertFPR64ToFPR32()
1300 return Reg - RISCV::F0_D + RISCV::F0_F; in convertFPR64ToFPR32()
1307 RegClassID = RISCV::VRM2RegClassID; in convertVRToVRMx()
1309 RegClassID = RISCV::VRM4RegClassID; in convertVRToVRMx()
1311 RegClassID = RISCV::VRM8RegClassID; in convertVRToVRMx()
1314 return RI.getMatchingSuperReg(Reg, RISCV::sub_vrm1_0, in convertVRToVRMx()
1326 RISCVMCRegisterClasses[RISCV::FPR64RegClassID].contains(Reg); in validateTargetOperandClass()
1328 RISCVMCRegisterClasses[RISCV::FPR64CRegClassID].contains(Reg); in validateTargetOperandClass()
1329 bool IsRegVR = RISCVMCRegisterClasses[RISCV::VRRegClassID].contains(Reg); in validateTargetOperandClass()
1359 if (MCID.operands()[I].RegClass == RISCV::GPRPairRegClassID) { in checkTargetMatchPredicate()
1364 if (RISCVMCRegisterClasses[RISCV::GPRPairRegClassID].contains(Reg)) in checkTargetMatchPredicate()
1368 if (((Reg.id() - RISCV::X0) & 1) != 0) in checkTargetMatchPredicate()
1675 assert(!(Reg >= RISCV::F0_H && Reg <= RISCV::F31_H)); in matchRegisterNameHelper()
1676 assert(!(Reg >= RISCV::F0_F && Reg <= RISCV::F31_F)); in matchRegisterNameHelper()
1678 static_assert(RISCV::F0_D < RISCV::F0_H, "FPR matching must be updated"); in matchRegisterNameHelper()
1679 static_assert(RISCV::F0_D < RISCV::F0_F, "FPR matching must be updated"); in matchRegisterNameHelper()
1682 if (isRVE() && Reg >= RISCV::X16 && Reg <= RISCV::X31) in matchRegisterNameHelper()
1683 Reg = RISCV::NoRegister; in matchRegisterNameHelper()
2197 unsigned ELEN = STI->hasFeature(RISCV::FeatureStdExtZve64x) ? 64 : 32; in parseVTypeToken()
2263 unsigned ELEN = STI->hasFeature(RISCV::FeatureStdExtZve64x) ? 64 : 32; in parseVTypeI()
2300 if (RegNo != RISCV::V0) in parseMaskReg()
2322 RegNo, S, E, !getSTI().hasFeature(RISCV::FeatureStdExtF))); in parseGPRAsFPR()
2350 if (!RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(RegNo)) in parseGPRPair()
2353 if ((RegNo - RISCV::X0) & 1) in parseGPRPair()
2362 RegNo, RISCV::sub_gpr_even, in parseGPRPair()
2363 &RISCVMCRegisterClasses[RISCV::GPRPairRegClassID]); in parseGPRPair()
2566 if (RegStart != RISCV::X1) in parseReglist()
2578 if (RegStart != RISCV::X8) in parseReglist()
2591 if (IsEABI && RegEnd != RISCV::X9) in parseReglist()
2600 if (RegEnd != RISCV::X9) in parseReglist()
2609 if (MatchRegisterName(EndName) != RISCV::X18) in parseReglist()
2620 if (MatchRegisterName(EndName) == RISCV::NoRegister) in parseReglist()
2628 if (RegEnd == RISCV::X26) in parseReglist()
2635 if (RegEnd == RISCV::NoRegister) in parseReglist()
2702 if (getSTI().hasFeature(RISCV::FeatureRelax)) { in ParseInstruction()
2812 clearFeatureBits(RISCV::Feature64Bit, "64bit"); in resetToArch()
2814 setFeatureBits(RISCV::Feature64Bit, "64bit"); in resetToArch()
2949 setFeatureBits(RISCV::FeatureStdExtC, "c"); in parseDirectiveOption()
2958 clearFeatureBits(RISCV::FeatureStdExtC, "c"); in parseDirectiveOption()
2959 clearFeatureBits(RISCV::FeatureStdExtZca, "zca"); in parseDirectiveOption()
2986 setFeatureBits(RISCV::FeatureRelax, "relax"); in parseDirectiveOption()
2995 clearFeatureBits(RISCV::FeatureRelax, "relax"); in parseDirectiveOption()
3100 bool AllowC = getSTI().hasFeature(RISCV::FeatureStdExtC) || in parseDirectiveInsn()
3101 getSTI().hasFeature(RISCV::FeatureStdExtZca); in parseDirectiveInsn()
3133 emitToStreamer(getStreamer(), MCInstBuilder(RealLength == 2 ? RISCV::Insn16 in parseDirectiveInsn()
3134 : RISCV::Insn32) in parseDirectiveInsn()
3203 Out, MCInstBuilder(RISCV::AUIPC).addOperand(TmpReg).addExpr(SymbolHi)); in emitAuipcInstPair()
3226 RISCV::ADDI, IDLoc, Out); in emitLoadLocalAddress()
3239 unsigned SecondOpcode = isRV64() ? RISCV::LD : RISCV::LW; in emitLoadGlobalAddress()
3269 unsigned SecondOpcode = isRV64() ? RISCV::LD : RISCV::LW; in emitLoadTLSIEAddress()
3285 RISCV::ADDI, IDLoc, Out); in emitLoadTLSGDAddress()
3320 unsigned SecondOpcode = SignExtend ? RISCV::SRAI : RISCV::SRLI; in emitPseudoExtend()
3325 emitToStreamer(Out, MCInstBuilder(RISCV::SLLI) in emitPseudoExtend()
3347 .addReg(RISCV::NoRegister) in emitVMSGE()
3349 emitToStreamer(Out, MCInstBuilder(RISCV::VMNAND_MM) in emitVMSGE()
3359 assert(Inst.getOperand(0).getReg() != RISCV::V0 && in emitVMSGE()
3367 emitToStreamer(Out, MCInstBuilder(RISCV::VMXOR_MM) in emitVMSGE()
3370 .addReg(RISCV::V0) in emitVMSGE()
3373 Inst.getOperand(0).getReg() == RISCV::V0) { in emitVMSGE()
3378 assert(Inst.getOperand(0).getReg() == RISCV::V0 && in emitVMSGE()
3380 assert(Inst.getOperand(1).getReg() != RISCV::V0 && in emitVMSGE()
3386 .addReg(RISCV::NoRegister) in emitVMSGE()
3388 emitToStreamer(Out, MCInstBuilder(RISCV::VMANDN_MM) in emitVMSGE()
3399 assert(Inst.getOperand(1).getReg() != RISCV::V0 && in emitVMSGE()
3405 .addReg(RISCV::NoRegister) in emitVMSGE()
3407 emitToStreamer(Out, MCInstBuilder(RISCV::VMANDN_MM) in emitVMSGE()
3409 .addReg(RISCV::V0) in emitVMSGE()
3412 emitToStreamer(Out, MCInstBuilder(RISCV::VMANDN_MM) in emitVMSGE()
3415 .addReg(RISCV::V0) in emitVMSGE()
3417 emitToStreamer(Out, MCInstBuilder(RISCV::VMOR_MM) in emitVMSGE()
3427 assert(Inst.getOpcode() == RISCV::PseudoAddTPRel && "Invalid instruction"); in checkPseudoAddTPRel()
3429 if (Inst.getOperand(2).getReg() != RISCV::X4) { in checkPseudoAddTPRel()
3440 assert(Inst.getOpcode() == RISCV::PseudoTLSDESCCall && "Invalid instruction"); in checkPseudoTLSDESCCall()
3442 if (Inst.getOperand(0).getReg() != RISCV::X5) { in checkPseudoTLSDESCCall()
3452 return RISCVOperand::createReg(RISCV::NoRegister, llvm::SMLoc(), in defaultMaskRegOp()
3470 if (Opcode == RISCV::PseudoVMSGEU_VX_M_T || in validateInstruction()
3471 Opcode == RISCV::PseudoVMSGE_VX_M_T) { in validateInstruction()
3481 if (Opcode == RISCV::TH_LDD || Opcode == RISCV::TH_LWUD || in validateInstruction()
3482 Opcode == RISCV::TH_LWD) { in validateInstruction()
3493 if (Opcode == RISCV::CM_MVSA01) { in validateInstruction()
3502 bool IsTHeadMemPair32 = (Opcode == RISCV::TH_LWD || in validateInstruction()
3503 Opcode == RISCV::TH_LWUD || Opcode == RISCV::TH_SWD); in validateInstruction()
3504 bool IsTHeadMemPair64 = (Opcode == RISCV::TH_LDD || Opcode == RISCV::TH_SDD); in validateInstruction()
3519 if (Opcode == RISCV::VC_V_XVW || Opcode == RISCV::VC_V_IVW || in validateInstruction()
3520 Opcode == RISCV::VC_V_FVW || Opcode == RISCV::VC_V_VVW) { in validateInstruction()
3559 if ((MCID.TSFlags & RISCVII::VMConstraint) && (DestReg == RISCV::V0)) { in validateInstruction()
3562 if (Opcode == RISCV::VADC_VVM || Opcode == RISCV::VADC_VXM || in validateInstruction()
3563 Opcode == RISCV::VADC_VIM || Opcode == RISCV::VSBC_VVM || in validateInstruction()
3564 Opcode == RISCV::VSBC_VXM || Opcode == RISCV::VFMERGE_VFM || in validateInstruction()
3565 Opcode == RISCV::VMERGE_VIM || Opcode == RISCV::VMERGE_VVM || in validateInstruction()
3566 Opcode == RISCV::VMERGE_VXM) in validateInstruction()
3574 assert((CheckReg == RISCV::V0 || CheckReg == RISCV::NoRegister) && in validateInstruction()
3592 case RISCV::PseudoLLAImm: in processInstruction()
3593 case RISCV::PseudoLAImm: in processInstruction()
3594 case RISCV::PseudoLI: { in processInstruction()
3600 emitToStreamer(Out, MCInstBuilder(RISCV::ADDI) in processInstruction()
3602 .addReg(RISCV::X0) in processInstruction()
3615 case RISCV::PseudoLLA: in processInstruction()
3618 case RISCV::PseudoLGA: in processInstruction()
3621 case RISCV::PseudoLA: in processInstruction()
3624 case RISCV::PseudoLA_TLS_IE: in processInstruction()
3627 case RISCV::PseudoLA_TLS_GD: in processInstruction()
3630 case RISCV::PseudoLB: in processInstruction()
3631 emitLoadStoreSymbol(Inst, RISCV::LB, IDLoc, Out, /*HasTmpReg=*/false); in processInstruction()
3633 case RISCV::PseudoLBU: in processInstruction()
3634 emitLoadStoreSymbol(Inst, RISCV::LBU, IDLoc, Out, /*HasTmpReg=*/false); in processInstruction()
3636 case RISCV::PseudoLH: in processInstruction()
3637 emitLoadStoreSymbol(Inst, RISCV::LH, IDLoc, Out, /*HasTmpReg=*/false); in processInstruction()
3639 case RISCV::PseudoLHU: in processInstruction()
3640 emitLoadStoreSymbol(Inst, RISCV::LHU, IDLoc, Out, /*HasTmpReg=*/false); in processInstruction()
3642 case RISCV::PseudoLW: in processInstruction()
3643 emitLoadStoreSymbol(Inst, RISCV::LW, IDLoc, Out, /*HasTmpReg=*/false); in processInstruction()
3645 case RISCV::PseudoLWU: in processInstruction()
3646 emitLoadStoreSymbol(Inst, RISCV::LWU, IDLoc, Out, /*HasTmpReg=*/false); in processInstruction()
3648 case RISCV::PseudoLD: in processInstruction()
3649 emitLoadStoreSymbol(Inst, RISCV::LD, IDLoc, Out, /*HasTmpReg=*/false); in processInstruction()
3651 case RISCV::PseudoFLH: in processInstruction()
3652 emitLoadStoreSymbol(Inst, RISCV::FLH, IDLoc, Out, /*HasTmpReg=*/true); in processInstruction()
3654 case RISCV::PseudoFLW: in processInstruction()
3655 emitLoadStoreSymbol(Inst, RISCV::FLW, IDLoc, Out, /*HasTmpReg=*/true); in processInstruction()
3657 case RISCV::PseudoFLD: in processInstruction()
3658 emitLoadStoreSymbol(Inst, RISCV::FLD, IDLoc, Out, /*HasTmpReg=*/true); in processInstruction()
3660 case RISCV::PseudoSB: in processInstruction()
3661 emitLoadStoreSymbol(Inst, RISCV::SB, IDLoc, Out, /*HasTmpReg=*/true); in processInstruction()
3663 case RISCV::PseudoSH: in processInstruction()
3664 emitLoadStoreSymbol(Inst, RISCV::SH, IDLoc, Out, /*HasTmpReg=*/true); in processInstruction()
3666 case RISCV::PseudoSW: in processInstruction()
3667 emitLoadStoreSymbol(Inst, RISCV::SW, IDLoc, Out, /*HasTmpReg=*/true); in processInstruction()
3669 case RISCV::PseudoSD: in processInstruction()
3670 emitLoadStoreSymbol(Inst, RISCV::SD, IDLoc, Out, /*HasTmpReg=*/true); in processInstruction()
3672 case RISCV::PseudoFSH: in processInstruction()
3673 emitLoadStoreSymbol(Inst, RISCV::FSH, IDLoc, Out, /*HasTmpReg=*/true); in processInstruction()
3675 case RISCV::PseudoFSW: in processInstruction()
3676 emitLoadStoreSymbol(Inst, RISCV::FSW, IDLoc, Out, /*HasTmpReg=*/true); in processInstruction()
3678 case RISCV::PseudoFSD: in processInstruction()
3679 emitLoadStoreSymbol(Inst, RISCV::FSD, IDLoc, Out, /*HasTmpReg=*/true); in processInstruction()
3681 case RISCV::PseudoAddTPRel: in processInstruction()
3685 case RISCV::PseudoTLSDESCCall: in processInstruction()
3689 case RISCV::PseudoSEXT_B: in processInstruction()
3692 case RISCV::PseudoSEXT_H: in processInstruction()
3695 case RISCV::PseudoZEXT_H: in processInstruction()
3698 case RISCV::PseudoZEXT_W: in processInstruction()
3701 case RISCV::PseudoVMSGEU_VX: in processInstruction()
3702 case RISCV::PseudoVMSGEU_VX_M: in processInstruction()
3703 case RISCV::PseudoVMSGEU_VX_M_T: in processInstruction()
3704 emitVMSGE(Inst, RISCV::VMSLTU_VX, IDLoc, Out); in processInstruction()
3706 case RISCV::PseudoVMSGE_VX: in processInstruction()
3707 case RISCV::PseudoVMSGE_VX_M: in processInstruction()
3708 case RISCV::PseudoVMSGE_VX_M_T: in processInstruction()
3709 emitVMSGE(Inst, RISCV::VMSLT_VX, IDLoc, Out); in processInstruction()
3711 case RISCV::PseudoVMSGE_VI: in processInstruction()
3712 case RISCV::PseudoVMSLT_VI: { in processInstruction()
3716 unsigned Opc = Inst.getOpcode() == RISCV::PseudoVMSGE_VI ? RISCV::VMSGT_VI in processInstruction()
3717 : RISCV::VMSLE_VI; in processInstruction()
3726 case RISCV::PseudoVMSGEU_VI: in processInstruction()
3727 case RISCV::PseudoVMSLTU_VI: { in processInstruction()
3734 unsigned Opc = Inst.getOpcode() == RISCV::PseudoVMSGEU_VI in processInstruction()
3735 ? RISCV::VMSEQ_VV in processInstruction()
3736 : RISCV::VMSNE_VV; in processInstruction()
3745 unsigned Opc = Inst.getOpcode() == RISCV::PseudoVMSGEU_VI in processInstruction()
3746 ? RISCV::VMSGTU_VI in processInstruction()
3747 : RISCV::VMSLEU_VI; in processInstruction()