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/freebsd/contrib/llvm-project/llvm/include/llvm/TargetParser/
H A DARMTargetParser.def1 //===- ARMTargetParser.def - ARM target parsing defines ---------*- C++ -*-===//
9 // This file provides defines to build up the ARM target parser's logic.
74 ARM::AEK_NONE)
76 ARM::AEK_NONE)
78 ARM::AEK_NONE)
80 ARM::AEK_NONE)
82 FK_NONE, ARM::AEK_DSP)
84 FK_NONE, ARM::AEK_DSP)
86 ARM::AEK_DSP)
88 ARM::AEK_DSP)
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMExpandPseudoInsts.cpp170 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true},
171 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true},
172 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true},
173 { ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, true, EvenDblSpc, 1, 2 ,true},
174 { ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, false, EvenDblSpc, 1, 8 ,true},
175 { ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, true, true, EvenDblSpc, 1, 8 ,true},
177 { ARM::VLD1d16QPseudo, ARM::VLD1d16Q, true, false, false, SingleSpc, 4, 4 ,false},
178 { ARM::VLD1d16QPseudoWB_fixed, ARM::VLD1d16Qwb_fixed, true, true, false, SingleSpc, 4, 4 ,false…
179 { ARM::VLD1d16QPseudoWB_register, ARM::VLD1d16Qwb_register, true, true, true, SingleSpc, 4, 4 ,fa…
180 { ARM::VLD1d16TPseudo, ARM::VLD1d16T, true, false, false, SingleSpc, 3, 4 ,false},
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H A DARMFeatures.h28 case ARM::tADC: in isV8EligibleForIT()
29 case ARM::tADDi3: in isV8EligibleForIT()
30 case ARM::tADDi8: in isV8EligibleForIT()
31 case ARM::tADDrr: in isV8EligibleForIT()
32 case ARM::tAND: in isV8EligibleForIT()
33 case ARM::tASRri: in isV8EligibleForIT()
34 case ARM::tASRrr: in isV8EligibleForIT()
35 case ARM::tBIC: in isV8EligibleForIT()
36 case ARM::tEOR: in isV8EligibleForIT()
37 case ARM::tLSLri: in isV8EligibleForIT()
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H A DARMRegisterBankInfo.cpp30 namespace ARM { namespace
142 const RegisterBank &RBGPR = getRegBank(ARM::GPRRegBankID); in ARMRegisterBankInfo()
144 assert(&ARM::GPRRegBank == &RBGPR && "The order in RegBanks is messed up"); in ARMRegisterBankInfo()
147 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRRegClassID)) && in ARMRegisterBankInfo()
149 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRwithAPSRRegClassID)) && in ARMRegisterBankInfo()
151 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnopcRegClassID)) && in ARMRegisterBankInfo()
153 assert(RBGPR.covers(*TRI.getRegClass(ARM::rGPRRegClassID)) && in ARMRegisterBankInfo()
155 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPRRegClassID)) && in ARMRegisterBankInfo()
157 assert(RBGPR.covers(*TRI.getRegClass(ARM::tcGPRRegClassID)) && in ARMRegisterBankInfo()
159 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPROdd_and_tcGPRRegClassID)) && in ARMRegisterBankInfo()
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H A DARMFixCortexA57AES1742098Pass.cpp123 return Opc == ARM::AESD || Opc == ARM::AESE; in isFirstAESPairInstr()
139 case ARM::AESD: in isSafeAESInput()
140 case ARM::AESE: in isSafeAESInput()
141 case ARM::AESMC: in isSafeAESInput()
142 case ARM::AESIMC: in isSafeAESInput()
146 case ARM::VANDd: in isSafeAESInput()
147 case ARM::VANDq: in isSafeAESInput()
148 case ARM::VORRd: in isSafeAESInput()
149 case ARM::VORRq: in isSafeAESInput()
150 case ARM::VEORd: in isSafeAESInput()
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H A DARMBaseInstrInfo.cpp90 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
91 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
92 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
93 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
94 { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
95 { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false },
96 { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false },
97 { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false },
100 { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false },
101 { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false },
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H A DThumb2InstrInfo.cpp53 return MCInstBuilder(ARM::tHINT).addImm(0).addImm(ARMCC::AL).addReg(0); in getNop()
92 if (MBBI->getOpcode() == ARM::t2IT) { in ReplaceTailWithBranchTo()
140 get(ARM::t2CSEL), DestReg) in optimizeSelect()
156 if (!ARM::GPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
159 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) in copyPhysReg()
180 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
181 BuildMI(MBB, I, DL, get(ARM::t2STRi12)) in storeRegToStackSlot()
190 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
196 MRI->constrainRegClass(SrcReg, &ARM::GPRPairnospRegClass); in storeRegToStackSlot()
199 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2STRDi8)); in storeRegToStackSlot()
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H A DThumb2SizeReduction.cpp82 { ARM::t2ADCrr, 0, ARM::tADC, 0, 0, 0, 1, 0,0, 0,0,0 },
83 { ARM::t2ADDri, ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 0,0, 0,1,0 },
84 { ARM::t2ADDrr, ARM::tADDrr, ARM::tADDhirr, 0, 0, 1, 0, 0,1, 0,0,0 },
85 { ARM::t2ADDSri,ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 2,2, 0,1,0 },
86 { ARM::t2ADDSrr,ARM::tADDrr, 0, 0, 0, 1, 0, 2,0, 0,1,0 },
87 { ARM::t2ANDrr, 0, ARM::tAND, 0, 0, 0, 1, 0,0, 1,0,0 },
88 { ARM::t2ASRri, ARM::tASRri, 0, 5, 0, 1, 0, 0,0, 1,0,1 },
89 { ARM::t2ASRrr, 0, ARM::tASRrr, 0, 0, 0, 1, 0,0, 1,0,1 },
90 { ARM::t2BICrr, 0, ARM::tBIC, 0, 0, 0, 1, 0,0, 1,0,0 },
93 { ARM::t2CMNzrr, ARM::tCMNz, 0, 0, 0, 1, 0, 2,0, 0,0,0 },
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H A DARMBaseInstrInfo.h378 return MI->getOpcode() == ARM::t2LoopEndDec || in isUnspillableTerminatorImpl()
379 MI->getOpcode() == ARM::t2DoLoopStartTP || in isUnspillableTerminatorImpl()
380 MI->getOpcode() == ARM::t2WhileLoopStartLR || in isUnspillableTerminatorImpl()
381 MI->getOpcode() == ARM::t2WhileLoopStartTP; in isUnspillableTerminatorImpl()
556 return MachineOperand::CreateReg(ARM::CPSR,
563 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B; in isUncondBranchOpcode()
570 return Opc == ARM::MVE_VPTv16i8 || Opc == ARM::MVE_VPTv16u8 || in isVPTOpcode()
571 Opc == ARM::MVE_VPTv16s8 || Opc == ARM::MVE_VPTv8i16 || in isVPTOpcode()
572 Opc == ARM::MVE_VPTv8u16 || Opc == ARM::MVE_VPTv8s16 || in isVPTOpcode()
573 Opc == ARM::MVE_VPTv4i32 || Opc == ARM::MVE_VPTv4u32 || in isVPTOpcode()
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H A DARMInstrInfo.cpp34 NopInst.setOpcode(ARM::HINT); in getNop()
39 NopInst.setOpcode(ARM::MOVr); in getNop()
40 NopInst.addOperand(MCOperand::createReg(ARM::R0)); in getNop()
41 NopInst.addOperand(MCOperand::createReg(ARM::R0)); in getNop()
53 case ARM::LDR_PRE_IMM: in getUnindexedOpcode()
54 case ARM::LDR_PRE_REG: in getUnindexedOpcode()
55 case ARM::LDR_POST_IMM: in getUnindexedOpcode()
56 case ARM::LDR_POST_REG: in getUnindexedOpcode()
57 return ARM::LDRi12; in getUnindexedOpcode()
58 case ARM::LDRH_PRE: in getUnindexedOpcode()
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H A DARMLoadStoreOptimizer.cpp208 if (MO.isDef() && MO.getReg() == ARM::CPSR && !MO.isDead()) in definesCPSR()
219 bool isAM3 = Opcode == ARM::LDRD || Opcode == ARM::STRD; in getMemoryOpOffset()
223 if (Opcode == ARM::t2LDRi12 || Opcode == ARM::t2LDRi8 || in getMemoryOpOffset()
224 Opcode == ARM::t2STRi12 || Opcode == ARM::t2STRi8 || in getMemoryOpOffset()
225 Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8 || in getMemoryOpOffset()
226 Opcode == ARM::LDRi12 || Opcode == ARM::STRi12) in getMemoryOpOffset()
230 if (Opcode == ARM::tLDRi || Opcode == ARM::tSTRi || in getMemoryOpOffset()
231 Opcode == ARM::tLDRspi || Opcode == ARM::tSTRspi) in getMemoryOpOffset()
256 case ARM::LDRi12: in getLoadStoreMultipleOpcode()
260 case ARM_AM::ia: return ARM::LDMIA; in getLoadStoreMultipleOpcode()
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H A DARMAsmPrinter.cpp100 (Subtarget->isTargetELF() ? ARM::S_TARGET1 : ARM::S_None), OutContext); in emitXXStructor()
184 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tBX) in runOnMachineFunction()
228 if(ARM::GPRPairRegClass.contains(Reg)) { in printOperand()
231 Reg = TRI->getSubReg(Reg, ARM::gsub_0); in printOperand()
310 if (!ARM::DPRRegClass.contains(SR)) in PrintAsmOperand()
312 bool Lane0 = TRI->getSubReg(SR, ARM::ssub_0) == Reg; in PrintAsmOperand()
337 if (ARM::GPRPairRegClass.contains(RegBegin)) { in PrintAsmOperand()
339 Register Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0); in PrintAsmOperand()
341 RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1); in PrintAsmOperand()
402 ARM::GPRPairRegClass.hasSubClassEq(TRI->getRegClass(RC))) { in PrintAsmOperand()
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H A DMVETailPredUtils.h30 case ARM::MVE_VCTP8: in VCTPOpcodeToLSTP()
31 return IsDoLoop ? ARM::MVE_DLSTP_8 : ARM::MVE_WLSTP_8; in VCTPOpcodeToLSTP()
32 case ARM::MVE_VCTP16: in VCTPOpcodeToLSTP()
33 return IsDoLoop ? ARM::MVE_DLSTP_16 : ARM::MVE_WLSTP_16; in VCTPOpcodeToLSTP()
34 case ARM::MVE_VCTP32: in VCTPOpcodeToLSTP()
35 return IsDoLoop ? ARM::MVE_DLSTP_32 : ARM::MVE_WLSTP_32; in VCTPOpcodeToLSTP()
36 case ARM::MVE_VCTP64: in VCTPOpcodeToLSTP()
37 return IsDoLoop ? ARM::MVE_DLSTP_64 : ARM::MVE_WLSTP_64; in VCTPOpcodeToLSTP()
46 case ARM::MVE_VCTP8: in getTailPredVectorWidth()
48 case ARM::MVE_VCTP16: in getTailPredVectorWidth()
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H A DThumb1FrameLowering.cpp76 if (ScratchReg == ARM::NoRegister) in emitPrologueEpilogueSPUpdate()
81 unsigned XOInstr = ST.useMovt() ? ARM::t2MOVi32imm : ARM::tMOVi32imm; in emitPrologueEpilogueSPUpdate()
88 BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDhirr), ARM::SP) in emitPrologueEpilogueSPUpdate()
89 .addReg(ARM::SP) in emitPrologueEpilogueSPUpdate()
97 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII, in emitPrologueEpilogueSPUpdate()
107 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII, in emitCallSPUpdate()
134 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) { in eliminateCallFramePseudoInstr()
137 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP); in eliminateCallFramePseudoInstr()
183 ARM::NoRegister, MachineInstr::FrameSetup); in emitPrologue()
192 ARM::NoRegister, MachineInstr::FrameSetup); in emitPrologue()
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H A DARMISelDAGToDAG.cpp519 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD) in hasNoVMLxHazardUse()
1599 Opcode = ARM::LDR_PRE_IMM; in tryARMIndexedLoad()
1603 Opcode = ARM::LDR_POST_IMM; in tryARMIndexedLoad()
1607 Opcode = isPre ? ARM::LDR_PRE_REG : ARM::LDR_POST_REG; in tryARMIndexedLoad()
1614 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST) in tryARMIndexedLoad()
1615 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST); in tryARMIndexedLoad()
1620 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST; in tryARMIndexedLoad()
1626 Opcode = ARM::LDRB_PRE_IMM; in tryARMIndexedLoad()
1630 Opcode = ARM::LDRB_POST_IMM; in tryARMIndexedLoad()
1633 Opcode = isPre ? ARM::LDRB_PRE_REG : ARM::LDRB_POST_REG; in tryARMIndexedLoad()
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H A DARMFrameLowering.cpp218 case ARM::FPCXTNS: in getSpillArea()
221 case ARM::FPSCR: in getSpillArea()
222 case ARM::FPEXC: in getSpillArea()
225 case ARM::R0: in getSpillArea()
226 case ARM::R1: in getSpillArea()
227 case ARM::R2: in getSpillArea()
228 case ARM::R3: in getSpillArea()
229 case ARM::R4: in getSpillArea()
230 case ARM::R5: in getSpillArea()
231 case ARM::R6: in getSpillArea()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMELFObjectWriter.cpp90 case ARM::S_GOTTPOFF: in getRelocType()
91 case ARM::S_GOTTPOFF_FDPIC: in getRelocType()
92 case ARM::S_TLSCALL: in getRelocType()
93 case ARM::S_TLSDESC: in getRelocType()
94 case ARM::S_TLSGD: in getRelocType()
95 case ARM::S_TLSGD_FDPIC: in getRelocType()
96 case ARM::S_TLSLDM: in getRelocType()
97 case ARM::S_TLSLDM_FDPIC: in getRelocType()
98 case ARM::S_TLSLDO: in getRelocType()
99 case ARM::S_TPOFF: in getRelocType()
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H A DARMAsmBackend.cpp67 const static MCFixupKindInfo InfosLE[ARM::NumTargetFixupKinds] = { in getFixupKindInfo()
116 const static MCFixupKindInfo InfosBE[ARM::NumTargetFixupKinds] = { in getFixupKindInfo()
174 assert(unsigned(Kind - FirstTargetFixupKind) < ARM::NumTargetFixupKinds && in getFixupKindInfo()
183 bool HasThumb2 = STI.hasFeature(ARM::FeatureThumb2); in getRelaxedOpcode()
184 bool HasV8MBaselineOps = STI.hasFeature(ARM::HasV8MBaselineOps); in getRelaxedOpcode()
189 case ARM::tBcc: in getRelaxedOpcode()
190 return HasThumb2 ? (unsigned)ARM::t2Bcc : Op; in getRelaxedOpcode()
191 case ARM::tLDRpci: in getRelaxedOpcode()
192 return HasThumb2 ? (unsigned)ARM::t2LDRpci : Op; in getRelaxedOpcode()
193 case ARM::tADR: in getRelaxedOpcode()
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H A DARMTargetStreamer.cpp111 void ARMTargetStreamer::emitArch(ARM::ArchKind Arch) {} in emitArch()
113 void ARMTargetStreamer::emitObjectArch(ARM::ArchKind Arch) {} in emitObjectArch()
114 void ARMTargetStreamer::emitFPU(ARM::FPUKind FPU) {} in emitFPU()
139 if (STI.hasFeature(ARM::HasV9_0aOps)) in getArchForCPU()
141 else if (STI.hasFeature(ARM::HasV8Ops)) { in getArchForCPU()
142 if (STI.hasFeature(ARM::FeatureRClass)) in getArchForCPU()
145 } else if (STI.hasFeature(ARM::HasV8_1MMainlineOps)) in getArchForCPU()
147 else if (STI.hasFeature(ARM::HasV8MMainlineOps)) in getArchForCPU()
149 else if (STI.hasFeature(ARM::HasV7Ops)) { in getArchForCPU()
150 if (STI.hasFeature(ARM::FeatureMClass) && STI.hasFeature(ARM::FeatureDSP)) in getArchForCPU()
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H A DARMMCAsmInfo.cpp21 {ARM::S_GOT_PREL, "GOT_PREL"},
22 {ARM::S_ARM_NONE, "none"},
23 {ARM::S_PREL31, "prel31"},
24 {ARM::S_SBREL, "sbrel"},
25 {ARM::S_TARGET1, "target1"},
26 {ARM::S_TARGET2, "target2"},
27 {ARM::S_TLSLDO, "TLSLDO"},
29 {ARM::S_FUNCDESC, "FUNCDESC"},
30 {ARM::S_GOT, "GOT"},
31 {ARM::S_GOTFUNCDESC, "GOTFUNCDESC"},
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H A DARMMCTargetDesc.cpp41 if (STI.hasFeature(llvm::ARM::HasV7Ops) && in getMCRDeprecationInfo()
68 if (STI.hasFeature(llvm::ARM::HasV7Ops) && in getMCRDeprecationInfo()
80 if (STI.hasFeature(llvm::ARM::HasV7Ops) && in getMRCDeprecationInfo()
92 assert(!STI.hasFeature(llvm::ARM::ModeThumb) && in getARMStoreDeprecationInfo()
98 if (MI.getOperand(OI).getReg() == ARM::PC) { in getARMStoreDeprecationInfo()
108 assert(!STI.hasFeature(llvm::ARM::ModeThumb) && in getARMLoadDeprecationInfo()
118 case ARM::LR: in getARMLoadDeprecationInfo()
121 case ARM::PC: in getARMLoadDeprecationInfo()
145 ARM::ArchKind ArchID = ARM::parseArch(TT.getArchName()); in ParseARMTriple()
146 if (ArchID != ARM::ArchKind::INVALID && (CPU.empty() || CPU == "generic")) in ParseARMTriple()
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/freebsd/contrib/llvm-project/llvm/lib/TargetParser/
H A DARMTargetParser.cpp31 ARM::ArchKind ARM::parseArch(StringRef Arch) { in parseArch()
42 unsigned ARM::parseArchVersion(StringRef Arch) { in parseArchVersion()
98 static ARM::ProfileKind getProfileKind(ARM::ArchKind AK) { in getProfileKind()
100 case ARM::ArchKind::ARMV6M: in getProfileKind()
101 case ARM::ArchKind::ARMV7M: in getProfileKind()
102 case ARM::ArchKind::ARMV7EM: in getProfileKind()
103 case ARM::ArchKind::ARMV8MMainline: in getProfileKind()
104 case ARM::ArchKind::ARMV8MBaseline: in getProfileKind()
105 case ARM::ArchKind::ARMV8_1MMainline: in getProfileKind()
106 return ARM::ProfileKind::M; in getProfileKind()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp138 InstructionEndianness = STI.hasFeature(ARM::ModeBigEndianInstructions) in ARMDisassembler()
721 case ARM::HVC: { in checkDecodedInstruction()
731 case ARM::t2ADDri: in checkDecodedInstruction()
732 case ARM::t2ADDri12: in checkDecodedInstruction()
733 case ARM::t2ADDrr: in checkDecodedInstruction()
734 case ARM::t2ADDrs: in checkDecodedInstruction()
735 case ARM::t2SUBri: in checkDecodedInstruction()
736 case ARM::t2SUBri12: in checkDecodedInstruction()
737 case ARM::t2SUBrr: in checkDecodedInstruction()
738 case ARM::t2SUBrs: in checkDecodedInstruction()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp118 UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {} in UnwindContext()
174 FPReg = ARM::SP; in reset()
302 ITInst.setOpcode(ARM::t2IT); in flushPendingInstructions()
457 bool parsePrefix(ARM::Specifier &);
529 return getSTI().hasFeature(ARM::ModeThumb); in isThumb()
533 return isThumb() && !getSTI().hasFeature(ARM::FeatureThumb2); in isThumbOne()
537 return isThumb() && getSTI().hasFeature(ARM::FeatureThumb2); in isThumbTwo()
541 return getSTI().hasFeature(ARM::HasV4TOps); in hasThumb()
545 return getSTI().hasFeature(ARM::FeatureThumb2); in hasThumb2()
549 return getSTI().hasFeature(ARM::HasV6Ops); in hasV6Ops()
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/freebsd/contrib/llvm-project/clang/lib/Basic/Targets/
H A DARM.cpp116 ArchISA = llvm::ARM::parseArchISA(ArchName); in setArchInfo()
117 CPU = std::string(llvm::ARM::getDefaultCPU(ArchName)); in setArchInfo()
118 llvm::ARM::ArchKind AK = llvm::ARM::parseArch(ArchName); in setArchInfo()
119 if (AK != llvm::ARM::ArchKind::INVALID) in setArchInfo()
124 void ARMTargetInfo::setArchInfo(llvm::ARM::ArchKind Kind) { in setArchInfo()
129 SubArch = llvm::ARM::getSubArch(ArchKind); in setArchInfo()
130 ArchProfile = llvm::ARM::parseArchProfile(SubArch); in setArchInfo()
131 ArchVersion = llvm::ARM::parseArchVersion(SubArch); in setArchInfo()
142 (ArchISA == llvm::ARM::ISAKind::ARM && ArchVersion >= 6) || in setAtomic()
143 (ArchISA == llvm::ARM::ISAKind::THUMB && ArchVersion >= 7); in setAtomic()
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