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Searched refs:ARM (Results 1 – 25 of 514) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/include/llvm/TargetParser/
H A DARMTargetParser.def1 //===- ARMTargetParser.def - ARM target parsing defines ---------*- C++ -*-===//
9 // This file provides defines to build up the ARM target parser's logic.
74 ARM::AEK_NONE)
76 ARM::AEK_NONE)
78 ARM::AEK_NONE)
80 ARM::AEK_NONE)
82 FK_NONE, ARM::AEK_DSP)
84 FK_NONE, ARM::AEK_DSP)
86 ARM::AEK_DSP)
88 ARM::AEK_DSP)
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMExpandPseudoInsts.cpp171 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true},
172 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true},
173 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true},
174 { ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, true, EvenDblSpc, 1, 2 ,true},
175 { ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, false, EvenDblSpc, 1, 8 ,true},
176 { ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, true, true, EvenDblSpc, 1, 8 ,true},
178 { ARM::VLD1d16QPseudo, ARM::VLD1d16Q, true, false, false, SingleSpc, 4, 4 ,false},
179 { ARM::VLD1d16QPseudoWB_fixed, ARM::VLD1d16Qwb_fixed, true, true, false, SingleSpc, 4, 4 ,false…
180 { ARM::VLD1d16QPseudoWB_register, ARM::VLD1d16Qwb_register, true, true, true, SingleSpc, 4, 4 ,fa…
181 { ARM::VLD1d16TPseudo, ARM::VLD1d16T, true, false, false, SingleSpc, 3, 4 ,false},
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H A DARMFeatures.h28 case ARM::tADC: in isV8EligibleForIT()
29 case ARM::tADDi3: in isV8EligibleForIT()
30 case ARM::tADDi8: in isV8EligibleForIT()
31 case ARM::tADDrr: in isV8EligibleForIT()
32 case ARM::tAND: in isV8EligibleForIT()
33 case ARM::tASRri: in isV8EligibleForIT()
34 case ARM::tASRrr: in isV8EligibleForIT()
35 case ARM::tBIC: in isV8EligibleForIT()
36 case ARM::tEOR: in isV8EligibleForIT()
37 case ARM::tLSLri: in isV8EligibleForIT()
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H A DARMFixCortexA57AES1742098Pass.cpp129 return Opc == ARM::AESD || Opc == ARM::AESE; in isFirstAESPairInstr()
145 case ARM::AESD: in isSafeAESInput()
146 case ARM::AESE: in isSafeAESInput()
147 case ARM::AESMC: in isSafeAESInput()
148 case ARM::AESIMC: in isSafeAESInput()
152 case ARM::VANDd: in isSafeAESInput()
153 case ARM::VANDq: in isSafeAESInput()
154 case ARM::VORRd: in isSafeAESInput()
155 case ARM::VORRq: in isSafeAESInput()
156 case ARM::VEORd: in isSafeAESInput()
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H A DARMRegisterBankInfo.cpp30 namespace ARM { namespace
142 const RegisterBank &RBGPR = getRegBank(ARM::GPRRegBankID); in ARMRegisterBankInfo()
144 assert(&ARM::GPRRegBank == &RBGPR && "The order in RegBanks is messed up"); in ARMRegisterBankInfo()
147 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRRegClassID)) && in ARMRegisterBankInfo()
149 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRwithAPSRRegClassID)) && in ARMRegisterBankInfo()
151 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnopcRegClassID)) && in ARMRegisterBankInfo()
153 assert(RBGPR.covers(*TRI.getRegClass(ARM::rGPRRegClassID)) && in ARMRegisterBankInfo()
155 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPRRegClassID)) && in ARMRegisterBankInfo()
157 assert(RBGPR.covers(*TRI.getRegClass(ARM::tcGPRRegClassID)) && in ARMRegisterBankInfo()
159 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPROdd_and_tcGPRRegClassID)) && in ARMRegisterBankInfo()
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H A DARMBaseInstrInfo.cpp96 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
97 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
98 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
99 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
100 { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
101 { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false },
102 { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false },
103 { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false },
106 { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false },
107 { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false },
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H A DThumb2InstrInfo.cpp54 return MCInstBuilder(ARM::tHINT).addImm(0).addImm(ARMCC::AL).addReg(0); in getNop()
93 if (MBBI->getOpcode() == ARM::t2IT) { in ReplaceTailWithBranchTo()
141 get(ARM::t2CSEL), DestReg) in optimizeSelect()
156 if (!ARM::GPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
159 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) in copyPhysReg()
179 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
180 BuildMI(MBB, I, DL, get(ARM::t2STRi12)) in storeRegToStackSlot()
189 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
195 MRI->constrainRegClass(SrcReg, &ARM::GPRPairnospRegClass); in storeRegToStackSlot()
198 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2STRDi8)); in storeRegToStackSlot()
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H A DThumb2SizeReduction.cpp84 { ARM::t2ADCrr, 0, ARM::tADC, 0, 0, 0, 1, 0,0, 0,0,0 },
85 { ARM::t2ADDri, ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 0,0, 0,1,0 },
86 { ARM::t2ADDrr, ARM::tADDrr, ARM::tADDhirr, 0, 0, 1, 0, 0,1, 0,0,0 },
87 { ARM::t2ADDSri,ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 2,2, 0,1,0 },
88 { ARM::t2ADDSrr,ARM::tADDrr, 0, 0, 0, 1, 0, 2,0, 0,1,0 },
89 { ARM::t2ANDrr, 0, ARM::tAND, 0, 0, 0, 1, 0,0, 1,0,0 },
90 { ARM::t2ASRri, ARM::tASRri, 0, 5, 0, 1, 0, 0,0, 1,0,1 },
91 { ARM::t2ASRrr, 0, ARM::tASRrr, 0, 0, 0, 1, 0,0, 1,0,1 },
92 { ARM::t2BICrr, 0, ARM::tBIC, 0, 0, 0, 1, 0,0, 1,0,0 },
95 { ARM::t2CMNzrr, ARM::tCMNz, 0, 0, 0, 1, 0, 2,0, 0,0,0 },
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H A DARMInstrInfo.cpp38 NopInst.setOpcode(ARM::HINT); in getNop()
43 NopInst.setOpcode(ARM::MOVr); in getNop()
44 NopInst.addOperand(MCOperand::createReg(ARM::R0)); in getNop()
45 NopInst.addOperand(MCOperand::createReg(ARM::R0)); in getNop()
57 case ARM::LDR_PRE_IMM: in getUnindexedOpcode()
58 case ARM::LDR_PRE_REG: in getUnindexedOpcode()
59 case ARM::LDR_POST_IMM: in getUnindexedOpcode()
60 case ARM::LDR_POST_REG: in getUnindexedOpcode()
61 return ARM::LDRi12; in getUnindexedOpcode()
62 case ARM::LDRH_PRE: in getUnindexedOpcode()
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H A DARMLoadStoreOptimizer.cpp211 if (MO.isDef() && MO.getReg() == ARM::CPSR && !MO.isDead()) in definesCPSR()
222 bool isAM3 = Opcode == ARM::LDRD || Opcode == ARM::STRD; in getMemoryOpOffset()
226 if (Opcode == ARM::t2LDRi12 || Opcode == ARM::t2LDRi8 || in getMemoryOpOffset()
227 Opcode == ARM::t2STRi12 || Opcode == ARM::t2STRi8 || in getMemoryOpOffset()
228 Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8 || in getMemoryOpOffset()
229 Opcode == ARM::LDRi12 || Opcode == ARM::STRi12) in getMemoryOpOffset()
233 if (Opcode == ARM::tLDRi || Opcode == ARM::tSTRi || in getMemoryOpOffset()
234 Opcode == ARM::tLDRspi || Opcode == ARM::tSTRspi) in getMemoryOpOffset()
259 case ARM::LDRi12: in getLoadStoreMultipleOpcode()
263 case ARM_AM::ia: return ARM::LDMIA; in getLoadStoreMultipleOpcode()
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H A DARMBaseInstrInfo.h377 return MI->getOpcode() == ARM::t2LoopEndDec || in isUnspillableTerminatorImpl()
378 MI->getOpcode() == ARM::t2DoLoopStartTP || in isUnspillableTerminatorImpl()
379 MI->getOpcode() == ARM::t2WhileLoopStartLR || in isUnspillableTerminatorImpl()
380 MI->getOpcode() == ARM::t2WhileLoopStartTP; in isUnspillableTerminatorImpl()
546 if (RegClassID == ARM::MQPRRegClass.getID()) in getUndefInitOpcode()
547 return ARM::PseudoARMInitUndefMQPR; in getUndefInitOpcode()
548 if (RegClassID == ARM::SPRRegClass.getID()) in getUndefInitOpcode()
549 return ARM::PseudoARMInitUndefSPR; in getUndefInitOpcode()
550 if (RegClassID == ARM::DPR_VFP2RegClass.getID()) in getUndefInitOpcode()
551 return ARM::PseudoARMInitUndefDPR_VFP2; in getUndefInitOpcode()
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H A DARMISelDAGToDAG.cpp119 Reg = CurDAG->getRegister(ARM::CPSR, MVT::i32); in SelectCMOVPred()
528 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD) in hasNoVMLxHazardUse()
1608 Opcode = ARM::LDR_PRE_IMM; in tryARMIndexedLoad()
1612 Opcode = ARM::LDR_POST_IMM; in tryARMIndexedLoad()
1616 Opcode = isPre ? ARM::LDR_PRE_REG : ARM::LDR_POST_REG; in tryARMIndexedLoad()
1623 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST) in tryARMIndexedLoad()
1624 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST); in tryARMIndexedLoad()
1629 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST; in tryARMIndexedLoad()
1635 Opcode = ARM::LDRB_PRE_IMM; in tryARMIndexedLoad()
1639 Opcode = ARM::LDRB_POST_IMM; in tryARMIndexedLoad()
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H A DMVETailPredUtils.h30 case ARM::MVE_VCTP8: in VCTPOpcodeToLSTP()
31 return IsDoLoop ? ARM::MVE_DLSTP_8 : ARM::MVE_WLSTP_8; in VCTPOpcodeToLSTP()
32 case ARM::MVE_VCTP16: in VCTPOpcodeToLSTP()
33 return IsDoLoop ? ARM::MVE_DLSTP_16 : ARM::MVE_WLSTP_16; in VCTPOpcodeToLSTP()
34 case ARM::MVE_VCTP32: in VCTPOpcodeToLSTP()
35 return IsDoLoop ? ARM::MVE_DLSTP_32 : ARM::MVE_WLSTP_32; in VCTPOpcodeToLSTP()
36 case ARM::MVE_VCTP64: in VCTPOpcodeToLSTP()
37 return IsDoLoop ? ARM::MVE_DLSTP_64 : ARM::MVE_WLSTP_64; in VCTPOpcodeToLSTP()
46 case ARM::MVE_VCTP8: in getTailPredVectorWidth()
48 case ARM::MVE_VCTP16: in getTailPredVectorWidth()
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H A DARMAsmPrinter.cpp181 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tBX) in runOnMachineFunction()
225 if(ARM::GPRPairRegClass.contains(Reg)) { in printOperand()
228 Reg = TRI->getSubReg(Reg, ARM::gsub_0); in printOperand()
307 if (!ARM::DPRRegClass.contains(SR)) in PrintAsmOperand()
309 bool Lane0 = TRI->getSubReg(SR, ARM::ssub_0) == Reg; in PrintAsmOperand()
334 if (ARM::GPRPairRegClass.contains(RegBegin)) { in PrintAsmOperand()
336 Register Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0); in PrintAsmOperand()
338 RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1); in PrintAsmOperand()
399 ARM::GPRPairRegClass.hasSubClassEq(TRI->getRegClass(RC))) { in PrintAsmOperand()
407 TRI->getSubReg(MO.getReg(), FirstHalf ? ARM::gsub_0 : ARM::gsub_1); in PrintAsmOperand()
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H A DARMFrameLowering.cpp259 IsTailCallReturn = RetOpcode == ARM::TCRETURNdi || in getArgumentStackToRestore()
260 RetOpcode == ARM::TCRETURNri || in getArgumentStackToRestore()
261 RetOpcode == ARM::TCRETURNrinotr12; in getArgumentStackToRestore()
309 case ARM::t2ADDri: // add.w r11, sp, #xx in insertSEH()
310 case ARM::t2ADDri12: // add.w r11, sp, #xx in insertSEH()
311 case ARM::t2MOVTi16: // movt r4, #xx in insertSEH()
312 case ARM::tBL: // bl __chkstk in insertSEH()
316 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop)) in insertSEH()
321 case ARM::t2MOVi16: { // mov(w) r4, #xx in insertSEH()
325 BuildMI(MF, DL, TII.get(ARM::tMOVi8)).setMIFlags(MBBI->getFlags()); in insertSEH()
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H A DARMTargetTransformInfo.h73 ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureNEON, ARM::FeatureThumb2,
74 ARM::FeatureFP16, ARM::FeatureVFP4, ARM::FeatureFPARMv8,
75 ARM::FeatureFullFP16, ARM::FeatureFP16FML, ARM::FeatureHWDivThumb,
76 ARM::FeatureHWDivARM, ARM::FeatureDB, ARM::FeatureV7Clrex,
77 ARM::FeatureAcquireRelease, ARM::FeatureSlowFPBrcc,
78 ARM::FeaturePerfMon, ARM::FeatureTrustZone, ARM::Feature8MSecExt,
79 ARM::FeatureCrypto, ARM::FeatureCRC, ARM::FeatureRAS,
80 ARM::FeatureFPAO, ARM::FeatureFuseAES, ARM::FeatureZCZeroing,
81 ARM::FeatureProfUnpredicate, ARM::FeatureSlowVGETLNi32,
82 ARM::FeatureSlowVDUP32, ARM::FeaturePreferVMOVSR,
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H A DThumb1FrameLowering.cpp78 if (ScratchReg == ARM::NoRegister) in emitPrologueEpilogueSPUpdate()
83 unsigned XOInstr = ST.useMovt() ? ARM::t2MOVi32imm : ARM::tMOVi32imm; in emitPrologueEpilogueSPUpdate()
90 BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDhirr), ARM::SP) in emitPrologueEpilogueSPUpdate()
91 .addReg(ARM::SP) in emitPrologueEpilogueSPUpdate()
99 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII, in emitPrologueEpilogueSPUpdate()
109 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII, in emitCallSPUpdate()
136 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) { in eliminateCallFramePseudoInstr()
139 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP); in eliminateCallFramePseudoInstr()
183 ARM::NoRegister, MachineInstr::FrameSetup); in emitPrologue()
196 ARM::NoRegister, MachineInstr::FrameSetup); in emitPrologue()
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H A DARMCallingConv.cpp24 static const MCPhysReg RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAPCS()
65 static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 }; in f64AssignAAPCS()
66 static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 }; in f64AssignAAPCS()
67 static const MCPhysReg ShadowRegList[] = { ARM::R0, ARM::R1 }; in f64AssignAAPCS()
68 static const MCPhysReg GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAAPCS()
75 assert((!Reg || Reg == ARM::R3) && "Wrong GPRs usage for f64"); in f64AssignAAPCS()
116 static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 }; in f64RetAssign()
117 static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 }; in f64RetAssign()
153 static const MCPhysReg RRegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
155 static const MCPhysReg SRegList[] = { ARM::S0, ARM::S1, ARM::S2, ARM::S3,
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/freebsd/contrib/llvm-project/llvm/lib/TargetParser/
H A DARMTargetParser.cpp31 ARM::ArchKind ARM::parseArch(StringRef Arch) { in parseArch()
42 unsigned ARM::parseArchVersion(StringRef Arch) { in parseArchVersion()
97 static ARM::ProfileKind getProfileKind(ARM::ArchKind AK) { in getProfileKind()
99 case ARM::ArchKind::ARMV6M: in getProfileKind()
100 case ARM::ArchKind::ARMV7M: in getProfileKind()
101 case ARM::ArchKind::ARMV7EM: in getProfileKind()
102 case ARM::ArchKind::ARMV8MMainline: in getProfileKind()
103 case ARM::ArchKind::ARMV8MBaseline: in getProfileKind()
104 case ARM::ArchKind::ARMV8_1MMainline: in getProfileKind()
105 return ARM::ProfileKind::M; in getProfileKind()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMAsmBackend.cpp70 const static MCFixupKindInfo InfosLE[ARM::NumTargetFixupKinds] = { in getFixupKindInfo()
132 const static MCFixupKindInfo InfosBE[ARM::NumTargetFixupKinds] = { in getFixupKindInfo()
225 bool HasThumb2 = STI.hasFeature(ARM::FeatureThumb2); in getRelaxedOpcode()
226 bool HasV8MBaselineOps = STI.hasFeature(ARM::HasV8MBaselineOps); in getRelaxedOpcode()
231 case ARM::tBcc: in getRelaxedOpcode()
232 return HasThumb2 ? (unsigned)ARM::t2Bcc : Op; in getRelaxedOpcode()
233 case ARM::tLDRpci: in getRelaxedOpcode()
234 return HasThumb2 ? (unsigned)ARM::t2LDRpci : Op; in getRelaxedOpcode()
235 case ARM::tADR: in getRelaxedOpcode()
236 return HasThumb2 ? (unsigned)ARM::t2ADR : Op; in getRelaxedOpcode()
[all …]
H A DARMTargetStreamer.cpp111 void ARMTargetStreamer::emitArch(ARM::ArchKind Arch) {} in emitArch()
113 void ARMTargetStreamer::emitObjectArch(ARM::ArchKind Arch) {} in emitObjectArch()
114 void ARMTargetStreamer::emitFPU(ARM::FPUKind FPU) {} in emitFPU()
135 if (STI.hasFeature(ARM::HasV9_0aOps)) in getArchForCPU()
137 else if (STI.hasFeature(ARM::HasV8Ops)) { in getArchForCPU()
138 if (STI.hasFeature(ARM::FeatureRClass)) in getArchForCPU()
141 } else if (STI.hasFeature(ARM::HasV8_1MMainlineOps)) in getArchForCPU()
143 else if (STI.hasFeature(ARM::HasV8MMainlineOps)) in getArchForCPU()
145 else if (STI.hasFeature(ARM::HasV7Ops)) { in getArchForCPU()
146 if (STI.hasFeature(ARM in getArchForCPU()
[all...]
H A DARMMCTargetDesc.cpp40 if (STI.hasFeature(llvm::ARM::HasV7Ops) && in getMCRDeprecationInfo()
67 if (STI.hasFeature(llvm::ARM::HasV7Ops) && in getMCRDeprecationInfo()
79 if (STI.hasFeature(llvm::ARM::HasV7Ops) && in getMRCDeprecationInfo()
91 assert(!STI.hasFeature(llvm::ARM::ModeThumb) && in getARMStoreDeprecationInfo()
97 if (MI.getOperand(OI).getReg() == ARM::PC) { in getARMStoreDeprecationInfo()
107 assert(!STI.hasFeature(llvm::ARM::ModeThumb) && in getARMLoadDeprecationInfo()
117 case ARM::LR: in getARMLoadDeprecationInfo()
120 case ARM::PC: in getARMLoadDeprecationInfo()
144 ARM::ArchKind ArchID = ARM::parseArch(TT.getArchName()); in ParseARMTriple()
145 if (ArchID != ARM::ArchKind::INVALID && (CPU.empty() || CPU == "generic")) in ParseARMTriple()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp138 InstructionEndianness = STI.hasFeature(ARM::ModeBigEndianInstructions) in ARMDisassembler()
721 case ARM::HVC: { in checkDecodedInstruction()
731 case ARM::t2ADDri: in checkDecodedInstruction()
732 case ARM::t2ADDri12: in checkDecodedInstruction()
733 case ARM::t2ADDrr: in checkDecodedInstruction()
734 case ARM::t2ADDrs: in checkDecodedInstruction()
735 case ARM::t2SUBri: in checkDecodedInstruction()
736 case ARM::t2SUBri12: in checkDecodedInstruction()
737 case ARM::t2SUBrr: in checkDecodedInstruction()
738 case ARM::t2SUBrs: in checkDecodedInstruction()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp119 UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {} in UnwindContext()
175 FPReg = ARM::SP; in reset()
299 ITInst.setOpcode(ARM::t2IT); in flushPendingInstructions()
526 return getSTI().hasFeature(ARM::ModeThumb); in isThumb()
530 return isThumb() && !getSTI().hasFeature(ARM::FeatureThumb2); in isThumbOne()
534 return isThumb() && getSTI().hasFeature(ARM::FeatureThumb2); in isThumbTwo()
538 return getSTI().hasFeature(ARM::HasV4TOps); in hasThumb()
542 return getSTI().hasFeature(ARM::FeatureThumb2); in hasThumb2()
546 return getSTI().hasFeature(ARM::HasV6Ops); in hasV6Ops()
550 return getSTI().hasFeature(ARM::HasV6T2Ops); in hasV6T2Ops()
[all …]
/freebsd/contrib/llvm-project/clang/lib/Basic/Targets/
H A DARM.cpp117 ArchISA = llvm::ARM::parseArchISA(ArchName); in setArchInfo()
118 CPU = std::string(llvm::ARM::getDefaultCPU(ArchName)); in setArchInfo()
119 llvm::ARM::ArchKind AK = llvm::ARM::parseArch(ArchName); in setArchInfo()
120 if (AK != llvm::ARM::ArchKind::INVALID) in setArchInfo()
125 void ARMTargetInfo::setArchInfo(llvm::ARM::ArchKind Kind) { in setArchInfo()
130 SubArch = llvm::ARM::getSubArch(ArchKind); in setArchInfo()
131 ArchProfile = llvm::ARM::parseArchProfile(SubArch); in setArchInfo()
132 ArchVersion = llvm::ARM::parseArchVersion(SubArch); in setArchInfo()
143 (ArchISA == llvm::ARM::ISAKind::ARM && ArchVersion >= 6) || in setAtomic()
144 (ArchISA == llvm::ARM::ISAKind::THUMB && ArchVersion >= 7); in setAtomic()
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