Lines Matching refs:ARM
259 IsTailCallReturn = RetOpcode == ARM::TCRETURNdi || in getArgumentStackToRestore()
260 RetOpcode == ARM::TCRETURNri || in getArgumentStackToRestore()
261 RetOpcode == ARM::TCRETURNrinotr12; in getArgumentStackToRestore()
309 case ARM::t2ADDri: // add.w r11, sp, #xx in insertSEH()
310 case ARM::t2ADDri12: // add.w r11, sp, #xx in insertSEH()
311 case ARM::t2MOVTi16: // movt r4, #xx in insertSEH()
312 case ARM::tBL: // bl __chkstk in insertSEH()
316 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop)) in insertSEH()
321 case ARM::t2MOVi16: { // mov(w) r4, #xx in insertSEH()
325 BuildMI(MF, DL, TII.get(ARM::tMOVi8)).setMIFlags(MBBI->getFlags()); in insertSEH()
334 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop)).addImm(Wide).setMIFlags(Flags); in insertSEH()
338 case ARM::tBLXr: // blx r12 (__chkstk) in insertSEH()
339 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop)) in insertSEH()
344 case ARM::t2MOVi32imm: // movw+movt in insertSEH()
352 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop)) in insertSEH()
356 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop)) in insertSEH()
361 case ARM::t2STR_PRE: in insertSEH()
362 if (MBBI->getOperand(0).getReg() == ARM::SP && in insertSEH()
363 MBBI->getOperand(2).getReg() == ARM::SP && in insertSEH()
366 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_SaveRegs)) in insertSEH()
375 case ARM::t2LDR_POST: in insertSEH()
376 if (MBBI->getOperand(1).getReg() == ARM::SP && in insertSEH()
377 MBBI->getOperand(2).getReg() == ARM::SP && in insertSEH()
380 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_SaveRegs)) in insertSEH()
389 case ARM::t2LDMIA_RET: in insertSEH()
390 case ARM::t2LDMIA_UPD: in insertSEH()
391 case ARM::t2STMDB_UPD: { in insertSEH()
403 else if (Opc == ARM::t2LDMIA_UPD && Reg == 14) in insertSEH()
410 case ARM::t2LDMIA_RET: in insertSEH()
411 NewOpc = ARM::tPOP_RET; in insertSEH()
413 case ARM::t2LDMIA_UPD: in insertSEH()
414 NewOpc = ARM::tPOP; in insertSEH()
416 case ARM::t2STMDB_UPD: in insertSEH()
417 NewOpc = ARM::tPUSH; in insertSEH()
431 (Opc == ARM::t2LDMIA_RET) ? ARM::SEH_SaveRegs_Ret : ARM::SEH_SaveRegs; in insertSEH()
438 case ARM::VSTMDDB_UPD: in insertSEH()
439 case ARM::VLDMDIA_UPD: { in insertSEH()
447 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_SaveFRegs)) in insertSEH()
453 case ARM::tSUBspi: in insertSEH()
454 case ARM::tADDspi: in insertSEH()
455 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_StackAlloc)) in insertSEH()
460 case ARM::t2SUBspImm: in insertSEH()
461 case ARM::t2SUBspImm12: in insertSEH()
462 case ARM::t2ADDspImm: in insertSEH()
463 case ARM::t2ADDspImm12: in insertSEH()
464 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_StackAlloc)) in insertSEH()
470 case ARM::tMOVr: in insertSEH()
471 if (MBBI->getOperand(1).getReg() == ARM::SP && in insertSEH()
474 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_SaveSP)) in insertSEH()
477 } else if (MBBI->getOperand(0).getReg() == ARM::SP && in insertSEH()
480 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_SaveSP)) in insertSEH()
488 case ARM::tBX_RET: in insertSEH()
489 case ARM::TCRETURNri: in insertSEH()
490 case ARM::TCRETURNrinotr12: in insertSEH()
491 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop_Ret)) in insertSEH()
496 case ARM::TCRETURNdi: in insertSEH()
497 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop_Ret)) in insertSEH()
555 emitRegPlusImmediate(isARM, MBB, MBBI, dl, TII, ARM::SP, ARM::SP, NumBytes, in emitSPUpdate()
562 case ARM::VSTMDDB_UPD: in sizeOfSPAdjustment()
565 case ARM::STMDB_UPD: in sizeOfSPAdjustment()
566 case ARM::t2STMDB_UPD: in sizeOfSPAdjustment()
569 case ARM::t2STR_PRE: in sizeOfSPAdjustment()
570 case ARM::STR_PRE_IMM: in sizeOfSPAdjustment()
671 BuildMI(MBB, MBBI, DL, TII.get(ARM::BFC), Reg) in emitAligningInstructions()
676 BuildMI(MBB, MBBI, DL, TII.get(ARM::BICri), Reg) in emitAligningInstructions()
686 BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg) in emitAligningInstructions()
691 BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg) in emitAligningInstructions()
701 BuildMI(MBB, MBBI, DL, TII.get(ARM::t2BFC), Reg) in emitAligningInstructions()
784 BuildMI(MBB, MBBI, dl, TII.get(ARM::SEH_PrologEnd)) in emitPrologue()
797 case ARM::R11: in emitPrologue()
798 case ARM::LR: in emitPrologue()
803 case ARM::R0: in emitPrologue()
804 case ARM::R1: in emitPrologue()
805 case ARM::R2: in emitPrologue()
806 case ARM::R3: in emitPrologue()
807 case ARM::R4: in emitPrologue()
808 case ARM::R5: in emitPrologue()
809 case ARM::R6: in emitPrologue()
810 case ARM::R7: in emitPrologue()
811 case ARM::R8: in emitPrologue()
812 case ARM::R9: in emitPrologue()
813 case ARM::R10: in emitPrologue()
814 case ARM::R12: in emitPrologue()
817 case ARM::FPCXTNS: in emitPrologue()
822 if (Reg == ARM::D8) in emitPrologue()
824 if (Reg < ARM::D8 || Reg >= ARM::D8 + AFI->getNumAlignedDPRCS2Regs()) in emitPrologue()
833 case ARM::R8: in emitPrologue()
834 case ARM::R9: in emitPrologue()
835 case ARM::R10: in emitPrologue()
836 case ARM::R11: in emitPrologue()
837 case ARM::R12: in emitPrologue()
843 case ARM::R0: in emitPrologue()
844 case ARM::R1: in emitPrologue()
845 case ARM::R2: in emitPrologue()
846 case ARM::R3: in emitPrologue()
847 case ARM::R4: in emitPrologue()
848 case ARM::R5: in emitPrologue()
849 case ARM::R6: in emitPrologue()
850 case ARM::R7: in emitPrologue()
851 case ARM::LR: in emitPrologue()
856 case ARM::FPCXTNS: in emitPrologue()
861 if (Reg == ARM::D8) in emitPrologue()
863 if (Reg < ARM::D8 || Reg >= ARM::D8 + AFI->getNumAlignedDPRCS2Regs()) in emitPrologue()
950 while (MBBI != MBB.end() && MBBI->getOpcode() == ARM::VSTMDDB_UPD) { in emitPrologue()
980 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), ARM::R4) in emitPrologue()
988 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), ARM::R4) in emitPrologue()
992 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), ARM::R4) in emitPrologue()
993 .addReg(ARM::R4) in emitPrologue()
1005 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBL)) in emitPrologue()
1008 .addReg(ARM::R4, RegState::Implicit) in emitPrologue()
1012 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R12) in emitPrologue()
1016 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBLXr)) in emitPrologue()
1018 .addReg(ARM::R12, RegState::Kill) in emitPrologue()
1019 .addReg(ARM::R4, RegState::Implicit) in emitPrologue()
1025 Instr = BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), ARM::SP) in emitPrologue()
1026 .addReg(ARM::SP, RegState::Kill) in emitPrologue()
1027 .addReg(ARM::R4, RegState::Kill) in emitPrologue()
1032 SEH = BuildMI(MF, dl, TII.get(ARM::SEH_StackAlloc)) in emitPrologue()
1081 FramePtr, ARM::SP, 0, MachineInstr::FrameSetup); in emitPrologue()
1084 FramePtr, ARM::SP, FPOffset, in emitPrologue()
1113 BuildMI(MBB, End, dl, TII.get(ARM::SEH_PrologEnd)) in emitPrologue()
1128 case ARM::R8: in emitPrologue()
1129 case ARM::R9: in emitPrologue()
1130 case ARM::R10: in emitPrologue()
1131 case ARM::R11: in emitPrologue()
1132 case ARM::R12: in emitPrologue()
1136 case ARM::R0: in emitPrologue()
1137 case ARM::R1: in emitPrologue()
1138 case ARM::R2: in emitPrologue()
1139 case ARM::R3: in emitPrologue()
1140 case ARM::R4: in emitPrologue()
1141 case ARM::R5: in emitPrologue()
1142 case ARM::R6: in emitPrologue()
1143 case ARM::R7: in emitPrologue()
1144 case ARM::LR: in emitPrologue()
1161 case ARM::R8: in emitPrologue()
1162 case ARM::R9: in emitPrologue()
1163 case ARM::R10: in emitPrologue()
1164 case ARM::R11: in emitPrologue()
1165 case ARM::R12: in emitPrologue()
1168 Reg == ARM::R12 ? ARM::RA_AUTH_CODE : Reg, true); in emitPrologue()
1188 if ((Reg >= ARM::D0 && Reg <= ARM::D31) && in emitPrologue()
1189 (Reg < ARM::D8 || Reg >= ARM::D8 + AFI->getNumAlignedDPRCS2Regs())) { in emitPrologue()
1226 emitAligningInstructions(MF, AFI, TII, MBB, MBBI, dl, ARM::SP, MaxAlign, in emitPrologue()
1236 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4) in emitPrologue()
1237 .addReg(ARM::SP, RegState::Kill) in emitPrologue()
1239 emitAligningInstructions(MF, AFI, TII, MBB, MBBI, dl, ARM::R4, MaxAlign, in emitPrologue()
1241 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP) in emitPrologue()
1242 .addReg(ARM::R4, RegState::Kill) in emitPrologue()
1256 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), RegInfo->getBaseRegister()) in emitPrologue()
1257 .addReg(ARM::SP) in emitPrologue()
1261 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), RegInfo->getBaseRegister()) in emitPrologue()
1262 .addReg(ARM::SP) in emitPrologue()
1306 BuildMI(MBB, MBBI, dl, TII.get(ARM::SEH_EpilogStart)) in emitEpilogue()
1327 BuildMI(MBB, MBBI, dl, TII.get(ARM::SEH_EpilogStart)) in emitEpilogue()
1346 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes, in emitEpilogue()
1357 assert(!MFI.getPristineRegs(MF).test(ARM::R4) && in emitEpilogue()
1359 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes, in emitEpilogue()
1361 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP) in emitEpilogue()
1362 .addReg(ARM::R4) in emitEpilogue()
1369 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP) in emitEpilogue()
1375 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP) in emitEpilogue()
1393 while (MBBI != MBB.end() && MBBI->getOpcode() == ARM::VLDMDIA_UPD) in emitEpilogue()
1420 BuildMI(MBB, MBBI, DebugLoc(), STI.getInstrInfo()->get(ARM::t2AUT)); in emitEpilogue()
1425 BuildMI(MBB, MBB.end(), dl, TII.get(ARM::SEH_EpilogEnd)) in emitEpilogue()
1451 FrameReg = ARM::SP; in ResolveFrameIndexReference()
1546 if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs) in emitPushInst()
1575 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StmOpc), ARM::SP) in emitPushInst()
1576 .addReg(ARM::SP) in emitPushInst()
1582 BuildMI(MBB, MI, DL, TII.get(StrOpc), ARM::SP) in emitPushInst()
1584 .addReg(ARM::SP) in emitPushInst()
1620 (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNri || in emitPopInst()
1621 RetOpcode == ARM::TCRETURNrinotr12); in emitPopInst()
1623 RetOpcode == ARM::SUBS_PC_LR || RetOpcode == ARM::t2SUBS_PC_LR; in emitPopInst()
1625 RetOpcode == ARM::TRAP || RetOpcode == ARM::TRAPNaCl || in emitPopInst()
1626 RetOpcode == ARM::tTRAP; in emitPopInst()
1627 isCmseEntry = (RetOpcode == ARM::tBXNS || RetOpcode == ARM::tBXNS_RET); in emitPopInst()
1641 if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs) in emitPopInst()
1643 if (Reg == ARM::LR && !isTailCall && !isVarArg && !isInterrupt && in emitPopInst()
1647 Reg = ARM::PC; in emitPopInst()
1650 LdmOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_RET : ARM::LDMIA_RET; in emitPopInst()
1671 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(LdmOpc), ARM::SP) in emitPopInst()
1672 .addReg(ARM::SP) in emitPopInst()
1687 if (Regs[0] == ARM::PC) in emitPopInst()
1688 Regs[0] = ARM::LR; in emitPopInst()
1691 .addReg(ARM::SP, RegState::Define) in emitPopInst()
1692 .addReg(ARM::SP) in emitPopInst()
1696 if (LdrOpc == ARM::LDR_POST_REG || LdrOpc == ARM::LDR_POST_IMM) { in emitPopInst()
1730 unsigned DNum = I.getReg() - ARM::D8; in emitAlignedDPRCS2Spills()
1761 unsigned Opc = isThumb ? ARM::t2SUBri : ARM::SUBri; in emitAlignedDPRCS2Spills()
1762 BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4) in emitAlignedDPRCS2Spills()
1763 .addReg(ARM::SP) in emitAlignedDPRCS2Spills()
1774 emitAligningInstructions(MF, AFI, TII, MBB, MI, DL, ARM::R4, MaxAlign, true); in emitAlignedDPRCS2Spills()
1780 Opc = isThumb ? ARM::tMOVr : ARM::MOVr; in emitAlignedDPRCS2Spills()
1781 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(Opc), ARM::SP) in emitAlignedDPRCS2Spills()
1782 .addReg(ARM::R4) in emitAlignedDPRCS2Spills()
1789 unsigned NextReg = ARM::D8; in emitAlignedDPRCS2Spills()
1794 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Spills()
1795 &ARM::QQPRRegClass); in emitAlignedDPRCS2Spills()
1797 BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Qwb_fixed), ARM::R4) in emitAlignedDPRCS2Spills()
1798 .addReg(ARM::R4, RegState::Kill) in emitAlignedDPRCS2Spills()
1813 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Spills()
1814 &ARM::QQPRRegClass); in emitAlignedDPRCS2Spills()
1816 BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Q)) in emitAlignedDPRCS2Spills()
1817 .addReg(ARM::R4) in emitAlignedDPRCS2Spills()
1828 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Spills()
1829 &ARM::QPRRegClass); in emitAlignedDPRCS2Spills()
1831 BuildMI(MBB, MI, DL, TII.get(ARM::VST1q64)) in emitAlignedDPRCS2Spills()
1832 .addReg(ARM::R4) in emitAlignedDPRCS2Spills()
1844 BuildMI(MBB, MI, DL, TII.get(ARM::VSTRD)) in emitAlignedDPRCS2Spills()
1846 .addReg(ARM::R4) in emitAlignedDPRCS2Spills()
1852 std::prev(MI)->addRegisterKilled(ARM::R4, TRI); in emitAlignedDPRCS2Spills()
1879 assert(MI->killsRegister(ARM::R4, /*TRI=*/nullptr) && "Missed kill flag"); in skipAlignedDPRCS2Spills()
1901 if (I.getReg() == ARM::D8) { in emitAlignedDPRCS2Restores()
1914 unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri; in emitAlignedDPRCS2Restores()
1915 BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4) in emitAlignedDPRCS2Restores()
1922 unsigned NextReg = ARM::D8; in emitAlignedDPRCS2Restores()
1926 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Restores()
1927 &ARM::QQPRRegClass); in emitAlignedDPRCS2Restores()
1928 BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Qwb_fixed), NextReg) in emitAlignedDPRCS2Restores()
1929 .addReg(ARM::R4, RegState::Define) in emitAlignedDPRCS2Restores()
1930 .addReg(ARM::R4, RegState::Kill) in emitAlignedDPRCS2Restores()
1944 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Restores()
1945 &ARM::QQPRRegClass); in emitAlignedDPRCS2Restores()
1946 BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Q), NextReg) in emitAlignedDPRCS2Restores()
1947 .addReg(ARM::R4) in emitAlignedDPRCS2Restores()
1957 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Restores()
1958 &ARM::QPRRegClass); in emitAlignedDPRCS2Restores()
1959 BuildMI(MBB, MI, DL, TII.get(ARM::VLD1q64), SupReg) in emitAlignedDPRCS2Restores()
1960 .addReg(ARM::R4) in emitAlignedDPRCS2Restores()
1969 BuildMI(MBB, MI, DL, TII.get(ARM::VLDRD), NextReg) in emitAlignedDPRCS2Restores()
1970 .addReg(ARM::R4) in emitAlignedDPRCS2Restores()
1975 std::prev(MI)->addRegisterKilled(ARM::R4, TRI); in emitAlignedDPRCS2Restores()
1987 unsigned PushOpc = AFI->isThumbFunction() ? ARM::t2STMDB_UPD : ARM::STMDB_UPD; in spillCalleeSavedRegisters()
1989 ARM::t2STR_PRE : ARM::STR_PRE_IMM; in spillCalleeSavedRegisters()
1990 unsigned FltOpc = ARM::VSTMDDB_UPD; in spillCalleeSavedRegisters()
1994 BuildMI(MBB, MI, DebugLoc(), STI.getInstrInfo()->get(ARM::t2PAC)) in spillCalleeSavedRegisters()
1999 return C.getReg() == ARM::FPCXTNS; in spillCalleeSavedRegisters()
2001 BuildMI(MBB, MI, DebugLoc(), STI.getInstrInfo()->get(ARM::VSTR_FPCXTNS_pre), in spillCalleeSavedRegisters()
2002 ARM::SP) in spillCalleeSavedRegisters()
2003 .addReg(ARM::SP) in spillCalleeSavedRegisters()
2048 unsigned PopOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_UPD : ARM::LDMIA_UPD; in restoreCalleeSavedRegisters()
2050 AFI->isThumbFunction() ? ARM::t2LDR_POST : ARM::LDR_POST_IMM; in restoreCalleeSavedRegisters()
2051 unsigned FltOpc = ARM::VLDMDIA_UPD; in restoreCalleeSavedRegisters()
2108 if (MI.getOpcode() == ARM::ADDri) { in estimateRSStackSizeLimit()
2114 if (MI.getOpcode() == ARM::t2ADDri || MI.getOpcode() == ARM::t2ADDri12) in estimateRSStackSizeLimit()
2119 if (RegClass && !RegClass->contains(ARM::SP)) in estimateRSStackSizeLimit()
2204 if (!SavedRegs.test(ARM::D8 + NumSpills)) in checkNumAlignedDPRCS2Regs()
2215 SavedRegs.set(ARM::R4); in checkNumAlignedDPRCS2Regs()
2253 if (MI.getOpcode() == ARM::tSTRspi || MI.getOpcode() == ARM::tSTRi || in canSpillOnFrameIndexAccess()
2259 if (ARM::hGPRRegClass.contains(Reg) && Reg != ARM::SP) in canSpillOnFrameIndexAccess()
2298 SavedRegs.set(ARM::R4); in determineCalleeSaves()
2307 SavedRegs.set(ARM::R4); in determineCalleeSaves()
2308 SavedRegs.set(ARM::LR); in determineCalleeSaves()
2314 SavedRegs.set(ARM::LR); in determineCalleeSaves()
2324 SavedRegs.set(ARM::R4); in determineCalleeSaves()
2353 if (!ARM::GPRRegClass.contains(Reg)) { in determineCalleeSaves()
2355 if (ARM::SPRRegClass.contains(Reg)) in determineCalleeSaves()
2357 else if (ARM::DPRRegClass.contains(Reg)) in determineCalleeSaves()
2359 else if (ARM::QPRRegClass.contains(Reg)) in determineCalleeSaves()
2369 if (Reg == ARM::LR) in determineCalleeSaves()
2377 case ARM::LR: in determineCalleeSaves()
2380 case ARM::R0: case ARM::R1: in determineCalleeSaves()
2381 case ARM::R2: case ARM::R3: in determineCalleeSaves()
2382 case ARM::R4: case ARM::R5: in determineCalleeSaves()
2383 case ARM::R6: case ARM::R7: in determineCalleeSaves()
2396 case ARM::R0: case ARM::R1: in determineCalleeSaves()
2397 case ARM::R2: case ARM::R3: in determineCalleeSaves()
2398 case ARM::R4: case ARM::R5: in determineCalleeSaves()
2399 case ARM::R6: case ARM::R7: in determineCalleeSaves()
2400 case ARM::LR: in determineCalleeSaves()
2526 SavedRegs.set(ARM::LR); in determineCalleeSaves()
2529 auto LRPos = llvm::find(UnspilledCS1GPRs, ARM::LR); in determineCalleeSaves()
2537 if (FramePtr == ARM::R7) in determineCalleeSaves()
2571 for (unsigned Reg : {ARM::R0, ARM::R1, ARM::R2, ARM::R3}) { in determineCalleeSaves()
2592 for (unsigned Reg : {ARM::R4, ARM::R5, ARM::R6}) { in determineCalleeSaves()
2608 if (!HasFP || FramePtr != ARM::R7) { in determineCalleeSaves()
2609 if (SavedRegs.test(ARM::R7)) { in determineCalleeSaves()
2614 AvailableRegs.push_back(ARM::R7); in determineCalleeSaves()
2622 for (unsigned Reg : {ARM::R8, ARM::R9, ARM::R10, ARM::R11}) { in determineCalleeSaves()
2635 !(MF.getRegInfo().isLiveIn(ARM::LR) && in determineCalleeSaves()
2637 if (SavedRegs.test(ARM::LR)) { in determineCalleeSaves()
2642 AvailableRegs.push_back(ARM::LR); in determineCalleeSaves()
2661 if (Reg != ARM::LR && !MRI.isPhysRegUsed(Reg)) in determineCalleeSaves()
2664 if (Reg == ARM::LR) in determineCalleeSaves()
2678 SavedRegs.set(ARM::LR); in determineCalleeSaves()
2681 LRPos = llvm::find(UnspilledCS1GPRs, (unsigned)ARM::LR); in determineCalleeSaves()
2686 if (!MRI.isReserved(ARM::LR) && !MRI.isPhysRegUsed(ARM::LR) && in determineCalleeSaves()
2702 (STI.isTargetWindows() && Reg == ARM::R11) || in determineCalleeSaves()
2704 (Reg == ARM::LR && !ExpensiveLRRestore)) { in determineCalleeSaves()
2709 !(Reg == ARM::LR && AFI->isThumb1OnlyFunction())) in determineCalleeSaves()
2772 const TargetRegisterClass &RC = ARM::GPRRegClass; in determineCalleeSaves()
2783 SavedRegs.set(ARM::LR); in determineCalleeSaves()
2784 AFI->setLRIsSpilled(SavedRegs.test(ARM::LR)); in determineCalleeSaves()
2796 if (Info.getReg() != ARM::LR) in updateLRRestored()
2800 return !Term.isReturn() || Term.getOpcode() == ARM::LDMIA_RET || in updateLRRestored()
2801 Term.getOpcode() == ARM::t2LDMIA_RET || in updateLRRestored()
2802 Term.getOpcode() == ARM::tPOP_RET; in updateLRRestored()
2826 SavedRegs.set(ARM::R0); in getCalleeSaves()
2836 CSI.emplace_back(ARM::FPCXTNS); in assignCalleeSavedSpillSlots()
2853 return Reg == ARM::R10 || Reg == ARM::R11 || in assignCalleeSavedSpillSlots()
2854 Reg == ARM::R8 || Reg == ARM::R9 || in assignCalleeSavedSpillSlots()
2855 ARM::DPRRegClass.contains(Reg); in assignCalleeSavedSpillSlots()
2857 CalleeSavedInfo(ARM::R12)); in assignCalleeSavedSpillSlots()
2865 static const SpillSlot FixedSpillOffsets[] = {{ARM::FPCXTNS, -4}}; in getCalleeSavedSpillSlots()
2906 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) { in eliminateCallFramePseudoInstr()
2910 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP); in eliminateCallFramePseudoInstr()
3011 unsigned ScratchReg0 = ARM::R4; in adjustForSegmentedStacks()
3012 unsigned ScratchReg1 = ARM::R5; in adjustForSegmentedStacks()
3013 unsigned MovOp = ST->useMovt() ? ARM::t2MOVi32imm : ARM::tMOVi32imm; in adjustForSegmentedStacks()
3081 BuildMI(PrevStackMBB, DL, TII.get(ARM::tPUSH)) in adjustForSegmentedStacks()
3086 BuildMI(PrevStackMBB, DL, TII.get(ARM::STMDB_UPD)) in adjustForSegmentedStacks()
3087 .addReg(ARM::SP, RegState::Define) in adjustForSegmentedStacks()
3088 .addReg(ARM::SP) in adjustForSegmentedStacks()
3112 BuildMI(McrMBB, DL, TII.get(ARM::tMOVr), ScratchReg1) in adjustForSegmentedStacks()
3113 .addReg(ARM::SP) in adjustForSegmentedStacks()
3116 BuildMI(McrMBB, DL, TII.get(ARM::MOVr), ScratchReg1) in adjustForSegmentedStacks()
3117 .addReg(ARM::SP) in adjustForSegmentedStacks()
3125 BuildMI(McrMBB, DL, TII.get(ARM::tSUBi8), ScratchReg1) in adjustForSegmentedStacks()
3140 BuildMI(McrMBB, DL, TII.get(ARM::tSUBrr), ScratchReg1) in adjustForSegmentedStacks()
3148 BuildMI(McrMBB, DL, TII.get(ARM::SUBri), ScratchReg1) in adjustForSegmentedStacks()
3149 .addReg(ARM::SP) in adjustForSegmentedStacks()
3158 BuildMI(McrMBB, DL, TII.get(ARM::SUBrr), ScratchReg1) in adjustForSegmentedStacks()
3159 .addReg(ARM::SP) in adjustForSegmentedStacks()
3178 BuildMI(GetMBB, DL, TII.get(ARM::tLDRpci), ScratchReg0) in adjustForSegmentedStacks()
3184 BuildMI(GetMBB, DL, TII.get(ARM::tLDRi), ScratchReg0) in adjustForSegmentedStacks()
3191 BuildMI(McrMBB, DL, TII.get(Thumb ? ARM::t2MRC : ARM::MRC), in adjustForSegmentedStacks()
3206 BuildMI(GetMBB, DL, TII.get(Thumb ? ARM::t2LDRi12 : ARM::LDRi12), in adjustForSegmentedStacks()
3215 Opcode = Thumb ? ARM::tCMPr : ARM::CMPrr; in adjustForSegmentedStacks()
3222 Opcode = Thumb ? ARM::tBcc : ARM::Bcc; in adjustForSegmentedStacks()
3226 .addReg(ARM::CPSR); in adjustForSegmentedStacks()
3236 BuildMI(AllocMBB, DL, TII.get(ARM::tMOVi8), ScratchReg0) in adjustForSegmentedStacks()
3253 BuildMI(AllocMBB, DL, TII.get(ARM::MOVi), ScratchReg0) in adjustForSegmentedStacks()
3269 BuildMI(AllocMBB, DL, TII.get(ARM::tMOVi8), ScratchReg1) in adjustForSegmentedStacks()
3287 BuildMI(AllocMBB, DL, TII.get(ARM::MOVi), ScratchReg1) in adjustForSegmentedStacks()
3302 BuildMI(AllocMBB, DL, TII.get(ARM::tPUSH)) in adjustForSegmentedStacks()
3304 .addReg(ARM::LR); in adjustForSegmentedStacks()
3306 BuildMI(AllocMBB, DL, TII.get(ARM::STMDB_UPD)) in adjustForSegmentedStacks()
3307 .addReg(ARM::SP, RegState::Define) in adjustForSegmentedStacks()
3308 .addReg(ARM::SP) in adjustForSegmentedStacks()
3310 .addReg(ARM::LR); in adjustForSegmentedStacks()
3320 nullptr, MRI->getDwarfRegNum(ARM::LR, true), -12)); in adjustForSegmentedStacks()
3327 BuildMI(AllocMBB, DL, TII.get(ARM::tBL)) in adjustForSegmentedStacks()
3331 BuildMI(AllocMBB, DL, TII.get(ARM::BL)) in adjustForSegmentedStacks()
3338 BuildMI(AllocMBB, DL, TII.get(ARM::tPOP)) in adjustForSegmentedStacks()
3341 BuildMI(AllocMBB, DL, TII.get(ARM::tMOVr), ARM::LR) in adjustForSegmentedStacks()
3345 BuildMI(AllocMBB, DL, TII.get(ARM::t2LDR_POST)) in adjustForSegmentedStacks()
3346 .addReg(ARM::LR, RegState::Define) in adjustForSegmentedStacks()
3347 .addReg(ARM::SP, RegState::Define) in adjustForSegmentedStacks()
3348 .addReg(ARM::SP) in adjustForSegmentedStacks()
3353 BuildMI(AllocMBB, DL, TII.get(ARM::LDMIA_UPD)) in adjustForSegmentedStacks()
3354 .addReg(ARM::SP, RegState::Define) in adjustForSegmentedStacks()
3355 .addReg(ARM::SP) in adjustForSegmentedStacks()
3357 .addReg(ARM::LR); in adjustForSegmentedStacks()
3365 BuildMI(AllocMBB, DL, TII.get(ARM::tPOP)) in adjustForSegmentedStacks()
3370 BuildMI(AllocMBB, DL, TII.get(ARM::LDMIA_UPD)) in adjustForSegmentedStacks()
3371 .addReg(ARM::SP, RegState::Define) in adjustForSegmentedStacks()
3372 .addReg(ARM::SP) in adjustForSegmentedStacks()
3391 BuildMI(PostStackMBB, DL, TII.get(ARM::tPOP)) in adjustForSegmentedStacks()
3396 BuildMI(PostStackMBB, DL, TII.get(ARM::LDMIA_UPD)) in adjustForSegmentedStacks()
3397 .addReg(ARM::SP, RegState::Define) in adjustForSegmentedStacks()
3398 .addReg(ARM::SP) in adjustForSegmentedStacks()