Lines Matching refs:ARM
78 if (ScratchReg == ARM::NoRegister) in emitPrologueEpilogueSPUpdate()
83 unsigned XOInstr = ST.useMovt() ? ARM::t2MOVi32imm : ARM::tMOVi32imm; in emitPrologueEpilogueSPUpdate()
90 BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDhirr), ARM::SP) in emitPrologueEpilogueSPUpdate()
91 .addReg(ARM::SP) in emitPrologueEpilogueSPUpdate()
99 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII, in emitPrologueEpilogueSPUpdate()
109 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII, in emitCallSPUpdate()
136 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) { in eliminateCallFramePseudoInstr()
139 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP); in eliminateCallFramePseudoInstr()
183 ARM::NoRegister, MachineInstr::FrameSetup); in emitPrologue()
196 ARM::NoRegister, MachineInstr::FrameSetup); in emitPrologue()
207 bool HasFrameRecordArea = hasFP(MF) && ARM::hGPRRegClass.contains(FramePtr); in emitPrologue()
215 case ARM::R11: in emitPrologue()
221 case ARM::R8: in emitPrologue()
222 case ARM::R9: in emitPrologue()
223 case ARM::R10: in emitPrologue()
229 case ARM::LR: in emitPrologue()
235 case ARM::R4: in emitPrologue()
236 case ARM::R5: in emitPrologue()
237 case ARM::R6: in emitPrologue()
238 case ARM::R7: in emitPrologue()
256 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) { in emitPrologue()
266 while (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tMOVr && in emitPrologue()
269 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH && in emitPrologue()
315 BuildMI(MBB, AfterPush, dl, TII.get(ARM::tMOVr), FramePtr) in emitPrologue()
316 .addReg(ARM::SP) in emitPrologue()
322 BuildMI(MBB, AfterPush, dl, TII.get(ARM::tADDrSPi), FramePtr) in emitPrologue()
323 .addReg(ARM::SP) in emitPrologue()
363 case ARM::R8: in emitPrologue()
364 case ARM::R9: in emitPrologue()
365 case ARM::R10: in emitPrologue()
366 case ARM::R11: in emitPrologue()
367 case ARM::R12: in emitPrologue()
371 case ARM::R0: in emitPrologue()
372 case ARM::R1: in emitPrologue()
373 case ARM::R2: in emitPrologue()
374 case ARM::R3: in emitPrologue()
375 case ARM::R4: in emitPrologue()
376 case ARM::R5: in emitPrologue()
377 case ARM::R6: in emitPrologue()
378 case ARM::R7: in emitPrologue()
379 case ARM::LR: in emitPrologue()
397 case ARM::R8: in emitPrologue()
398 case ARM::R9: in emitPrologue()
399 case ARM::R10: in emitPrologue()
400 case ARM::R11: in emitPrologue()
401 case ARM::R12: { in emitPrologue()
421 unsigned ScratchRegister = ARM::NoRegister; in emitPrologue()
457 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4) in emitPrologue()
458 .addReg(ARM::SP, RegState::Kill) in emitPrologue()
461 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLSRri), ARM::R4) in emitPrologue()
462 .addDef(ARM::CPSR) in emitPrologue()
463 .addReg(ARM::R4, RegState::Kill) in emitPrologue()
467 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLSLri), ARM::R4) in emitPrologue()
468 .addDef(ARM::CPSR) in emitPrologue()
469 .addReg(ARM::R4, RegState::Kill) in emitPrologue()
473 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP) in emitPrologue()
474 .addReg(ARM::R4, RegState::Kill) in emitPrologue()
485 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), BasePtr) in emitPrologue()
486 .addReg(ARM::SP) in emitPrologue()
520 NumBytes - ArgRegsSaveSize, ARM::NoRegister, in emitEpilogue()
541 unsigned ScratchRegister = ARM::NoRegister; in emitEpilogue()
557 assert(ScratchRegister != ARM::NoRegister && in emitEpilogue()
561 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP) in emitEpilogue()
566 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP) in emitEpilogue()
571 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tBX_RET && in emitEpilogue()
572 &MBB.front() != &*MBBI && std::prev(MBBI)->getOpcode() == ARM::tPOP) { in emitEpilogue()
606 if (CSI.getReg() == ARM::LR) in needPopSpecialFixUp()
651 if (MBBI != MBB.end() && MBBI->getOpcode() != ARM::tB) in emitPopSpecialFixUp()
652 CanRestoreDirectly = (MBBI->getOpcode() == ARM::tBX_RET || in emitPopSpecialFixUp()
653 MBBI->getOpcode() == ARM::tPOP_RET); in emitPopSpecialFixUp()
657 assert(MBBI_prev->getOpcode() == ARM::tPOP); in emitPopSpecialFixUp()
659 if ((*MBB.succ_begin())->begin()->getOpcode() == ARM::tBX_RET) in emitPopSpecialFixUp()
667 if (!DoIt || MBBI->getOpcode() == ARM::tPOP_RET) in emitPopSpecialFixUp()
670 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII.get(ARM::tPOP_RET)) in emitPopSpecialFixUp()
677 MIB.addReg(ARM::PC, RegState::Define); in emitPopSpecialFixUp()
711 TRI.getAllocatableSet(MF, TRI.getRegClass(ARM::tGPRRegClassID)); in emitPopSpecialFixUp()
717 TRI.getAllocatableSet(MF, TRI.getRegClass(ARM::hGPRRegClassID)); in emitPopSpecialFixUp()
719 GPRsNoLRSP.reset(ARM::LR); in emitPopSpecialFixUp()
720 GPRsNoLRSP.reset(ARM::SP); in emitPopSpecialFixUp()
721 GPRsNoLRSP.reset(ARM::PC); in emitPopSpecialFixUp()
732 if (PrevMBBI->getOpcode() == ARM::tPOP) { in emitPopSpecialFixUp()
751 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRspi)) in emitPopSpecialFixUp()
753 .addReg(ARM::SP) in emitPopSpecialFixUp()
758 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr)) in emitPopSpecialFixUp()
759 .addReg(ARM::LR, RegState::Define) in emitPopSpecialFixUp()
767 ArgRegsSaveSize + 4, ARM::NoRegister, in emitPopSpecialFixUp()
775 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr)) in emitPopSpecialFixUp()
782 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPOP_RET) { in emitPopSpecialFixUp()
786 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII.get(ARM::tPOP)) in emitPopSpecialFixUp()
792 MO.getReg() != ARM::PC) { in emitPopSpecialFixUp()
802 MBBI = BuildMI(MBB, MBB.end(), dl, TII.get(ARM::tBX_RET)) in emitPopSpecialFixUp()
808 BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)) in emitPopSpecialFixUp()
814 ARM::NoRegister, MachineInstr::FrameDestroy); in emitPopSpecialFixUp()
816 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr)) in emitPopSpecialFixUp()
817 .addReg(ARM::LR, RegState::Define) in emitPopSpecialFixUp()
823 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr)) in emitPopSpecialFixUp()
832 static const SmallVector<Register> OrderedLowRegs = {ARM::R4, ARM::R5, ARM::R6,
833 ARM::R7, ARM::LR};
834 static const SmallVector<Register> OrderedHighRegs = {ARM::R8, ARM::R9,
835 ARM::R10, ARM::R11};
837 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4,
838 ARM::R5, ARM::R6, ARM::R7, ARM::LR};
844 if (ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) { in splitLowAndHighRegs()
846 } else if (ARM::hGPRRegClass.contains(Reg) && Reg != ARM::LR) { in splitLowAndHighRegs()
876 BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH)).add(predOps(ARMCC::AL)); in pushRegsToStack()
911 MachineInstrBuilder PushMIB = BuildMI(MF, DL, TII.get(ARM::tPUSH)) in pushRegsToStack()
924 BuildMI(MBB, MI, DL, TII.get(ARM::tMOVr)) in pushRegsToStack()
983 LowScratchReg = ARM::R0; in popRegsFromStack()
984 BuildMI(MBB, MI, DL, TII.get(ARM::tMOVr)) in popRegsFromStack()
985 .addReg(ARM::R12, RegState::Define) in popRegsFromStack()
1000 MachineInstrBuilder PopMIB = BuildMI(MBB, MI, DL, TII.get(ARM::tPOP)) in popRegsFromStack()
1010 BuildMI(MBB, MI, DL, TII.get(ARM::tMOVr)) in popRegsFromStack()
1027 BuildMI(MBB, MI, DL, TII.get(ARM::tMOVr)) in popRegsFromStack()
1029 .addReg(ARM::R12, RegState::Kill) in popRegsFromStack()
1036 MachineInstrBuilder MIB = BuildMI(MF, DL, TII.get(ARM::tPOP)) in popRegsFromStack()
1045 if (Reg == ARM::LR) { in popRegsFromStack()
1046 if (!MBB.succ_empty() || MI->getOpcode() == ARM::TCRETURNdi || in popRegsFromStack()
1047 MI->getOpcode() == ARM::TCRETURNri || in popRegsFromStack()
1048 MI->getOpcode() == ARM::TCRETURNrinotr12) in popRegsFromStack()
1068 Reg = ARM::PC; in popRegsFromStack()
1069 (*MIB).setDesc(TII.get(ARM::tPOP_RET)); in popRegsFromStack()
1100 bool NeedsFrameRecordPush = hasFP(MF) && ARM::hGPRRegClass.contains(FPReg); in spillCalleeSavedRegisters()
1106 if (NeedsFrameRecordPush && (Reg == FPReg || Reg == ARM::LR)) in spillCalleeSavedRegisters()
1112 pushRegsToStack(MBB, MI, TII, FrameRecord, {ARM::LR}); in spillCalleeSavedRegisters()
1119 if ((ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) && in spillCalleeSavedRegisters()
1122 for (unsigned ArgReg : {ARM::R0, ARM::R1, ARM::R2, ARM::R3}) in spillCalleeSavedRegisters()
1147 bool NeedsFrameRecordPop = hasFP(MF) && ARM::hGPRRegClass.contains(FPReg); in restoreCalleeSavedRegisters()
1153 if (NeedsFrameRecordPop && (Reg == FPReg || Reg == ARM::LR)) in restoreCalleeSavedRegisters()
1158 if (Reg == ARM::LR) in restoreCalleeSavedRegisters()
1168 if ((ARM::tGPRRegClass.contains(Reg)) && !(hasFP(MF) && Reg == FPReg)) in restoreCalleeSavedRegisters()
1171 if (Terminator != MBB.end() && Terminator->getOpcode() == ARM::tBX_RET) { in restoreCalleeSavedRegisters()
1172 UnusedReturnRegs.insert(ARM::R0); in restoreCalleeSavedRegisters()
1173 UnusedReturnRegs.insert(ARM::R1); in restoreCalleeSavedRegisters()
1174 UnusedReturnRegs.insert(ARM::R2); in restoreCalleeSavedRegisters()
1175 UnusedReturnRegs.insert(ARM::R3); in restoreCalleeSavedRegisters()
1189 assert((!SpilledGPRs.count(ARM::LR) || FrameRecord.empty()) && in restoreCalleeSavedRegisters()