Lines Matching refs:ARM
181 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tBX) in runOnMachineFunction()
225 if(ARM::GPRPairRegClass.contains(Reg)) { in printOperand()
228 Reg = TRI->getSubReg(Reg, ARM::gsub_0); in printOperand()
307 if (!ARM::DPRRegClass.contains(SR)) in PrintAsmOperand()
309 bool Lane0 = TRI->getSubReg(SR, ARM::ssub_0) == Reg; in PrintAsmOperand()
334 if (ARM::GPRPairRegClass.contains(RegBegin)) { in PrintAsmOperand()
336 Register Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0); in PrintAsmOperand()
338 RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1); in PrintAsmOperand()
399 ARM::GPRPairRegClass.hasSubClassEq(TRI->getRegClass(RC))) { in PrintAsmOperand()
407 TRI->getSubReg(MO.getReg(), FirstHalf ? ARM::gsub_0 : ARM::gsub_1); in PrintAsmOperand()
429 if (!ARM::QPRRegClass.contains(Reg)) in PrintAsmOperand()
433 TRI->getSubReg(Reg, ExtraCode[0] == 'e' ? ARM::dsub_0 : ARM::dsub_1); in PrintAsmOperand()
448 if(!ARM::GPRPairRegClass.contains(Reg)) in PrintAsmOperand()
450 Reg = TRI->getSubReg(Reg, ARM::gsub_1); in PrintAsmOperand()
486 return STI.hasFeature(ARM::ModeThumb); in isThumb()
1061 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2B) in emitJumpTableInsts()
1130 case ARM::BR_JTadd: in getCodeViewJumpTableInfo()
1131 case ARM::BR_JTr: in getCodeViewJumpTableInfo()
1132 case ARM::tBR_JTr: in getCodeViewJumpTableInfo()
1137 case ARM::tTBH_JT: in getCodeViewJumpTableInfo()
1138 case ARM::t2TBH_JT: in getCodeViewJumpTableInfo()
1145 case ARM::tTBB_JT: in getCodeViewJumpTableInfo()
1146 case ARM::t2TBB_JT: in getCodeViewJumpTableInfo()
1153 case ARM::t2BR_JT: in getCodeViewJumpTableInfo()
1181 case ARM::tPUSH: in EmitUnwindingInstruction()
1183 SrcReg = DstReg = ARM::SP; in EmitUnwindingInstruction()
1185 case ARM::tLDRpci: in EmitUnwindingInstruction()
1186 case ARM::t2MOVi16: in EmitUnwindingInstruction()
1187 case ARM::t2MOVTi16: in EmitUnwindingInstruction()
1188 case ARM::tMOVi8: in EmitUnwindingInstruction()
1189 case ARM::tADDi8: in EmitUnwindingInstruction()
1190 case ARM::tLSLri: in EmitUnwindingInstruction()
1219 assert(DstReg == ARM::SP && in EmitUnwindingInstruction()
1238 case ARM::tPUSH: in EmitUnwindingInstruction()
1242 case ARM::STMDB_UPD: in EmitUnwindingInstruction()
1243 case ARM::t2STMDB_UPD: in EmitUnwindingInstruction()
1244 case ARM::VSTMDDB_UPD: in EmitUnwindingInstruction()
1245 assert(SrcReg == ARM::SP && in EmitUnwindingInstruction()
1274 case ARM::STR_PRE_IMM: in EmitUnwindingInstruction()
1275 case ARM::STR_PRE_REG: in EmitUnwindingInstruction()
1276 case ARM::t2STR_PRE: in EmitUnwindingInstruction()
1277 assert(MI->getOperand(2).getReg() == ARM::SP && in EmitUnwindingInstruction()
1284 case ARM::t2STRD_PRE: in EmitUnwindingInstruction()
1285 assert(MI->getOperand(3).getReg() == ARM::SP && in EmitUnwindingInstruction()
1298 if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM) { in EmitUnwindingInstruction()
1301 ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD); in EmitUnwindingInstruction()
1308 if (SrcReg == ARM::SP) { in EmitUnwindingInstruction()
1314 case ARM::MOVr: in EmitUnwindingInstruction()
1315 case ARM::tMOVr: in EmitUnwindingInstruction()
1318 case ARM::ADDri: in EmitUnwindingInstruction()
1319 case ARM::t2ADDri: in EmitUnwindingInstruction()
1320 case ARM::t2ADDri12: in EmitUnwindingInstruction()
1321 case ARM::t2ADDspImm: in EmitUnwindingInstruction()
1322 case ARM::t2ADDspImm12: in EmitUnwindingInstruction()
1325 case ARM::SUBri: in EmitUnwindingInstruction()
1326 case ARM::t2SUBri: in EmitUnwindingInstruction()
1327 case ARM::t2SUBri12: in EmitUnwindingInstruction()
1328 case ARM::t2SUBspImm: in EmitUnwindingInstruction()
1329 case ARM::t2SUBspImm12: in EmitUnwindingInstruction()
1332 case ARM::tSUBspi: in EmitUnwindingInstruction()
1335 case ARM::tADDspi: in EmitUnwindingInstruction()
1336 case ARM::tADDrSPi: in EmitUnwindingInstruction()
1339 case ARM::tADDhirr: in EmitUnwindingInstruction()
1345 if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM) { in EmitUnwindingInstruction()
1346 if (DstReg == FramePtr && FramePtr != ARM::SP) in EmitUnwindingInstruction()
1349 ATS.emitSetFP(FramePtr, ARM::SP, -Offset); in EmitUnwindingInstruction()
1350 else if (DstReg == ARM::SP) { in EmitUnwindingInstruction()
1360 } else if (DstReg == ARM::SP) { in EmitUnwindingInstruction()
1366 case ARM::tMOVr: in EmitUnwindingInstruction()
1372 case ARM::tLDRpci: { in EmitUnwindingInstruction()
1388 case ARM::t2MOVi16: in EmitUnwindingInstruction()
1392 case ARM::t2MOVTi16: in EmitUnwindingInstruction()
1396 case ARM::tMOVi8: in EmitUnwindingInstruction()
1400 case ARM::tLSLri: in EmitUnwindingInstruction()
1407 case ARM::tADDi8: in EmitUnwindingInstruction()
1413 case ARM::t2PAC: in EmitUnwindingInstruction()
1414 case ARM::t2PACBTI: in EmitUnwindingInstruction()
1415 AFI->EHPrologueRemappedRegs[ARM::R12] = ARM::RA_AUTH_CODE; in EmitUnwindingInstruction()
1439 if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) { in emitInstruction()
1459 case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass"); in emitInstruction()
1460 case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing"); in emitInstruction()
1461 case ARM::LEApcrel: in emitInstruction()
1462 case ARM::tLEApcrel: in emitInstruction()
1463 case ARM::t2LEApcrel: { in emitInstruction()
1467 ARM::t2LEApcrel ? ARM::t2ADR in emitInstruction()
1468 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR in emitInstruction()
1469 : ARM::ADR)) in emitInstruction()
1477 case ARM::LEApcrelJT: in emitInstruction()
1478 case ARM::tLEApcrelJT: in emitInstruction()
1479 case ARM::t2LEApcrelJT: { in emitInstruction()
1483 ARM::t2LEApcrelJT ? ARM::t2ADR in emitInstruction()
1484 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR in emitInstruction()
1485 : ARM::ADR)) in emitInstruction()
1495 case ARM::BX_CALL: { in emitInstruction()
1496 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr) in emitInstruction()
1497 .addReg(ARM::LR) in emitInstruction()
1498 .addReg(ARM::PC) in emitInstruction()
1506 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::BX) in emitInstruction()
1510 case ARM::tBX_CALL: { in emitInstruction()
1535 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tBL) in emitInstruction()
1541 case ARM::BMOVPCRX_CALL: { in emitInstruction()
1542 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr) in emitInstruction()
1543 .addReg(ARM::LR) in emitInstruction()
1544 .addReg(ARM::PC) in emitInstruction()
1551 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr) in emitInstruction()
1552 .addReg(ARM::PC) in emitInstruction()
1561 case ARM::BMOVPCB_CALL: { in emitInstruction()
1562 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr) in emitInstruction()
1563 .addReg(ARM::LR) in emitInstruction()
1564 .addReg(ARM::PC) in emitInstruction()
1576 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::Bcc) in emitInstruction()
1583 case ARM::MOVi16_ga_pcrel: in emitInstruction()
1584 case ARM::t2MOVi16_ga_pcrel: { in emitInstruction()
1586 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16); in emitInstruction()
1598 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4; in emitInstruction()
1614 case ARM::MOVTi16_ga_pcrel: in emitInstruction()
1615 case ARM::t2MOVTi16_ga_pcrel: { in emitInstruction()
1617 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel in emitInstruction()
1618 ? ARM::MOVTi16 : ARM::t2MOVTi16); in emitInstruction()
1631 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4; in emitInstruction()
1646 case ARM::t2BFi: in emitInstruction()
1647 case ARM::t2BFic: in emitInstruction()
1648 case ARM::t2BFLi: in emitInstruction()
1649 case ARM::t2BFr: in emitInstruction()
1650 case ARM::t2BFLr: { in emitInstruction()
1682 if (Opc == ARM::t2BFic) { in emitInstruction()
1697 case ARM::t2BF_LabelPseudo: { in emitInstruction()
1706 case ARM::tPICADD: { in emitInstruction()
1718 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr) in emitInstruction()
1721 .addReg(ARM::PC) in emitInstruction()
1727 case ARM::PICADD: { in emitInstruction()
1739 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDrr) in emitInstruction()
1741 .addReg(ARM::PC) in emitInstruction()
1750 case ARM::PICSTR: in emitInstruction()
1751 case ARM::PICSTRB: in emitInstruction()
1752 case ARM::PICSTRH: in emitInstruction()
1753 case ARM::PICLDR: in emitInstruction()
1754 case ARM::PICLDRB: in emitInstruction()
1755 case ARM::PICLDRH: in emitInstruction()
1756 case ARM::PICLDRSB: in emitInstruction()
1757 case ARM::PICLDRSH: { in emitInstruction()
1774 case ARM::PICSTR: Opcode = ARM::STRrs; break; in emitInstruction()
1775 case ARM::PICSTRB: Opcode = ARM::STRBrs; break; in emitInstruction()
1776 case ARM::PICSTRH: Opcode = ARM::STRH; break; in emitInstruction()
1777 case ARM::PICLDR: Opcode = ARM::LDRrs; break; in emitInstruction()
1778 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break; in emitInstruction()
1779 case ARM::PICLDRH: Opcode = ARM::LDRH; break; in emitInstruction()
1780 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break; in emitInstruction()
1781 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break; in emitInstruction()
1785 .addReg(ARM::PC) in emitInstruction()
1794 case ARM::CONSTPOOL_ENTRY: { in emitInstruction()
1821 case ARM::JUMPTABLE_ADDRS: in emitInstruction()
1824 case ARM::JUMPTABLE_INSTS: in emitInstruction()
1827 case ARM::JUMPTABLE_TBB: in emitInstruction()
1828 case ARM::JUMPTABLE_TBH: in emitInstruction()
1829 emitJumpTableTBInst(MI, MI->getOpcode() == ARM::JUMPTABLE_TBB ? 1 : 2); in emitInstruction()
1831 case ARM::t2BR_JT: { in emitInstruction()
1832 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVr) in emitInstruction()
1833 .addReg(ARM::PC) in emitInstruction()
1840 case ARM::t2TBB_JT: in emitInstruction()
1841 case ARM::t2TBH_JT: { in emitInstruction()
1842 unsigned Opc = MI->getOpcode() == ARM::t2TBB_JT ? ARM::t2TBB : ARM::t2TBH; in emitInstruction()
1853 case ARM::tTBB_JT: in emitInstruction()
1854 case ARM::tTBH_JT: { in emitInstruction()
1856 bool Is8Bit = MI->getOpcode() == ARM::tTBB_JT; in emitInstruction()
1863 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLSLri) in emitInstruction()
1865 .addReg(ARM::CPSR) in emitInstruction()
1872 if (Base == ARM::PC) { in emitInstruction()
1887 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr) in emitInstruction()
1895 unsigned Opc = Is8Bit ? ARM::tLDRBi : ARM::tLDRHi; in emitInstruction()
1909 unsigned Opc = Is8Bit ? ARM::tLDRBr : ARM::tLDRHr; in emitInstruction()
1919 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLSLri) in emitInstruction()
1921 .addReg(ARM::CPSR) in emitInstruction()
1929 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr) in emitInstruction()
1930 .addReg(ARM::PC) in emitInstruction()
1931 .addReg(ARM::PC) in emitInstruction()
1938 case ARM::tBR_JTr: in emitInstruction()
1939 case ARM::BR_JTr: { in emitInstruction()
1942 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ? in emitInstruction()
1943 ARM::MOVr : ARM::tMOVr; in emitInstruction()
1945 TmpInst.addOperand(MCOperand::createReg(ARM::PC)); in emitInstruction()
1951 if (Opc == ARM::MOVr) in emitInstruction()
1956 case ARM::BR_JTm_i12: { in emitInstruction()
1959 TmpInst.setOpcode(ARM::LDRi12); in emitInstruction()
1960 TmpInst.addOperand(MCOperand::createReg(ARM::PC)); in emitInstruction()
1969 case ARM::BR_JTm_rs: { in emitInstruction()
1972 TmpInst.setOpcode(ARM::LDRrs); in emitInstruction()
1973 TmpInst.addOperand(MCOperand::createReg(ARM::PC)); in emitInstruction()
1983 case ARM::BR_JTadd: { in emitInstruction()
1985 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDrr) in emitInstruction()
1986 .addReg(ARM::PC) in emitInstruction()
1996 case ARM::SPACE: in emitInstruction()
1999 case ARM::TRAP: { in emitInstruction()
2010 case ARM::TRAPNaCl: { in emitInstruction()
2016 case ARM::tTRAP: { in emitInstruction()
2027 case ARM::t2Int_eh_sjlj_setjmp: in emitInstruction()
2028 case ARM::t2Int_eh_sjlj_setjmp_nofp: in emitInstruction()
2029 case ARM::tInt_eh_sjlj_setjmp: { in emitInstruction()
2042 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVr) in emitInstruction()
2044 .addReg(ARM::PC) in emitInstruction()
2049 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDi3) in emitInstruction()
2052 .addReg(ARM::CPSR) in emitInstruction()
2059 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tSTRi) in emitInstruction()
2069 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVi8) in emitInstruction()
2070 .addReg(ARM::R0) in emitInstruction()
2071 .addReg(ARM::CPSR) in emitInstruction()
2078 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tB) in emitInstruction()
2084 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVi8) in emitInstruction()
2085 .addReg(ARM::R0) in emitInstruction()
2086 .addReg(ARM::CPSR) in emitInstruction()
2096 case ARM::Int_eh_sjlj_setjmp_nofp: in emitInstruction()
2097 case ARM::Int_eh_sjlj_setjmp: { in emitInstruction()
2108 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDri) in emitInstruction()
2110 .addReg(ARM::PC) in emitInstruction()
2118 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::STRi12) in emitInstruction()
2126 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVi) in emitInstruction()
2127 .addReg(ARM::R0) in emitInstruction()
2135 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDri) in emitInstruction()
2136 .addReg(ARM::PC) in emitInstruction()
2137 .addReg(ARM::PC) in emitInstruction()
2146 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVi) in emitInstruction()
2147 .addReg(ARM::R0) in emitInstruction()
2156 case ARM::Int_eh_sjlj_longjmp: { in emitInstruction()
2163 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12) in emitInstruction()
2164 .addReg(ARM::SP) in emitInstruction()
2171 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12) in emitInstruction()
2184 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12) in emitInstruction()
2194 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12) in emitInstruction()
2195 .addReg(ARM::R7) in emitInstruction()
2201 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12) in emitInstruction()
2202 .addReg(ARM::R11) in emitInstruction()
2211 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::BX) in emitInstruction()
2218 case ARM::tInt_eh_sjlj_longjmp: { in emitInstruction()
2230 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi) in emitInstruction()
2240 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVr) in emitInstruction()
2241 .addReg(ARM::SP) in emitInstruction()
2247 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi) in emitInstruction()
2257 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi) in emitInstruction()
2267 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi) in emitInstruction()
2268 .addReg(ARM::R7) in emitInstruction()
2274 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi) in emitInstruction()
2275 .addReg(ARM::R11) in emitInstruction()
2283 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tBX) in emitInstruction()
2290 case ARM::tInt_WIN_eh_sjlj_longjmp: { in emitInstruction()
2297 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2LDRi12) in emitInstruction()
2298 .addReg(ARM::R11) in emitInstruction()
2304 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2LDRi12) in emitInstruction()
2305 .addReg(ARM::SP) in emitInstruction()
2311 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2LDRi12) in emitInstruction()
2312 .addReg(ARM::PC) in emitInstruction()
2320 case ARM::PATCHABLE_FUNCTION_ENTER: in emitInstruction()
2323 case ARM::PATCHABLE_FUNCTION_EXIT: in emitInstruction()
2326 case ARM::PATCHABLE_TAIL_CALL: in emitInstruction()
2329 case ARM::SpeculationBarrierISBDSBEndBB: { in emitInstruction()
2332 TmpInstDSB.setOpcode(ARM::DSB); in emitInstruction()
2336 TmpInstISB.setOpcode(ARM::ISB); in emitInstruction()
2341 case ARM::t2SpeculationBarrierISBDSBEndBB: { in emitInstruction()
2344 TmpInstDSB.setOpcode(ARM::t2DSB); in emitInstruction()
2350 TmpInstISB.setOpcode(ARM::t2ISB); in emitInstruction()
2357 case ARM::SpeculationBarrierSBEndBB: { in emitInstruction()
2360 TmpInstSB.setOpcode(ARM::SB); in emitInstruction()
2364 case ARM::t2SpeculationBarrierSBEndBB: { in emitInstruction()
2367 TmpInstSB.setOpcode(ARM::t2SB); in emitInstruction()
2372 case ARM::SEH_StackAlloc: in emitInstruction()
2377 case ARM::SEH_SaveRegs: in emitInstruction()
2378 case ARM::SEH_SaveRegs_Ret: in emitInstruction()
2383 case ARM::SEH_SaveSP: in emitInstruction()
2387 case ARM::SEH_SaveFRegs: in emitInstruction()
2392 case ARM::SEH_SaveLR: in emitInstruction()
2396 case ARM::SEH_Nop: in emitInstruction()
2397 case ARM::SEH_Nop_Ret: in emitInstruction()
2401 case ARM::SEH_PrologEnd: in emitInstruction()
2405 case ARM::SEH_EpilogStart: in emitInstruction()
2409 case ARM::SEH_EpilogEnd: in emitInstruction()
2413 case ARM::PseudoARMInitUndefMQPR: in emitInstruction()
2414 case ARM::PseudoARMInitUndefSPR: in emitInstruction()
2415 case ARM::PseudoARMInitUndefDPR_VFP2: in emitInstruction()
2416 case ARM::PseudoARMInitUndefGPR: in emitInstruction()