Lines Matching refs:ARM
138 InstructionEndianness = STI.hasFeature(ARM::ModeBigEndianInstructions) in ARMDisassembler()
721 case ARM::HVC: { in checkDecodedInstruction()
731 case ARM::t2ADDri: in checkDecodedInstruction()
732 case ARM::t2ADDri12: in checkDecodedInstruction()
733 case ARM::t2ADDrr: in checkDecodedInstruction()
734 case ARM::t2ADDrs: in checkDecodedInstruction()
735 case ARM::t2SUBri: in checkDecodedInstruction()
736 case ARM::t2SUBri12: in checkDecodedInstruction()
737 case ARM::t2SUBrr: in checkDecodedInstruction()
738 case ARM::t2SUBrs: in checkDecodedInstruction()
739 if (MI.getOperand(0).getReg() == ARM::SP && in checkDecodedInstruction()
740 MI.getOperand(1).getReg() != ARM::SP) in checkDecodedInstruction()
752 if (!STI.hasFeature(ARM::ModeThumb)) in suggestBytesToSkip()
779 if (STI.hasFeature(ARM::ModeThumb)) in getInstruction()
790 assert(!STI.hasFeature(ARM::ModeThumb) && in getARMInstruction()
894 MCID.operands()[i].RegClass == ARM::CCRRegClassID) { in AddThumb1SBit()
897 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); in AddThumb1SBit()
902 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); in AddThumb1SBit()
908 if (ARM::isVpred(MCID.operands()[i].OperandType)) in isVectorPredicable()
927 case ARM::tBcc: in AddThumbPredicate()
928 case ARM::t2Bcc: in AddThumbPredicate()
929 case ARM::tCBZ: in AddThumbPredicate()
930 case ARM::tCBNZ: in AddThumbPredicate()
931 case ARM::tCPS: in AddThumbPredicate()
932 case ARM::t2CPS3p: in AddThumbPredicate()
933 case ARM::t2CPS2p: in AddThumbPredicate()
934 case ARM::t2CPS1p: in AddThumbPredicate()
935 case ARM::t2CSEL: in AddThumbPredicate()
936 case ARM::t2CSINC: in AddThumbPredicate()
937 case ARM::t2CSINV: in AddThumbPredicate()
938 case ARM::t2CSNEG: in AddThumbPredicate()
939 case ARM::tMOVSr: in AddThumbPredicate()
940 case ARM::tSETEND: in AddThumbPredicate()
948 case ARM::t2HINT: in AddThumbPredicate()
949 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0) in AddThumbPredicate()
952 case ARM::tB: in AddThumbPredicate()
953 case ARM::t2B: in AddThumbPredicate()
954 case ARM::t2TBB: in AddThumbPredicate()
955 case ARM::t2TBH: in AddThumbPredicate()
997 MI.insert(CCI, MCOperand::createReg(ARM::CPSR)); in AddThumbPredicate()
1005 if (ARM::isVpred(MCID.operands()[VCCPos].OperandType) || VCCI == MI.end()) in AddThumbPredicate()
1015 VCCI = MI.insert(VCCI, MCOperand::createReg(ARM::P0)); in AddThumbPredicate()
1019 if (MCID.operands()[VCCPos].OperandType == ARM::OPERAND_VPRED_R) { in AddThumbPredicate()
1064 I->setReg(ARM::CPSR); in UpdateThumbVFPPredicate()
1076 assert(STI.hasFeature(ARM::ModeThumb) && in getThumbInstruction()
1112 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) in getThumbInstruction()
1120 if (MI.getOpcode() == ARM::t2IT) { in getThumbInstruction()
1256 const uint8_t *DecoderTable = ARM::isCDECoproc(Coproc, STI) in getThumbInstruction()
1283 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
1284 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
1285 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1286 ARM::R12, ARM::SP, ARM::LR, ARM::PC
1290 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
1291 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
1292 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1293 ARM::R12, 0, ARM::LR, ARM::APSR
1354 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); in DecodeGPRwithAPSRRegisterClass()
1369 Inst.addOperand(MCOperand::createReg(ARM::ZR)); in DecodeGPRwithZRRegisterClass()
1399 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
1400 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
1452 Register = ARM::R0; in DecodetcGPRRegisterClass()
1455 Register = ARM::R1; in DecodetcGPRRegisterClass()
1458 Register = ARM::R2; in DecodetcGPRRegisterClass()
1461 Register = ARM::R3; in DecodetcGPRRegisterClass()
1464 Register = ARM::R9; in DecodetcGPRRegisterClass()
1467 Register = ARM::R12; in DecodetcGPRRegisterClass()
1485 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15) in DecoderGPRRegisterClass()
1493 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
1494 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
1495 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
1496 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
1497 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
1498 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
1499 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
1500 ARM::S28, ARM::S29, ARM::S30, ARM::S31
1521 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
1522 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1523 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
1524 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
1525 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
1526 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
1527 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
1528 ARM::D28, ARM::D29, ARM::D30, ARM::D31
1537 bool hasD32 = featureBits[ARM::FeatureD32]; in DecodeDPRRegisterClass()
1572 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1573 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1574 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
1575 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1591 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1592 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1593 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1594 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1595 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1596 ARM::Q15
1611 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1612 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1613 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1614 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1615 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1616 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1617 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1618 ARM::D28_D30, ARM::D29_D31
1638 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) in DecodePredicateOperand()
1648 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); in DecodePredicateOperand()
1656 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); in DecodeCCOutOperand()
1747 case ARM::LDMIA_UPD: in DecodeRegListOperand()
1748 case ARM::LDMDB_UPD: in DecodeRegListOperand()
1749 case ARM::LDMIB_UPD: in DecodeRegListOperand()
1750 case ARM::LDMDA_UPD: in DecodeRegListOperand()
1751 case ARM::t2LDMIA_UPD: in DecodeRegListOperand()
1752 case ARM::t2LDMDB_UPD: in DecodeRegListOperand()
1753 case ARM::t2STMIA_UPD: in DecodeRegListOperand()
1754 case ARM::t2STMDB_UPD: in DecodeRegListOperand()
1758 case ARM::t2CLRM: in DecodeRegListOperand()
1878 case ARM::LDC_OFFSET: in DecodeCopMemInstruction()
1879 case ARM::LDC_PRE: in DecodeCopMemInstruction()
1880 case ARM::LDC_POST: in DecodeCopMemInstruction()
1881 case ARM::LDC_OPTION: in DecodeCopMemInstruction()
1882 case ARM::LDCL_OFFSET: in DecodeCopMemInstruction()
1883 case ARM::LDCL_PRE: in DecodeCopMemInstruction()
1884 case ARM::LDCL_POST: in DecodeCopMemInstruction()
1885 case ARM::LDCL_OPTION: in DecodeCopMemInstruction()
1886 case ARM::STC_OFFSET: in DecodeCopMemInstruction()
1887 case ARM::STC_PRE: in DecodeCopMemInstruction()
1888 case ARM::STC_POST: in DecodeCopMemInstruction()
1889 case ARM::STC_OPTION: in DecodeCopMemInstruction()
1890 case ARM::STCL_OFFSET: in DecodeCopMemInstruction()
1891 case ARM::STCL_PRE: in DecodeCopMemInstruction()
1892 case ARM::STCL_POST: in DecodeCopMemInstruction()
1893 case ARM::STCL_OPTION: in DecodeCopMemInstruction()
1894 case ARM::t2LDC_OFFSET: in DecodeCopMemInstruction()
1895 case ARM::t2LDC_PRE: in DecodeCopMemInstruction()
1896 case ARM::t2LDC_POST: in DecodeCopMemInstruction()
1897 case ARM::t2LDC_OPTION: in DecodeCopMemInstruction()
1898 case ARM::t2LDCL_OFFSET: in DecodeCopMemInstruction()
1899 case ARM::t2LDCL_PRE: in DecodeCopMemInstruction()
1900 case ARM::t2LDCL_POST: in DecodeCopMemInstruction()
1901 case ARM::t2LDCL_OPTION: in DecodeCopMemInstruction()
1902 case ARM::t2STC_OFFSET: in DecodeCopMemInstruction()
1903 case ARM::t2STC_PRE: in DecodeCopMemInstruction()
1904 case ARM::t2STC_POST: in DecodeCopMemInstruction()
1905 case ARM::t2STC_OPTION: in DecodeCopMemInstruction()
1906 case ARM::t2STCL_OFFSET: in DecodeCopMemInstruction()
1907 case ARM::t2STCL_PRE: in DecodeCopMemInstruction()
1908 case ARM::t2STCL_POST: in DecodeCopMemInstruction()
1909 case ARM::t2STCL_OPTION: in DecodeCopMemInstruction()
1910 case ARM::t2LDC2_OFFSET: in DecodeCopMemInstruction()
1911 case ARM::t2LDC2L_OFFSET: in DecodeCopMemInstruction()
1912 case ARM::t2LDC2_PRE: in DecodeCopMemInstruction()
1913 case ARM::t2LDC2L_PRE: in DecodeCopMemInstruction()
1914 case ARM::t2STC2_OFFSET: in DecodeCopMemInstruction()
1915 case ARM::t2STC2L_OFFSET: in DecodeCopMemInstruction()
1916 case ARM::t2STC2_PRE: in DecodeCopMemInstruction()
1917 case ARM::t2STC2L_PRE: in DecodeCopMemInstruction()
1918 case ARM::LDC2_OFFSET: in DecodeCopMemInstruction()
1919 case ARM::LDC2L_OFFSET: in DecodeCopMemInstruction()
1920 case ARM::LDC2_PRE: in DecodeCopMemInstruction()
1921 case ARM::LDC2L_PRE: in DecodeCopMemInstruction()
1922 case ARM::STC2_OFFSET: in DecodeCopMemInstruction()
1923 case ARM::STC2L_OFFSET: in DecodeCopMemInstruction()
1924 case ARM::STC2_PRE: in DecodeCopMemInstruction()
1925 case ARM::STC2L_PRE: in DecodeCopMemInstruction()
1926 case ARM::t2LDC2_OPTION: in DecodeCopMemInstruction()
1927 case ARM::t2STC2_OPTION: in DecodeCopMemInstruction()
1928 case ARM::t2LDC2_POST: in DecodeCopMemInstruction()
1929 case ARM::t2LDC2L_POST: in DecodeCopMemInstruction()
1930 case ARM::t2STC2_POST: in DecodeCopMemInstruction()
1931 case ARM::t2STC2L_POST: in DecodeCopMemInstruction()
1932 case ARM::LDC2_POST: in DecodeCopMemInstruction()
1933 case ARM::LDC2L_POST: in DecodeCopMemInstruction()
1934 case ARM::STC2_POST: in DecodeCopMemInstruction()
1935 case ARM::STC2L_POST: in DecodeCopMemInstruction()
1937 (featureBits[ARM::HasV8_1MMainlineOps] && in DecodeCopMemInstruction()
1946 if (featureBits[ARM::HasV8Ops] && (coproc != 14)) in DecodeCopMemInstruction()
1955 case ARM::t2LDC2_OFFSET: in DecodeCopMemInstruction()
1956 case ARM::t2LDC2L_OFFSET: in DecodeCopMemInstruction()
1957 case ARM::t2LDC2_PRE: in DecodeCopMemInstruction()
1958 case ARM::t2LDC2L_PRE: in DecodeCopMemInstruction()
1959 case ARM::t2STC2_OFFSET: in DecodeCopMemInstruction()
1960 case ARM::t2STC2L_OFFSET: in DecodeCopMemInstruction()
1961 case ARM::t2STC2_PRE: in DecodeCopMemInstruction()
1962 case ARM::t2STC2L_PRE: in DecodeCopMemInstruction()
1963 case ARM::LDC2_OFFSET: in DecodeCopMemInstruction()
1964 case ARM::LDC2L_OFFSET: in DecodeCopMemInstruction()
1965 case ARM::LDC2_PRE: in DecodeCopMemInstruction()
1966 case ARM::LDC2L_PRE: in DecodeCopMemInstruction()
1967 case ARM::STC2_OFFSET: in DecodeCopMemInstruction()
1968 case ARM::STC2L_OFFSET: in DecodeCopMemInstruction()
1969 case ARM::STC2_PRE: in DecodeCopMemInstruction()
1970 case ARM::STC2L_PRE: in DecodeCopMemInstruction()
1971 case ARM::t2LDC_OFFSET: in DecodeCopMemInstruction()
1972 case ARM::t2LDCL_OFFSET: in DecodeCopMemInstruction()
1973 case ARM::t2LDC_PRE: in DecodeCopMemInstruction()
1974 case ARM::t2LDCL_PRE: in DecodeCopMemInstruction()
1975 case ARM::t2STC_OFFSET: in DecodeCopMemInstruction()
1976 case ARM::t2STCL_OFFSET: in DecodeCopMemInstruction()
1977 case ARM::t2STC_PRE: in DecodeCopMemInstruction()
1978 case ARM::t2STCL_PRE: in DecodeCopMemInstruction()
1979 case ARM::LDC_OFFSET: in DecodeCopMemInstruction()
1980 case ARM::LDCL_OFFSET: in DecodeCopMemInstruction()
1981 case ARM::LDC_PRE: in DecodeCopMemInstruction()
1982 case ARM::LDCL_PRE: in DecodeCopMemInstruction()
1983 case ARM::STC_OFFSET: in DecodeCopMemInstruction()
1984 case ARM::STCL_OFFSET: in DecodeCopMemInstruction()
1985 case ARM::STC_PRE: in DecodeCopMemInstruction()
1986 case ARM::STCL_PRE: in DecodeCopMemInstruction()
1990 case ARM::t2LDC2_POST: in DecodeCopMemInstruction()
1991 case ARM::t2LDC2L_POST: in DecodeCopMemInstruction()
1992 case ARM::t2STC2_POST: in DecodeCopMemInstruction()
1993 case ARM::t2STC2L_POST: in DecodeCopMemInstruction()
1994 case ARM::LDC2_POST: in DecodeCopMemInstruction()
1995 case ARM::LDC2L_POST: in DecodeCopMemInstruction()
1996 case ARM::STC2_POST: in DecodeCopMemInstruction()
1997 case ARM::STC2L_POST: in DecodeCopMemInstruction()
1998 case ARM::t2LDC_POST: in DecodeCopMemInstruction()
1999 case ARM::t2LDCL_POST: in DecodeCopMemInstruction()
2000 case ARM::t2STC_POST: in DecodeCopMemInstruction()
2001 case ARM::t2STCL_POST: in DecodeCopMemInstruction()
2002 case ARM::LDC_POST: in DecodeCopMemInstruction()
2003 case ARM::LDCL_POST: in DecodeCopMemInstruction()
2004 case ARM::STC_POST: in DecodeCopMemInstruction()
2005 case ARM::STCL_POST: in DecodeCopMemInstruction()
2016 case ARM::LDC_OFFSET: in DecodeCopMemInstruction()
2017 case ARM::LDC_PRE: in DecodeCopMemInstruction()
2018 case ARM::LDC_POST: in DecodeCopMemInstruction()
2019 case ARM::LDC_OPTION: in DecodeCopMemInstruction()
2020 case ARM::LDCL_OFFSET: in DecodeCopMemInstruction()
2021 case ARM::LDCL_PRE: in DecodeCopMemInstruction()
2022 case ARM::LDCL_POST: in DecodeCopMemInstruction()
2023 case ARM::LDCL_OPTION: in DecodeCopMemInstruction()
2024 case ARM::STC_OFFSET: in DecodeCopMemInstruction()
2025 case ARM::STC_PRE: in DecodeCopMemInstruction()
2026 case ARM::STC_POST: in DecodeCopMemInstruction()
2027 case ARM::STC_OPTION: in DecodeCopMemInstruction()
2028 case ARM::STCL_OFFSET: in DecodeCopMemInstruction()
2029 case ARM::STCL_PRE: in DecodeCopMemInstruction()
2030 case ARM::STCL_POST: in DecodeCopMemInstruction()
2031 case ARM::STCL_OPTION: in DecodeCopMemInstruction()
2058 case ARM::STR_POST_IMM: in DecodeAddrMode2IdxInstruction()
2059 case ARM::STR_POST_REG: in DecodeAddrMode2IdxInstruction()
2060 case ARM::STRB_POST_IMM: in DecodeAddrMode2IdxInstruction()
2061 case ARM::STRB_POST_REG: in DecodeAddrMode2IdxInstruction()
2062 case ARM::STRT_POST_REG: in DecodeAddrMode2IdxInstruction()
2063 case ARM::STRT_POST_IMM: in DecodeAddrMode2IdxInstruction()
2064 case ARM::STRBT_POST_REG: in DecodeAddrMode2IdxInstruction()
2065 case ARM::STRBT_POST_IMM: in DecodeAddrMode2IdxInstruction()
2078 case ARM::LDR_POST_IMM: in DecodeAddrMode2IdxInstruction()
2079 case ARM::LDR_POST_REG: in DecodeAddrMode2IdxInstruction()
2080 case ARM::LDRB_POST_IMM: in DecodeAddrMode2IdxInstruction()
2081 case ARM::LDRB_POST_REG: in DecodeAddrMode2IdxInstruction()
2082 case ARM::LDRBT_POST_REG: in DecodeAddrMode2IdxInstruction()
2083 case ARM::LDRBT_POST_IMM: in DecodeAddrMode2IdxInstruction()
2084 case ARM::LDRT_POST_REG: in DecodeAddrMode2IdxInstruction()
2085 case ARM::LDRT_POST_IMM: in DecodeAddrMode2IdxInstruction()
2195 if (Inst.getOpcode() != ARM::TSB && Inst.getOpcode() != ARM::t2TSB) in DecodeTSBInstruction()
2225 case ARM::STRD: in DecodeAddrMode3Instruction()
2226 case ARM::STRD_PRE: in DecodeAddrMode3Instruction()
2227 case ARM::STRD_POST: in DecodeAddrMode3Instruction()
2228 case ARM::LDRD: in DecodeAddrMode3Instruction()
2229 case ARM::LDRD_PRE: in DecodeAddrMode3Instruction()
2230 case ARM::LDRD_POST: in DecodeAddrMode3Instruction()
2237 case ARM::STRD: in DecodeAddrMode3Instruction()
2238 case ARM::STRD_PRE: in DecodeAddrMode3Instruction()
2239 case ARM::STRD_POST: in DecodeAddrMode3Instruction()
2252 case ARM::STRH: in DecodeAddrMode3Instruction()
2253 case ARM::STRH_PRE: in DecodeAddrMode3Instruction()
2254 case ARM::STRH_POST: in DecodeAddrMode3Instruction()
2262 case ARM::LDRD: in DecodeAddrMode3Instruction()
2263 case ARM::LDRD_PRE: in DecodeAddrMode3Instruction()
2264 case ARM::LDRD_POST: in DecodeAddrMode3Instruction()
2279 case ARM::LDRH: in DecodeAddrMode3Instruction()
2280 case ARM::LDRH_PRE: in DecodeAddrMode3Instruction()
2281 case ARM::LDRH_POST: in DecodeAddrMode3Instruction()
2294 case ARM::LDRSH: in DecodeAddrMode3Instruction()
2295 case ARM::LDRSH_PRE: in DecodeAddrMode3Instruction()
2296 case ARM::LDRSH_POST: in DecodeAddrMode3Instruction()
2297 case ARM::LDRSB: in DecodeAddrMode3Instruction()
2298 case ARM::LDRSB_PRE: in DecodeAddrMode3Instruction()
2299 case ARM::LDRSB_POST: in DecodeAddrMode3Instruction()
2324 case ARM::STRD: in DecodeAddrMode3Instruction()
2325 case ARM::STRD_PRE: in DecodeAddrMode3Instruction()
2326 case ARM::STRD_POST: in DecodeAddrMode3Instruction()
2327 case ARM::STRH: in DecodeAddrMode3Instruction()
2328 case ARM::STRH_PRE: in DecodeAddrMode3Instruction()
2329 case ARM::STRH_POST: in DecodeAddrMode3Instruction()
2341 case ARM::STRD: in DecodeAddrMode3Instruction()
2342 case ARM::STRD_PRE: in DecodeAddrMode3Instruction()
2343 case ARM::STRD_POST: in DecodeAddrMode3Instruction()
2344 case ARM::LDRD: in DecodeAddrMode3Instruction()
2345 case ARM::LDRD_PRE: in DecodeAddrMode3Instruction()
2346 case ARM::LDRD_POST: in DecodeAddrMode3Instruction()
2357 case ARM::LDRD: in DecodeAddrMode3Instruction()
2358 case ARM::LDRD_PRE: in DecodeAddrMode3Instruction()
2359 case ARM::LDRD_POST: in DecodeAddrMode3Instruction()
2360 case ARM::LDRH: in DecodeAddrMode3Instruction()
2361 case ARM::LDRH_PRE: in DecodeAddrMode3Instruction()
2362 case ARM::LDRH_POST: in DecodeAddrMode3Instruction()
2363 case ARM::LDRSH: in DecodeAddrMode3Instruction()
2364 case ARM::LDRSH_PRE: in DecodeAddrMode3Instruction()
2365 case ARM::LDRSH_POST: in DecodeAddrMode3Instruction()
2366 case ARM::LDRSB: in DecodeAddrMode3Instruction()
2367 case ARM::LDRSB_PRE: in DecodeAddrMode3Instruction()
2368 case ARM::LDRSB_POST: in DecodeAddrMode3Instruction()
2369 case ARM::LDRHTr: in DecodeAddrMode3Instruction()
2370 case ARM::LDRSBTr: in DecodeAddrMode3Instruction()
2464 case ARM::LDMDA: in DecodeMemMultipleWritebackInstruction()
2465 Inst.setOpcode(ARM::RFEDA); in DecodeMemMultipleWritebackInstruction()
2467 case ARM::LDMDA_UPD: in DecodeMemMultipleWritebackInstruction()
2468 Inst.setOpcode(ARM::RFEDA_UPD); in DecodeMemMultipleWritebackInstruction()
2470 case ARM::LDMDB: in DecodeMemMultipleWritebackInstruction()
2471 Inst.setOpcode(ARM::RFEDB); in DecodeMemMultipleWritebackInstruction()
2473 case ARM::LDMDB_UPD: in DecodeMemMultipleWritebackInstruction()
2474 Inst.setOpcode(ARM::RFEDB_UPD); in DecodeMemMultipleWritebackInstruction()
2476 case ARM::LDMIA: in DecodeMemMultipleWritebackInstruction()
2477 Inst.setOpcode(ARM::RFEIA); in DecodeMemMultipleWritebackInstruction()
2479 case ARM::LDMIA_UPD: in DecodeMemMultipleWritebackInstruction()
2480 Inst.setOpcode(ARM::RFEIA_UPD); in DecodeMemMultipleWritebackInstruction()
2482 case ARM::LDMIB: in DecodeMemMultipleWritebackInstruction()
2483 Inst.setOpcode(ARM::RFEIB); in DecodeMemMultipleWritebackInstruction()
2485 case ARM::LDMIB_UPD: in DecodeMemMultipleWritebackInstruction()
2486 Inst.setOpcode(ARM::RFEIB_UPD); in DecodeMemMultipleWritebackInstruction()
2488 case ARM::STMDA: in DecodeMemMultipleWritebackInstruction()
2489 Inst.setOpcode(ARM::SRSDA); in DecodeMemMultipleWritebackInstruction()
2491 case ARM::STMDA_UPD: in DecodeMemMultipleWritebackInstruction()
2492 Inst.setOpcode(ARM::SRSDA_UPD); in DecodeMemMultipleWritebackInstruction()
2494 case ARM::STMDB: in DecodeMemMultipleWritebackInstruction()
2495 Inst.setOpcode(ARM::SRSDB); in DecodeMemMultipleWritebackInstruction()
2497 case ARM::STMDB_UPD: in DecodeMemMultipleWritebackInstruction()
2498 Inst.setOpcode(ARM::SRSDB_UPD); in DecodeMemMultipleWritebackInstruction()
2500 case ARM::STMIA: in DecodeMemMultipleWritebackInstruction()
2501 Inst.setOpcode(ARM::SRSIA); in DecodeMemMultipleWritebackInstruction()
2503 case ARM::STMIA_UPD: in DecodeMemMultipleWritebackInstruction()
2504 Inst.setOpcode(ARM::SRSIA_UPD); in DecodeMemMultipleWritebackInstruction()
2506 case ARM::STMIB: in DecodeMemMultipleWritebackInstruction()
2507 Inst.setOpcode(ARM::SRSIB); in DecodeMemMultipleWritebackInstruction()
2509 case ARM::STMIB_UPD: in DecodeMemMultipleWritebackInstruction()
2510 Inst.setOpcode(ARM::SRSIB_UPD); in DecodeMemMultipleWritebackInstruction()
2561 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0)) in DecodeHINTInstruction()
2592 Inst.setOpcode(ARM::CPS3p); in DecodeCPSInstruction()
2597 Inst.setOpcode(ARM::CPS2p); in DecodeCPSInstruction()
2602 Inst.setOpcode(ARM::CPS1p); in DecodeCPSInstruction()
2607 Inst.setOpcode(ARM::CPS1p); in DecodeCPSInstruction()
2633 Inst.setOpcode(ARM::t2CPS3p); in DecodeT2CPSInstruction()
2638 Inst.setOpcode(ARM::t2CPS2p); in DecodeT2CPSInstruction()
2643 Inst.setOpcode(ARM::t2CPS1p); in DecodeT2CPSInstruction()
2651 Inst.setOpcode(ARM::t2HINT); in DecodeT2CPSInstruction()
2663 unsigned Opcode = ARM::t2HINT; in DecodeT2HintSpaceInstruction()
2666 Opcode = ARM::t2PACBTI; in DecodeT2HintSpaceInstruction()
2668 Opcode = ARM::t2PAC; in DecodeT2HintSpaceInstruction()
2670 Opcode = ARM::t2AUT; in DecodeT2HintSpaceInstruction()
2672 Opcode = ARM::t2BTI; in DecodeT2HintSpaceInstruction()
2676 if (Opcode == ARM::t2HINT) { in DecodeT2HintSpaceInstruction()
2696 if (Inst.getOpcode() == ARM::t2MOVTi16) in DecodeT2MOVTWInstruction()
2720 if (Inst.getOpcode() == ARM::MOVTi16) in DecodeArmMOVTWInstruction()
2797 if (!FeatureBits[ARM::HasV8_1aOps] || in DecodeSETPANInstruction()
2798 !FeatureBits[ARM::HasV8Ops]) in DecodeSETPANInstruction()
2810 Inst.setOpcode(ARM::SETPAN); in DecodeSETPANInstruction()
2921 Inst.setOpcode(ARM::BLXi); in DecodeBranchImmInstruction()
2935 if (Inst.getOpcode() != ARM::BL) in DecodeBranchImmInstruction()
2974 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: in DecodeVLDInstruction()
2975 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: in DecodeVLDInstruction()
2976 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: in DecodeVLDInstruction()
2977 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: in DecodeVLDInstruction()
2978 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: in DecodeVLDInstruction()
2979 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: in DecodeVLDInstruction()
2980 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: in DecodeVLDInstruction()
2981 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: in DecodeVLDInstruction()
2982 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: in DecodeVLDInstruction()
2986 case ARM::VLD2b16: in DecodeVLDInstruction()
2987 case ARM::VLD2b32: in DecodeVLDInstruction()
2988 case ARM::VLD2b8: in DecodeVLDInstruction()
2989 case ARM::VLD2b16wb_fixed: in DecodeVLDInstruction()
2990 case ARM::VLD2b16wb_register: in DecodeVLDInstruction()
2991 case ARM::VLD2b32wb_fixed: in DecodeVLDInstruction()
2992 case ARM::VLD2b32wb_register: in DecodeVLDInstruction()
2993 case ARM::VLD2b8wb_fixed: in DecodeVLDInstruction()
2994 case ARM::VLD2b8wb_register: in DecodeVLDInstruction()
3005 case ARM::VLD3d8: in DecodeVLDInstruction()
3006 case ARM::VLD3d16: in DecodeVLDInstruction()
3007 case ARM::VLD3d32: in DecodeVLDInstruction()
3008 case ARM::VLD3d8_UPD: in DecodeVLDInstruction()
3009 case ARM::VLD3d16_UPD: in DecodeVLDInstruction()
3010 case ARM::VLD3d32_UPD: in DecodeVLDInstruction()
3011 case ARM::VLD4d8: in DecodeVLDInstruction()
3012 case ARM::VLD4d16: in DecodeVLDInstruction()
3013 case ARM::VLD4d32: in DecodeVLDInstruction()
3014 case ARM::VLD4d8_UPD: in DecodeVLDInstruction()
3015 case ARM::VLD4d16_UPD: in DecodeVLDInstruction()
3016 case ARM::VLD4d32_UPD: in DecodeVLDInstruction()
3020 case ARM::VLD3q8: in DecodeVLDInstruction()
3021 case ARM::VLD3q16: in DecodeVLDInstruction()
3022 case ARM::VLD3q32: in DecodeVLDInstruction()
3023 case ARM::VLD3q8_UPD: in DecodeVLDInstruction()
3024 case ARM::VLD3q16_UPD: in DecodeVLDInstruction()
3025 case ARM::VLD3q32_UPD: in DecodeVLDInstruction()
3026 case ARM::VLD4q8: in DecodeVLDInstruction()
3027 case ARM::VLD4q16: in DecodeVLDInstruction()
3028 case ARM::VLD4q32: in DecodeVLDInstruction()
3029 case ARM::VLD4q8_UPD: in DecodeVLDInstruction()
3030 case ARM::VLD4q16_UPD: in DecodeVLDInstruction()
3031 case ARM::VLD4q32_UPD: in DecodeVLDInstruction()
3041 case ARM::VLD3d8: in DecodeVLDInstruction()
3042 case ARM::VLD3d16: in DecodeVLDInstruction()
3043 case ARM::VLD3d32: in DecodeVLDInstruction()
3044 case ARM::VLD3d8_UPD: in DecodeVLDInstruction()
3045 case ARM::VLD3d16_UPD: in DecodeVLDInstruction()
3046 case ARM::VLD3d32_UPD: in DecodeVLDInstruction()
3047 case ARM::VLD4d8: in DecodeVLDInstruction()
3048 case ARM::VLD4d16: in DecodeVLDInstruction()
3049 case ARM::VLD4d32: in DecodeVLDInstruction()
3050 case ARM::VLD4d8_UPD: in DecodeVLDInstruction()
3051 case ARM::VLD4d16_UPD: in DecodeVLDInstruction()
3052 case ARM::VLD4d32_UPD: in DecodeVLDInstruction()
3056 case ARM::VLD3q8: in DecodeVLDInstruction()
3057 case ARM::VLD3q16: in DecodeVLDInstruction()
3058 case ARM::VLD3q32: in DecodeVLDInstruction()
3059 case ARM::VLD3q8_UPD: in DecodeVLDInstruction()
3060 case ARM::VLD3q16_UPD: in DecodeVLDInstruction()
3061 case ARM::VLD3q32_UPD: in DecodeVLDInstruction()
3062 case ARM::VLD4q8: in DecodeVLDInstruction()
3063 case ARM::VLD4q16: in DecodeVLDInstruction()
3064 case ARM::VLD4q32: in DecodeVLDInstruction()
3065 case ARM::VLD4q8_UPD: in DecodeVLDInstruction()
3066 case ARM::VLD4q16_UPD: in DecodeVLDInstruction()
3067 case ARM::VLD4q32_UPD: in DecodeVLDInstruction()
3077 case ARM::VLD4d8: in DecodeVLDInstruction()
3078 case ARM::VLD4d16: in DecodeVLDInstruction()
3079 case ARM::VLD4d32: in DecodeVLDInstruction()
3080 case ARM::VLD4d8_UPD: in DecodeVLDInstruction()
3081 case ARM::VLD4d16_UPD: in DecodeVLDInstruction()
3082 case ARM::VLD4d32_UPD: in DecodeVLDInstruction()
3086 case ARM::VLD4q8: in DecodeVLDInstruction()
3087 case ARM::VLD4q16: in DecodeVLDInstruction()
3088 case ARM::VLD4q32: in DecodeVLDInstruction()
3089 case ARM::VLD4q8_UPD: in DecodeVLDInstruction()
3090 case ARM::VLD4q16_UPD: in DecodeVLDInstruction()
3091 case ARM::VLD4q32_UPD: in DecodeVLDInstruction()
3101 case ARM::VLD1d8wb_fixed: in DecodeVLDInstruction()
3102 case ARM::VLD1d16wb_fixed: in DecodeVLDInstruction()
3103 case ARM::VLD1d32wb_fixed: in DecodeVLDInstruction()
3104 case ARM::VLD1d64wb_fixed: in DecodeVLDInstruction()
3105 case ARM::VLD1d8wb_register: in DecodeVLDInstruction()
3106 case ARM::VLD1d16wb_register: in DecodeVLDInstruction()
3107 case ARM::VLD1d32wb_register: in DecodeVLDInstruction()
3108 case ARM::VLD1d64wb_register: in DecodeVLDInstruction()
3109 case ARM::VLD1q8wb_fixed: in DecodeVLDInstruction()
3110 case ARM::VLD1q16wb_fixed: in DecodeVLDInstruction()
3111 case ARM::VLD1q32wb_fixed: in DecodeVLDInstruction()
3112 case ARM::VLD1q64wb_fixed: in DecodeVLDInstruction()
3113 case ARM::VLD1q8wb_register: in DecodeVLDInstruction()
3114 case ARM::VLD1q16wb_register: in DecodeVLDInstruction()
3115 case ARM::VLD1q32wb_register: in DecodeVLDInstruction()
3116 case ARM::VLD1q64wb_register: in DecodeVLDInstruction()
3117 case ARM::VLD1d8Twb_fixed: in DecodeVLDInstruction()
3118 case ARM::VLD1d8Twb_register: in DecodeVLDInstruction()
3119 case ARM::VLD1d16Twb_fixed: in DecodeVLDInstruction()
3120 case ARM::VLD1d16Twb_register: in DecodeVLDInstruction()
3121 case ARM::VLD1d32Twb_fixed: in DecodeVLDInstruction()
3122 case ARM::VLD1d32Twb_register: in DecodeVLDInstruction()
3123 case ARM::VLD1d64Twb_fixed: in DecodeVLDInstruction()
3124 case ARM::VLD1d64Twb_register: in DecodeVLDInstruction()
3125 case ARM::VLD1d8Qwb_fixed: in DecodeVLDInstruction()
3126 case ARM::VLD1d8Qwb_register: in DecodeVLDInstruction()
3127 case ARM::VLD1d16Qwb_fixed: in DecodeVLDInstruction()
3128 case ARM::VLD1d16Qwb_register: in DecodeVLDInstruction()
3129 case ARM::VLD1d32Qwb_fixed: in DecodeVLDInstruction()
3130 case ARM::VLD1d32Qwb_register: in DecodeVLDInstruction()
3131 case ARM::VLD1d64Qwb_fixed: in DecodeVLDInstruction()
3132 case ARM::VLD1d64Qwb_register: in DecodeVLDInstruction()
3133 case ARM::VLD2d8wb_fixed: in DecodeVLDInstruction()
3134 case ARM::VLD2d16wb_fixed: in DecodeVLDInstruction()
3135 case ARM::VLD2d32wb_fixed: in DecodeVLDInstruction()
3136 case ARM::VLD2q8wb_fixed: in DecodeVLDInstruction()
3137 case ARM::VLD2q16wb_fixed: in DecodeVLDInstruction()
3138 case ARM::VLD2q32wb_fixed: in DecodeVLDInstruction()
3139 case ARM::VLD2d8wb_register: in DecodeVLDInstruction()
3140 case ARM::VLD2d16wb_register: in DecodeVLDInstruction()
3141 case ARM::VLD2d32wb_register: in DecodeVLDInstruction()
3142 case ARM::VLD2q8wb_register: in DecodeVLDInstruction()
3143 case ARM::VLD2q16wb_register: in DecodeVLDInstruction()
3144 case ARM::VLD2q32wb_register: in DecodeVLDInstruction()
3145 case ARM::VLD2b8wb_fixed: in DecodeVLDInstruction()
3146 case ARM::VLD2b16wb_fixed: in DecodeVLDInstruction()
3147 case ARM::VLD2b32wb_fixed: in DecodeVLDInstruction()
3148 case ARM::VLD2b8wb_register: in DecodeVLDInstruction()
3149 case ARM::VLD2b16wb_register: in DecodeVLDInstruction()
3150 case ARM::VLD2b32wb_register: in DecodeVLDInstruction()
3153 case ARM::VLD3d8_UPD: in DecodeVLDInstruction()
3154 case ARM::VLD3d16_UPD: in DecodeVLDInstruction()
3155 case ARM::VLD3d32_UPD: in DecodeVLDInstruction()
3156 case ARM::VLD3q8_UPD: in DecodeVLDInstruction()
3157 case ARM::VLD3q16_UPD: in DecodeVLDInstruction()
3158 case ARM::VLD3q32_UPD: in DecodeVLDInstruction()
3159 case ARM::VLD4d8_UPD: in DecodeVLDInstruction()
3160 case ARM::VLD4d16_UPD: in DecodeVLDInstruction()
3161 case ARM::VLD4d32_UPD: in DecodeVLDInstruction()
3162 case ARM::VLD4q8_UPD: in DecodeVLDInstruction()
3163 case ARM::VLD4q16_UPD: in DecodeVLDInstruction()
3164 case ARM::VLD4q32_UPD: in DecodeVLDInstruction()
3191 case ARM::VLD1d8wb_fixed: in DecodeVLDInstruction()
3192 case ARM::VLD1d16wb_fixed: in DecodeVLDInstruction()
3193 case ARM::VLD1d32wb_fixed: in DecodeVLDInstruction()
3194 case ARM::VLD1d64wb_fixed: in DecodeVLDInstruction()
3195 case ARM::VLD1d8Twb_fixed: in DecodeVLDInstruction()
3196 case ARM::VLD1d16Twb_fixed: in DecodeVLDInstruction()
3197 case ARM::VLD1d32Twb_fixed: in DecodeVLDInstruction()
3198 case ARM::VLD1d64Twb_fixed: in DecodeVLDInstruction()
3199 case ARM::VLD1d8Qwb_fixed: in DecodeVLDInstruction()
3200 case ARM::VLD1d16Qwb_fixed: in DecodeVLDInstruction()
3201 case ARM::VLD1d32Qwb_fixed: in DecodeVLDInstruction()
3202 case ARM::VLD1d64Qwb_fixed: in DecodeVLDInstruction()
3203 case ARM::VLD1d8wb_register: in DecodeVLDInstruction()
3204 case ARM::VLD1d16wb_register: in DecodeVLDInstruction()
3205 case ARM::VLD1d32wb_register: in DecodeVLDInstruction()
3206 case ARM::VLD1d64wb_register: in DecodeVLDInstruction()
3207 case ARM::VLD1q8wb_fixed: in DecodeVLDInstruction()
3208 case ARM::VLD1q16wb_fixed: in DecodeVLDInstruction()
3209 case ARM::VLD1q32wb_fixed: in DecodeVLDInstruction()
3210 case ARM::VLD1q64wb_fixed: in DecodeVLDInstruction()
3211 case ARM::VLD1q8wb_register: in DecodeVLDInstruction()
3212 case ARM::VLD1q16wb_register: in DecodeVLDInstruction()
3213 case ARM::VLD1q32wb_register: in DecodeVLDInstruction()
3214 case ARM::VLD1q64wb_register: in DecodeVLDInstruction()
3222 case ARM::VLD2d8wb_fixed: in DecodeVLDInstruction()
3223 case ARM::VLD2d16wb_fixed: in DecodeVLDInstruction()
3224 case ARM::VLD2d32wb_fixed: in DecodeVLDInstruction()
3225 case ARM::VLD2b8wb_fixed: in DecodeVLDInstruction()
3226 case ARM::VLD2b16wb_fixed: in DecodeVLDInstruction()
3227 case ARM::VLD2b32wb_fixed: in DecodeVLDInstruction()
3228 case ARM::VLD2q8wb_fixed: in DecodeVLDInstruction()
3229 case ARM::VLD2q16wb_fixed: in DecodeVLDInstruction()
3230 case ARM::VLD2q32wb_fixed: in DecodeVLDInstruction()
3306 case ARM::VST1d8wb_fixed: in DecodeVSTInstruction()
3307 case ARM::VST1d16wb_fixed: in DecodeVSTInstruction()
3308 case ARM::VST1d32wb_fixed: in DecodeVSTInstruction()
3309 case ARM::VST1d64wb_fixed: in DecodeVSTInstruction()
3310 case ARM::VST1d8wb_register: in DecodeVSTInstruction()
3311 case ARM::VST1d16wb_register: in DecodeVSTInstruction()
3312 case ARM::VST1d32wb_register: in DecodeVSTInstruction()
3313 case ARM::VST1d64wb_register: in DecodeVSTInstruction()
3314 case ARM::VST1q8wb_fixed: in DecodeVSTInstruction()
3315 case ARM::VST1q16wb_fixed: in DecodeVSTInstruction()
3316 case ARM::VST1q32wb_fixed: in DecodeVSTInstruction()
3317 case ARM::VST1q64wb_fixed: in DecodeVSTInstruction()
3318 case ARM::VST1q8wb_register: in DecodeVSTInstruction()
3319 case ARM::VST1q16wb_register: in DecodeVSTInstruction()
3320 case ARM::VST1q32wb_register: in DecodeVSTInstruction()
3321 case ARM::VST1q64wb_register: in DecodeVSTInstruction()
3322 case ARM::VST1d8Twb_fixed: in DecodeVSTInstruction()
3323 case ARM::VST1d16Twb_fixed: in DecodeVSTInstruction()
3324 case ARM::VST1d32Twb_fixed: in DecodeVSTInstruction()
3325 case ARM::VST1d64Twb_fixed: in DecodeVSTInstruction()
3326 case ARM::VST1d8Twb_register: in DecodeVSTInstruction()
3327 case ARM::VST1d16Twb_register: in DecodeVSTInstruction()
3328 case ARM::VST1d32Twb_register: in DecodeVSTInstruction()
3329 case ARM::VST1d64Twb_register: in DecodeVSTInstruction()
3330 case ARM::VST1d8Qwb_fixed: in DecodeVSTInstruction()
3331 case ARM::VST1d16Qwb_fixed: in DecodeVSTInstruction()
3332 case ARM::VST1d32Qwb_fixed: in DecodeVSTInstruction()
3333 case ARM::VST1d64Qwb_fixed: in DecodeVSTInstruction()
3334 case ARM::VST1d8Qwb_register: in DecodeVSTInstruction()
3335 case ARM::VST1d16Qwb_register: in DecodeVSTInstruction()
3336 case ARM::VST1d32Qwb_register: in DecodeVSTInstruction()
3337 case ARM::VST1d64Qwb_register: in DecodeVSTInstruction()
3338 case ARM::VST2d8wb_fixed: in DecodeVSTInstruction()
3339 case ARM::VST2d16wb_fixed: in DecodeVSTInstruction()
3340 case ARM::VST2d32wb_fixed: in DecodeVSTInstruction()
3341 case ARM::VST2d8wb_register: in DecodeVSTInstruction()
3342 case ARM::VST2d16wb_register: in DecodeVSTInstruction()
3343 case ARM::VST2d32wb_register: in DecodeVSTInstruction()
3344 case ARM::VST2q8wb_fixed: in DecodeVSTInstruction()
3345 case ARM::VST2q16wb_fixed: in DecodeVSTInstruction()
3346 case ARM::VST2q32wb_fixed: in DecodeVSTInstruction()
3347 case ARM::VST2q8wb_register: in DecodeVSTInstruction()
3348 case ARM::VST2q16wb_register: in DecodeVSTInstruction()
3349 case ARM::VST2q32wb_register: in DecodeVSTInstruction()
3350 case ARM::VST2b8wb_fixed: in DecodeVSTInstruction()
3351 case ARM::VST2b16wb_fixed: in DecodeVSTInstruction()
3352 case ARM::VST2b32wb_fixed: in DecodeVSTInstruction()
3353 case ARM::VST2b8wb_register: in DecodeVSTInstruction()
3354 case ARM::VST2b16wb_register: in DecodeVSTInstruction()
3355 case ARM::VST2b32wb_register: in DecodeVSTInstruction()
3360 case ARM::VST3d8_UPD: in DecodeVSTInstruction()
3361 case ARM::VST3d16_UPD: in DecodeVSTInstruction()
3362 case ARM::VST3d32_UPD: in DecodeVSTInstruction()
3363 case ARM::VST3q8_UPD: in DecodeVSTInstruction()
3364 case ARM::VST3q16_UPD: in DecodeVSTInstruction()
3365 case ARM::VST3q32_UPD: in DecodeVSTInstruction()
3366 case ARM::VST4d8_UPD: in DecodeVSTInstruction()
3367 case ARM::VST4d16_UPD: in DecodeVSTInstruction()
3368 case ARM::VST4d32_UPD: in DecodeVSTInstruction()
3369 case ARM::VST4q8_UPD: in DecodeVSTInstruction()
3370 case ARM::VST4q16_UPD: in DecodeVSTInstruction()
3371 case ARM::VST4q32_UPD: in DecodeVSTInstruction()
3393 case ARM::VST1d8wb_fixed: in DecodeVSTInstruction()
3394 case ARM::VST1d16wb_fixed: in DecodeVSTInstruction()
3395 case ARM::VST1d32wb_fixed: in DecodeVSTInstruction()
3396 case ARM::VST1d64wb_fixed: in DecodeVSTInstruction()
3397 case ARM::VST1q8wb_fixed: in DecodeVSTInstruction()
3398 case ARM::VST1q16wb_fixed: in DecodeVSTInstruction()
3399 case ARM::VST1q32wb_fixed: in DecodeVSTInstruction()
3400 case ARM::VST1q64wb_fixed: in DecodeVSTInstruction()
3401 case ARM::VST1d8Twb_fixed: in DecodeVSTInstruction()
3402 case ARM::VST1d16Twb_fixed: in DecodeVSTInstruction()
3403 case ARM::VST1d32Twb_fixed: in DecodeVSTInstruction()
3404 case ARM::VST1d64Twb_fixed: in DecodeVSTInstruction()
3405 case ARM::VST1d8Qwb_fixed: in DecodeVSTInstruction()
3406 case ARM::VST1d16Qwb_fixed: in DecodeVSTInstruction()
3407 case ARM::VST1d32Qwb_fixed: in DecodeVSTInstruction()
3408 case ARM::VST1d64Qwb_fixed: in DecodeVSTInstruction()
3409 case ARM::VST2d8wb_fixed: in DecodeVSTInstruction()
3410 case ARM::VST2d16wb_fixed: in DecodeVSTInstruction()
3411 case ARM::VST2d32wb_fixed: in DecodeVSTInstruction()
3412 case ARM::VST2q8wb_fixed: in DecodeVSTInstruction()
3413 case ARM::VST2q16wb_fixed: in DecodeVSTInstruction()
3414 case ARM::VST2q32wb_fixed: in DecodeVSTInstruction()
3415 case ARM::VST2b8wb_fixed: in DecodeVSTInstruction()
3416 case ARM::VST2b16wb_fixed: in DecodeVSTInstruction()
3417 case ARM::VST2b32wb_fixed: in DecodeVSTInstruction()
3423 case ARM::VST1q16: in DecodeVSTInstruction()
3424 case ARM::VST1q32: in DecodeVSTInstruction()
3425 case ARM::VST1q64: in DecodeVSTInstruction()
3426 case ARM::VST1q8: in DecodeVSTInstruction()
3427 case ARM::VST1q16wb_fixed: in DecodeVSTInstruction()
3428 case ARM::VST1q16wb_register: in DecodeVSTInstruction()
3429 case ARM::VST1q32wb_fixed: in DecodeVSTInstruction()
3430 case ARM::VST1q32wb_register: in DecodeVSTInstruction()
3431 case ARM::VST1q64wb_fixed: in DecodeVSTInstruction()
3432 case ARM::VST1q64wb_register: in DecodeVSTInstruction()
3433 case ARM::VST1q8wb_fixed: in DecodeVSTInstruction()
3434 case ARM::VST1q8wb_register: in DecodeVSTInstruction()
3435 case ARM::VST2d16: in DecodeVSTInstruction()
3436 case ARM::VST2d32: in DecodeVSTInstruction()
3437 case ARM::VST2d8: in DecodeVSTInstruction()
3438 case ARM::VST2d16wb_fixed: in DecodeVSTInstruction()
3439 case ARM::VST2d16wb_register: in DecodeVSTInstruction()
3440 case ARM::VST2d32wb_fixed: in DecodeVSTInstruction()
3441 case ARM::VST2d32wb_register: in DecodeVSTInstruction()
3442 case ARM::VST2d8wb_fixed: in DecodeVSTInstruction()
3443 case ARM::VST2d8wb_register: in DecodeVSTInstruction()
3447 case ARM::VST2b16: in DecodeVSTInstruction()
3448 case ARM::VST2b32: in DecodeVSTInstruction()
3449 case ARM::VST2b8: in DecodeVSTInstruction()
3450 case ARM::VST2b16wb_fixed: in DecodeVSTInstruction()
3451 case ARM::VST2b16wb_register: in DecodeVSTInstruction()
3452 case ARM::VST2b32wb_fixed: in DecodeVSTInstruction()
3453 case ARM::VST2b32wb_register: in DecodeVSTInstruction()
3454 case ARM::VST2b8wb_fixed: in DecodeVSTInstruction()
3455 case ARM::VST2b8wb_register: in DecodeVSTInstruction()
3466 case ARM::VST3d8: in DecodeVSTInstruction()
3467 case ARM::VST3d16: in DecodeVSTInstruction()
3468 case ARM::VST3d32: in DecodeVSTInstruction()
3469 case ARM::VST3d8_UPD: in DecodeVSTInstruction()
3470 case ARM::VST3d16_UPD: in DecodeVSTInstruction()
3471 case ARM::VST3d32_UPD: in DecodeVSTInstruction()
3472 case ARM::VST4d8: in DecodeVSTInstruction()
3473 case ARM::VST4d16: in DecodeVSTInstruction()
3474 case ARM::VST4d32: in DecodeVSTInstruction()
3475 case ARM::VST4d8_UPD: in DecodeVSTInstruction()
3476 case ARM::VST4d16_UPD: in DecodeVSTInstruction()
3477 case ARM::VST4d32_UPD: in DecodeVSTInstruction()
3481 case ARM::VST3q8: in DecodeVSTInstruction()
3482 case ARM::VST3q16: in DecodeVSTInstruction()
3483 case ARM::VST3q32: in DecodeVSTInstruction()
3484 case ARM::VST3q8_UPD: in DecodeVSTInstruction()
3485 case ARM::VST3q16_UPD: in DecodeVSTInstruction()
3486 case ARM::VST3q32_UPD: in DecodeVSTInstruction()
3487 case ARM::VST4q8: in DecodeVSTInstruction()
3488 case ARM::VST4q16: in DecodeVSTInstruction()
3489 case ARM::VST4q32: in DecodeVSTInstruction()
3490 case ARM::VST4q8_UPD: in DecodeVSTInstruction()
3491 case ARM::VST4q16_UPD: in DecodeVSTInstruction()
3492 case ARM::VST4q32_UPD: in DecodeVSTInstruction()
3502 case ARM::VST3d8: in DecodeVSTInstruction()
3503 case ARM::VST3d16: in DecodeVSTInstruction()
3504 case ARM::VST3d32: in DecodeVSTInstruction()
3505 case ARM::VST3d8_UPD: in DecodeVSTInstruction()
3506 case ARM::VST3d16_UPD: in DecodeVSTInstruction()
3507 case ARM::VST3d32_UPD: in DecodeVSTInstruction()
3508 case ARM::VST4d8: in DecodeVSTInstruction()
3509 case ARM::VST4d16: in DecodeVSTInstruction()
3510 case ARM::VST4d32: in DecodeVSTInstruction()
3511 case ARM::VST4d8_UPD: in DecodeVSTInstruction()
3512 case ARM::VST4d16_UPD: in DecodeVSTInstruction()
3513 case ARM::VST4d32_UPD: in DecodeVSTInstruction()
3517 case ARM::VST3q8: in DecodeVSTInstruction()
3518 case ARM::VST3q16: in DecodeVSTInstruction()
3519 case ARM::VST3q32: in DecodeVSTInstruction()
3520 case ARM::VST3q8_UPD: in DecodeVSTInstruction()
3521 case ARM::VST3q16_UPD: in DecodeVSTInstruction()
3522 case ARM::VST3q32_UPD: in DecodeVSTInstruction()
3523 case ARM::VST4q8: in DecodeVSTInstruction()
3524 case ARM::VST4q16: in DecodeVSTInstruction()
3525 case ARM::VST4q32: in DecodeVSTInstruction()
3526 case ARM::VST4q8_UPD: in DecodeVSTInstruction()
3527 case ARM::VST4q16_UPD: in DecodeVSTInstruction()
3528 case ARM::VST4q32_UPD: in DecodeVSTInstruction()
3538 case ARM::VST4d8: in DecodeVSTInstruction()
3539 case ARM::VST4d16: in DecodeVSTInstruction()
3540 case ARM::VST4d32: in DecodeVSTInstruction()
3541 case ARM::VST4d8_UPD: in DecodeVSTInstruction()
3542 case ARM::VST4d16_UPD: in DecodeVSTInstruction()
3543 case ARM::VST4d32_UPD: in DecodeVSTInstruction()
3547 case ARM::VST4q8: in DecodeVSTInstruction()
3548 case ARM::VST4q16: in DecodeVSTInstruction()
3549 case ARM::VST4q32: in DecodeVSTInstruction()
3550 case ARM::VST4q8_UPD: in DecodeVSTInstruction()
3551 case ARM::VST4q16_UPD: in DecodeVSTInstruction()
3552 case ARM::VST4q32_UPD: in DecodeVSTInstruction()
3580 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: in DecodeVLD1DupInstruction()
3581 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: in DecodeVLD1DupInstruction()
3582 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: in DecodeVLD1DupInstruction()
3583 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: in DecodeVLD1DupInstruction()
3625 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: in DecodeVLD2DupInstruction()
3626 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: in DecodeVLD2DupInstruction()
3627 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: in DecodeVLD2DupInstruction()
3628 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: in DecodeVLD2DupInstruction()
3632 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: in DecodeVLD2DupInstruction()
3633 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: in DecodeVLD2DupInstruction()
3634 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: in DecodeVLD2DupInstruction()
3635 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: in DecodeVLD2DupInstruction()
3774 case ARM::VORRiv4i16: in DecodeVMOVModImmInstruction()
3775 case ARM::VORRiv2i32: in DecodeVMOVModImmInstruction()
3776 case ARM::VBICiv4i16: in DecodeVMOVModImmInstruction()
3777 case ARM::VBICiv2i32: in DecodeVMOVModImmInstruction()
3781 case ARM::VORRiv8i16: in DecodeVMOVModImmInstruction()
3782 case ARM::VORRiv4i32: in DecodeVMOVModImmInstruction()
3783 case ARM::VBICiv8i16: in DecodeVMOVModImmInstruction()
3784 case ARM::VBICiv4i32: in DecodeVMOVModImmInstruction()
3809 if (cmode == 0xF && Inst.getOpcode() == ARM::MVE_VMVNimmi32) in DecodeMVEModImmInstruction()
3833 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); in DecodeMVEVADCInstruction()
3844 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); in DecodeMVEVADCInstruction()
3919 case ARM::VTBL2: in DecodeTBLInstruction()
3920 case ARM::VTBX2: in DecodeTBLInstruction()
3949 case ARM::tADR: in DecodeThumbAddSpecialReg()
3951 case ARM::tADDrSPi: in DecodeThumbAddSpecialReg()
3952 Inst.addOperand(MCOperand::createReg(ARM::SP)); in DecodeThumbAddSpecialReg()
4032 Inst.addOperand(MCOperand::createReg(ARM::SP)); in DecodeThumbAddrModeSP()
4049 case ARM::t2STRHs: in DecodeT2AddrModeSOReg()
4050 case ARM::t2STRBs: in DecodeT2AddrModeSOReg()
4051 case ARM::t2STRs: in DecodeT2AddrModeSOReg()
4079 bool hasMP = featureBits[ARM::FeatureMP]; in DecodeT2LoadShift()
4080 bool hasV7Ops = featureBits[ARM::HasV7Ops]; in DecodeT2LoadShift()
4084 case ARM::t2LDRBs: in DecodeT2LoadShift()
4085 Inst.setOpcode(ARM::t2LDRBpci); in DecodeT2LoadShift()
4087 case ARM::t2LDRHs: in DecodeT2LoadShift()
4088 Inst.setOpcode(ARM::t2LDRHpci); in DecodeT2LoadShift()
4090 case ARM::t2LDRSHs: in DecodeT2LoadShift()
4091 Inst.setOpcode(ARM::t2LDRSHpci); in DecodeT2LoadShift()
4093 case ARM::t2LDRSBs: in DecodeT2LoadShift()
4094 Inst.setOpcode(ARM::t2LDRSBpci); in DecodeT2LoadShift()
4096 case ARM::t2LDRs: in DecodeT2LoadShift()
4097 Inst.setOpcode(ARM::t2LDRpci); in DecodeT2LoadShift()
4099 case ARM::t2PLDs: in DecodeT2LoadShift()
4100 Inst.setOpcode(ARM::t2PLDpci); in DecodeT2LoadShift()
4102 case ARM::t2PLIs: in DecodeT2LoadShift()
4103 Inst.setOpcode(ARM::t2PLIpci); in DecodeT2LoadShift()
4114 case ARM::t2LDRSHs: in DecodeT2LoadShift()
4116 case ARM::t2LDRHs: in DecodeT2LoadShift()
4117 Inst.setOpcode(ARM::t2PLDWs); in DecodeT2LoadShift()
4119 case ARM::t2LDRSBs: in DecodeT2LoadShift()
4120 Inst.setOpcode(ARM::t2PLIs); in DecodeT2LoadShift()
4128 case ARM::t2PLDs: in DecodeT2LoadShift()
4130 case ARM::t2PLIs: in DecodeT2LoadShift()
4134 case ARM::t2PLDWs: in DecodeT2LoadShift()
4168 bool hasMP = featureBits[ARM::FeatureMP]; in DecodeT2LoadImm8()
4169 bool hasV7Ops = featureBits[ARM::HasV7Ops]; in DecodeT2LoadImm8()
4173 case ARM::t2LDRi8: in DecodeT2LoadImm8()
4174 Inst.setOpcode(ARM::t2LDRpci); in DecodeT2LoadImm8()
4176 case ARM::t2LDRBi8: in DecodeT2LoadImm8()
4177 Inst.setOpcode(ARM::t2LDRBpci); in DecodeT2LoadImm8()
4179 case ARM::t2LDRSBi8: in DecodeT2LoadImm8()
4180 Inst.setOpcode(ARM::t2LDRSBpci); in DecodeT2LoadImm8()
4182 case ARM::t2LDRHi8: in DecodeT2LoadImm8()
4183 Inst.setOpcode(ARM::t2LDRHpci); in DecodeT2LoadImm8()
4185 case ARM::t2LDRSHi8: in DecodeT2LoadImm8()
4186 Inst.setOpcode(ARM::t2LDRSHpci); in DecodeT2LoadImm8()
4188 case ARM::t2PLDi8: in DecodeT2LoadImm8()
4189 Inst.setOpcode(ARM::t2PLDpci); in DecodeT2LoadImm8()
4191 case ARM::t2PLIi8: in DecodeT2LoadImm8()
4192 Inst.setOpcode(ARM::t2PLIpci); in DecodeT2LoadImm8()
4202 case ARM::t2LDRSHi8: in DecodeT2LoadImm8()
4204 case ARM::t2LDRHi8: in DecodeT2LoadImm8()
4206 Inst.setOpcode(ARM::t2PLDWi8); in DecodeT2LoadImm8()
4208 case ARM::t2LDRSBi8: in DecodeT2LoadImm8()
4209 Inst.setOpcode(ARM::t2PLIi8); in DecodeT2LoadImm8()
4217 case ARM::t2PLDi8: in DecodeT2LoadImm8()
4219 case ARM::t2PLIi8: in DecodeT2LoadImm8()
4223 case ARM::t2PLDWi8: in DecodeT2LoadImm8()
4250 bool hasMP = featureBits[ARM::FeatureMP]; in DecodeT2LoadImm12()
4251 bool hasV7Ops = featureBits[ARM::HasV7Ops]; in DecodeT2LoadImm12()
4255 case ARM::t2LDRi12: in DecodeT2LoadImm12()
4256 Inst.setOpcode(ARM::t2LDRpci); in DecodeT2LoadImm12()
4258 case ARM::t2LDRHi12: in DecodeT2LoadImm12()
4259 Inst.setOpcode(ARM::t2LDRHpci); in DecodeT2LoadImm12()
4261 case ARM::t2LDRSHi12: in DecodeT2LoadImm12()
4262 Inst.setOpcode(ARM::t2LDRSHpci); in DecodeT2LoadImm12()
4264 case ARM::t2LDRBi12: in DecodeT2LoadImm12()
4265 Inst.setOpcode(ARM::t2LDRBpci); in DecodeT2LoadImm12()
4267 case ARM::t2LDRSBi12: in DecodeT2LoadImm12()
4268 Inst.setOpcode(ARM::t2LDRSBpci); in DecodeT2LoadImm12()
4270 case ARM::t2PLDi12: in DecodeT2LoadImm12()
4271 Inst.setOpcode(ARM::t2PLDpci); in DecodeT2LoadImm12()
4273 case ARM::t2PLIi12: in DecodeT2LoadImm12()
4274 Inst.setOpcode(ARM::t2PLIpci); in DecodeT2LoadImm12()
4284 case ARM::t2LDRSHi12: in DecodeT2LoadImm12()
4286 case ARM::t2LDRHi12: in DecodeT2LoadImm12()
4287 Inst.setOpcode(ARM::t2PLDWi12); in DecodeT2LoadImm12()
4289 case ARM::t2LDRSBi12: in DecodeT2LoadImm12()
4290 Inst.setOpcode(ARM::t2PLIi12); in DecodeT2LoadImm12()
4298 case ARM::t2PLDi12: in DecodeT2LoadImm12()
4300 case ARM::t2PLIi12: in DecodeT2LoadImm12()
4304 case ARM::t2PLDWi12: in DecodeT2LoadImm12()
4329 case ARM::t2LDRT: in DecodeT2LoadT()
4330 Inst.setOpcode(ARM::t2LDRpci); in DecodeT2LoadT()
4332 case ARM::t2LDRBT: in DecodeT2LoadT()
4333 Inst.setOpcode(ARM::t2LDRBpci); in DecodeT2LoadT()
4335 case ARM::t2LDRHT: in DecodeT2LoadT()
4336 Inst.setOpcode(ARM::t2LDRHpci); in DecodeT2LoadT()
4338 case ARM::t2LDRSBT: in DecodeT2LoadT()
4339 Inst.setOpcode(ARM::t2LDRSBpci); in DecodeT2LoadT()
4341 case ARM::t2LDRSHT: in DecodeT2LoadT()
4342 Inst.setOpcode(ARM::t2LDRSHpci); in DecodeT2LoadT()
4369 bool hasV7Ops = featureBits[ARM::HasV7Ops]; in DecodeT2LoadLabel()
4373 case ARM::t2LDRBpci: in DecodeT2LoadLabel()
4374 case ARM::t2LDRHpci: in DecodeT2LoadLabel()
4375 Inst.setOpcode(ARM::t2PLDpci); in DecodeT2LoadLabel()
4377 case ARM::t2LDRSBpci: in DecodeT2LoadLabel()
4378 Inst.setOpcode(ARM::t2PLIpci); in DecodeT2LoadLabel()
4380 case ARM::t2LDRSHpci: in DecodeT2LoadLabel()
4388 case ARM::t2PLDpci: in DecodeT2LoadLabel()
4390 case ARM::t2PLIpci: in DecodeT2LoadLabel()
4525 case ARM::t2STRT: in DecodeT2AddrModeImm8()
4526 case ARM::t2STRBT: in DecodeT2AddrModeImm8()
4527 case ARM::t2STRHT: in DecodeT2AddrModeImm8()
4528 case ARM::t2STRi8: in DecodeT2AddrModeImm8()
4529 case ARM::t2STRHi8: in DecodeT2AddrModeImm8()
4530 case ARM::t2STRBi8: in DecodeT2AddrModeImm8()
4540 case ARM::t2LDRT: in DecodeT2AddrModeImm8()
4541 case ARM::t2LDRBT: in DecodeT2AddrModeImm8()
4542 case ARM::t2LDRHT: in DecodeT2AddrModeImm8()
4543 case ARM::t2LDRSBT: in DecodeT2AddrModeImm8()
4544 case ARM::t2LDRSHT: in DecodeT2AddrModeImm8()
4545 case ARM::t2STRT: in DecodeT2AddrModeImm8()
4546 case ARM::t2STRBT: in DecodeT2AddrModeImm8()
4547 case ARM::t2STRHT: in DecodeT2AddrModeImm8()
4612 case ARM::t2LDR_PRE: in DecodeT2LdStPre()
4613 case ARM::t2LDR_POST: in DecodeT2LdStPre()
4614 Inst.setOpcode(ARM::t2LDRpci); in DecodeT2LdStPre()
4616 case ARM::t2LDRB_PRE: in DecodeT2LdStPre()
4617 case ARM::t2LDRB_POST: in DecodeT2LdStPre()
4618 Inst.setOpcode(ARM::t2LDRBpci); in DecodeT2LdStPre()
4620 case ARM::t2LDRH_PRE: in DecodeT2LdStPre()
4621 case ARM::t2LDRH_POST: in DecodeT2LdStPre()
4622 Inst.setOpcode(ARM::t2LDRHpci); in DecodeT2LdStPre()
4624 case ARM::t2LDRSB_PRE: in DecodeT2LdStPre()
4625 case ARM::t2LDRSB_POST: in DecodeT2LdStPre()
4627 Inst.setOpcode(ARM::t2PLIpci); in DecodeT2LdStPre()
4629 Inst.setOpcode(ARM::t2LDRSBpci); in DecodeT2LdStPre()
4631 case ARM::t2LDRSH_PRE: in DecodeT2LdStPre()
4632 case ARM::t2LDRSH_POST: in DecodeT2LdStPre()
4633 Inst.setOpcode(ARM::t2LDRSHpci); in DecodeT2LdStPre()
4670 case ARM::t2STRi12: in DecodeT2AddrModeImm12()
4671 case ARM::t2STRBi12: in DecodeT2AddrModeImm12()
4672 case ARM::t2STRHi12: in DecodeT2AddrModeImm12()
4692 Inst.addOperand(MCOperand::createReg(ARM::SP)); in DecodeThumbAddSPImm()
4693 Inst.addOperand(MCOperand::createReg(ARM::SP)); in DecodeThumbAddSPImm()
4704 if (Inst.getOpcode() == ARM::tADDrSP) { in DecodeThumbAddSPReg()
4710 Inst.addOperand(MCOperand::createReg(ARM::SP)); in DecodeThumbAddSPReg()
4713 } else if (Inst.getOpcode() == ARM::tADDspr) { in DecodeThumbAddSPReg()
4716 Inst.addOperand(MCOperand::createReg(ARM::SP)); in DecodeThumbAddSPReg()
4717 Inst.addOperand(MCOperand::createReg(ARM::SP)); in DecodeThumbAddSPReg()
4841 if (Rn == 13 && !FeatureBits[ARM::HasV8Ops]) S = MCDisassembler::SoftFail; in DecodeThumbTableBranch()
4861 Inst.setOpcode(ARM::t2DSB); in DecodeThumb2BCCInstruction()
4864 Inst.setOpcode(ARM::t2DMB); in DecodeThumb2BCCInstruction()
4867 Inst.setOpcode(ARM::t2ISB); in DecodeThumb2BCCInstruction()
4982 if (FeatureBits[ARM::FeatureMClass]) { in DecodeMSRMask()
5002 if (!(FeatureBits[ARM::HasV7Ops])) in DecodeMSRMask()
5010 if (!(FeatureBits[ARM::HasV8MMainlineOps])) in DecodeMSRMask()
5020 if (!(FeatureBits[ARM::Feature8MSecExt])) in DecodeMSRMask()
5039 if (!(FeatureBits[ARM::FeaturePACBTI])) in DecodeMSRMask()
5048 if (Inst.getOpcode() == ARM::t2MSR_M) { in DecodeMSRMask()
5050 if (!(FeatureBits[ARM::HasV7Ops])) { in DecodeMSRMask()
5064 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1))) in DecodeMSRMask()
5965 Inst.setOpcode(ARM::t2SUBri12); in DecodeT2Adr()
5966 Inst.addOperand(MCOperand::createReg(ARM::PC)); in DecodeT2Adr()
6016 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; in DecodeVCVTD()
6032 Inst.setOpcode(ARM::VMOVv2f32); in DecodeVCVTD()
6037 Inst.setOpcode(ARM::VMOVv1i64); in DecodeVCVTD()
6039 Inst.setOpcode(ARM::VMOVv8i8); in DecodeVCVTD()
6044 Inst.setOpcode(ARM::VMVNv2i32); in DecodeVCVTD()
6046 Inst.setOpcode(ARM::VMOVv2i32); in DecodeVCVTD()
6051 Inst.setOpcode(ARM::VMVNv2i32); in DecodeVCVTD()
6053 Inst.setOpcode(ARM::VMOVv2i32); in DecodeVCVTD()
6075 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; in DecodeVCVTQ()
6091 Inst.setOpcode(ARM::VMOVv4f32); in DecodeVCVTQ()
6096 Inst.setOpcode(ARM::VMOVv2i64); in DecodeVCVTQ()
6098 Inst.setOpcode(ARM::VMOVv16i8); in DecodeVCVTQ()
6103 Inst.setOpcode(ARM::VMVNv4i32); in DecodeVCVTQ()
6105 Inst.setOpcode(ARM::VMOVv4i32); in DecodeVCVTQ()
6110 Inst.setOpcode(ARM::VMVNv4i32); in DecodeVCVTQ()
6112 Inst.setOpcode(ARM::VMOVv4i32); in DecodeVCVTQ()
6217 if (Inst.getOpcode() == ARM::MRRC2) { in DecoderForMRRC2AndMCRR2()
6225 if (Inst.getOpcode() == ARM::MCRR2) { in DecoderForMRRC2AndMCRR2()
6246 case ARM::VMSR_FPSCR_NZCVQC: in DecodeForVMRSandVMSR()
6247 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); in DecodeForVMRSandVMSR()
6249 case ARM::VMSR_P0: in DecodeForVMRSandVMSR()
6250 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeForVMRSandVMSR()
6254 if (Inst.getOpcode() != ARM::FMSTAT) { in DecodeForVMRSandVMSR()
6257 if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) { in DecodeForVMRSandVMSR()
6267 case ARM::VMRS_FPSCR_NZCVQC: in DecodeForVMRSandVMSR()
6268 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); in DecodeForVMRSandVMSR()
6270 case ARM::VMRS_P0: in DecodeForVMRSandVMSR()
6271 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeForVMRSandVMSR()
6275 if (featureBits[ARM::ModeThumb]) { in DecodeForVMRSandVMSR()
6332 if (Inst.getOpcode() == ARM::MVE_LCTP) in DecodeLOLoop()
6338 case ARM::t2LEUpdate: in DecodeLOLoop()
6339 case ARM::MVE_LETP: in DecodeLOLoop()
6340 Inst.addOperand(MCOperand::createReg(ARM::LR)); in DecodeLOLoop()
6341 Inst.addOperand(MCOperand::createReg(ARM::LR)); in DecodeLOLoop()
6343 case ARM::t2LE: in DecodeLOLoop()
6348 case ARM::t2WLS: in DecodeLOLoop()
6349 case ARM::MVE_WLSTP_8: in DecodeLOLoop()
6350 case ARM::MVE_WLSTP_16: in DecodeLOLoop()
6351 case ARM::MVE_WLSTP_32: in DecodeLOLoop()
6352 case ARM::MVE_WLSTP_64: in DecodeLOLoop()
6353 Inst.addOperand(MCOperand::createReg(ARM::LR)); in DecodeLOLoop()
6361 case ARM::t2DLS: in DecodeLOLoop()
6362 case ARM::MVE_DLSTP_8: in DecodeLOLoop()
6363 case ARM::MVE_DLSTP_16: in DecodeLOLoop()
6364 case ARM::MVE_DLSTP_32: in DecodeLOLoop()
6365 case ARM::MVE_DLSTP_64: in DecodeLOLoop()
6377 Inst.setOpcode(ARM::MVE_LCTP); in DecodeLOLoop()
6379 Inst.addOperand(MCOperand::createReg(ARM::LR)); in DecodeLOLoop()
6430 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); in DecodeGPRwithAPSR_NZCVnospRegisterClass()
6449 if (Inst.getOpcode() == ARM::VSCCLRMD) { in DecodeVSCCLRM()
6464 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeVSCCLRM()
6481 ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4,
6482 ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7
6497 ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5,
6498 ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7
6642 case ARM::MVE_VCVTf16s16_fix: in DecodeVCVTImmOperand()
6643 case ARM::MVE_VCVTs16f16_fix: in DecodeVCVTImmOperand()
6644 case ARM::MVE_VCVTf16u16_fix: in DecodeVCVTImmOperand()
6645 case ARM::MVE_VCVTu16f16_fix: in DecodeVCVTImmOperand()
6649 case ARM::MVE_VCVTf32s32_fix: in DecodeVCVTImmOperand()
6650 case ARM::MVE_VCVTs32f32_fix: in DecodeVCVTImmOperand()
6651 case ARM::MVE_VCVTf32u32_fix: in DecodeVCVTImmOperand()
6652 case ARM::MVE_VCVTu32f32_fix: in DecodeVCVTImmOperand()
6665 case ARM::VSTR_P0_off: in FixedRegForVSTRVLDR_SYSREG()
6666 case ARM::VSTR_P0_pre: in FixedRegForVSTRVLDR_SYSREG()
6667 case ARM::VSTR_P0_post: in FixedRegForVSTRVLDR_SYSREG()
6668 case ARM::VLDR_P0_off: in FixedRegForVSTRVLDR_SYSREG()
6669 case ARM::VLDR_P0_pre: in FixedRegForVSTRVLDR_SYSREG()
6670 case ARM::VLDR_P0_post: in FixedRegForVSTRVLDR_SYSREG()
6671 return ARM::P0; in FixedRegForVSTRVLDR_SYSREG()
6682 case ARM::VSTR_FPSCR_pre: in DecodeVSTRVLDR_SYSREG()
6683 case ARM::VSTR_FPSCR_NZCVQC_pre: in DecodeVSTRVLDR_SYSREG()
6684 case ARM::VLDR_FPSCR_pre: in DecodeVSTRVLDR_SYSREG()
6685 case ARM::VLDR_FPSCR_NZCVQC_pre: in DecodeVSTRVLDR_SYSREG()
6686 case ARM::VSTR_FPSCR_off: in DecodeVSTRVLDR_SYSREG()
6687 case ARM::VSTR_FPSCR_NZCVQC_off: in DecodeVSTRVLDR_SYSREG()
6688 case ARM::VLDR_FPSCR_off: in DecodeVSTRVLDR_SYSREG()
6689 case ARM::VLDR_FPSCR_NZCVQC_off: in DecodeVSTRVLDR_SYSREG()
6690 case ARM::VSTR_FPSCR_post: in DecodeVSTRVLDR_SYSREG()
6691 case ARM::VSTR_FPSCR_NZCVQC_post: in DecodeVSTRVLDR_SYSREG()
6692 case ARM::VLDR_FPSCR_post: in DecodeVSTRVLDR_SYSREG()
6693 case ARM::VLDR_FPSCR_NZCVQC_post: in DecodeVSTRVLDR_SYSREG()
6697 if (!featureBits[ARM::HasMVEIntegerOps] && !featureBits[ARM::FeatureVFP2]) in DecodeVSTRVLDR_SYSREG()
6863 case ARM::MVE_ASRLr: in DecodeMVEOverlappingLongShift()
6864 case ARM::MVE_SQRSHRL: in DecodeMVEOverlappingLongShift()
6865 Inst.setOpcode(ARM::MVE_SQRSHR); in DecodeMVEOverlappingLongShift()
6867 case ARM::MVE_LSLLr: in DecodeMVEOverlappingLongShift()
6868 case ARM::MVE_UQRSHLL: in DecodeMVEOverlappingLongShift()
6869 Inst.setOpcode(ARM::MVE_UQRSHL); in DecodeMVEOverlappingLongShift()
6915 if (Inst.getOpcode() == ARM::MVE_SQRSHRL || in DecodeMVEOverlappingLongShift()
6916 Inst.getOpcode() == ARM::MVE_UQRSHLL) { in DecodeMVEOverlappingLongShift()
6949 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeMVEVCMP()
6986 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeMveVCTP()
6997 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeMVEVPNOT()
6998 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeMVEVPNOT()
7024 Inst.setOpcode(sign1 ? ARM::t2SUBspImm12 : ARM::t2ADDspImm12); in DecodeT2AddSubSPImm()
7027 Inst.setOpcode(sign1 ? ARM::t2SUBspImm : ARM::t2ADDspImm); in DecodeT2AddSubSPImm()