Lines Matching refs:ARM
119 UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {} in UnwindContext()
175 FPReg = ARM::SP; in reset()
299 ITInst.setOpcode(ARM::t2IT); in flushPendingInstructions()
526 return getSTI().hasFeature(ARM::ModeThumb); in isThumb()
530 return isThumb() && !getSTI().hasFeature(ARM::FeatureThumb2); in isThumbOne()
534 return isThumb() && getSTI().hasFeature(ARM::FeatureThumb2); in isThumbTwo()
538 return getSTI().hasFeature(ARM::HasV4TOps); in hasThumb()
542 return getSTI().hasFeature(ARM::FeatureThumb2); in hasThumb2()
546 return getSTI().hasFeature(ARM::HasV6Ops); in hasV6Ops()
550 return getSTI().hasFeature(ARM::HasV6T2Ops); in hasV6T2Ops()
554 return getSTI().hasFeature(ARM::HasV6MOps); in hasV6MOps()
558 return getSTI().hasFeature(ARM::HasV7Ops); in hasV7Ops()
562 return getSTI().hasFeature(ARM::HasV8Ops); in hasV8Ops()
566 return getSTI().hasFeature(ARM::HasV8MBaselineOps); in hasV8MBaseline()
570 return getSTI().hasFeature(ARM::HasV8MMainlineOps); in hasV8MMainline()
573 return getSTI().hasFeature(ARM::HasV8_1MMainlineOps); in hasV8_1MMainline()
576 return getSTI().hasFeature(ARM::HasMVEFloatOps); in hasMVEFloat()
579 return getSTI().hasFeature(ARM::HasCDEOps); in hasCDE()
582 return getSTI().hasFeature(ARM::Feature8MSecExt); in has8MSecExt()
586 return !getSTI().hasFeature(ARM::FeatureNoARM); in hasARM()
590 return getSTI().hasFeature(ARM::FeatureDSP); in hasDSP()
594 return getSTI().hasFeature(ARM::FeatureD32); in hasD32()
598 return getSTI().hasFeature(ARM::HasV8_1aOps); in hasV8_1aOps()
602 return getSTI().hasFeature(ARM::FeatureRAS); in hasRAS()
607 auto FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb)); in SwitchMode()
614 return getSTI().hasFeature(ARM::FeatureMClass); in isMClass()
759 bool hasMVE() const { return getSTI().hasFeature(ARM::HasMVEIntegerOps); } in hasMVE()
763 return MRI->getSubReg(QReg, ARM::dsub_0); in getDRegFromQReg()
1148 if(Memory.BaseRegNum != ARM::PC) return false; in isThumbMemPC()
1373 ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg.RegNum); in isDReg()
1377 ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg.RegNum); in isQReg()
1394 !ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Memory.BaseRegNum) && in isMVEMem()
1395 !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(Memory.BaseRegNum)) in isMVEMem()
1398 !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains( in isMVEMem()
1407 !ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Memory.BaseRegNum)) in isGPRMem()
1410 !ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Memory.OffsetRegNum)) in isGPRMem()
1417 ARMMCRegisterClasses[ARM::GPRRegClassID].contains( in isRegShiftedReg()
1419 ARMMCRegisterClasses[ARM::GPRRegClassID].contains( in isRegShiftedReg()
1424 ARMMCRegisterClasses[ARM::GPRRegClassID].contains( in isRegShiftedImm()
1477 ARMMCRegisterClasses[ARM::GPRRegClassID].contains(PostIdxReg.RegNum); in isPostIdxRegShifted()
1493 if (!ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains( in isMemNoOffsetT2()
1505 if (!ARMMCRegisterClasses[ARM::rGPRRegClassID].contains( in isMemNoOffsetT2NoSp()
1517 if (!ARMMCRegisterClasses[ARM::tGPRRegClassID].contains( in isMemNoOffsetT()
1529 if (Memory.BaseRegNum != ARM::PC) in isMemPCRelImm12()
1736 Memory.Alignment != 0 || Memory.BaseRegNum == ARM::PC) in isT2MemRegOffset()
1797 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0) in isMemThumbSPI()
1834 !ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains( in isMemImm7s4Offset()
1863 if (Memory.BaseRegNum == ARM::PC) return false; in isMemImm8Offset()
1909 if (!ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains( in isMemRegRQOffset()
1912 if (!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains( in isMemRegRQOffset()
1930 if (!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains( in isMemRegQOffset()
1970 if (Memory.BaseRegNum == ARM::PC) return false; in isMemNegImm8Offset()
2069 ARMMCRegisterClasses[ARM::MQPRRegClassID].contains( in isVecListTwoMQ()
2079 return (ARMMCRegisterClasses[ARM::DPairRegClassID] in isVecListDPair()
2096 return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID] in isVecListDPairSpaced()
2112 ARMMCRegisterClasses[ARM::MQPRRegClassID].contains( in isVecListFourMQ()
2131 return (ARMMCRegisterClasses[ARM::DPairRegClassID] in isVecListDPairAllLanes()
2535 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; in addCondCodeOperands()
2542 unsigned RegNum = getVPTPred() == ARMVCC::None ? 0: ARM::P0; in addVPTPredNOperands()
3398 DPair, ARM::dsub_0, &ARMMCRegisterClasses[ARM::DPairRegClassID]); in addVecListOperands()
3424 const MCRegisterClass *RC_in = &ARMMCRegisterClasses[ARM::MQPRRegClassID]; in addMVEVecListOperands()
3426 (VectorList.Count == 2) ? &ARMMCRegisterClasses[ARM::MQQPRRegClassID] in addMVEVecListOperands()
3427 : &ARMMCRegisterClasses[ARM::MQQQQPRRegClassID]; in addMVEVecListOperands()
3521 assert((Inst.getOpcode() == ARM::VMOVv8i8 || in addNEONi8ReplicateOperands()
3522 Inst.getOpcode() == ARM::VMOVv16i8) && in addNEONi8ReplicateOperands()
3564 assert((Inst.getOpcode() == ARM::VMOVv4i16 || in addNEONvmovi16ReplicateOperands()
3565 Inst.getOpcode() == ARM::VMOVv8i16 || in addNEONvmovi16ReplicateOperands()
3566 Inst.getOpcode() == ARM::VMVNv4i16 || in addNEONvmovi16ReplicateOperands()
3567 Inst.getOpcode() == ARM::VMVNv8i16) && in addNEONvmovi16ReplicateOperands()
3588 assert((Inst.getOpcode() == ARM::VMOVv2i32 || in addNEONvmovi32ReplicateOperands()
3589 Inst.getOpcode() == ARM::VMOVv4i32 || in addNEONvmovi32ReplicateOperands()
3590 Inst.getOpcode() == ARM::VMVNv2i32 || in addNEONvmovi32ReplicateOperands()
3591 Inst.getOpcode() == ARM::VMVNv4i32) && in addNEONvmovi32ReplicateOperands()
3801 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains( in CreateRegList()
3803 if (Regs.back().second == ARM::VPR) in CreateRegList()
3807 } else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains( in CreateRegList()
3809 if (Regs.back().second == ARM::VPR) in CreateRegList()
3815 if (Kind == k_RegisterList && Regs.back().second == ARM::APSR) in CreateRegList()
4230 .Case("r13", ARM::SP) in tryParseRegister()
4231 .Case("r14", ARM::LR) in tryParseRegister()
4232 .Case("r15", ARM::PC) in tryParseRegister()
4233 .Case("ip", ARM::R12) in tryParseRegister()
4235 .Case("a1", ARM::R0) in tryParseRegister()
4236 .Case("a2", ARM::R1) in tryParseRegister()
4237 .Case("a3", ARM::R2) in tryParseRegister()
4238 .Case("a4", ARM::R3) in tryParseRegister()
4239 .Case("v1", ARM::R4) in tryParseRegister()
4240 .Case("v2", ARM::R5) in tryParseRegister()
4241 .Case("v3", ARM::R6) in tryParseRegister()
4242 .Case("v4", ARM::R7) in tryParseRegister()
4243 .Case("v5", ARM::R8) in tryParseRegister()
4244 .Case("v6", ARM::R9) in tryParseRegister()
4245 .Case("v7", ARM::R10) in tryParseRegister()
4246 .Case("v8", ARM::R11) in tryParseRegister()
4247 .Case("sb", ARM::R9) in tryParseRegister()
4248 .Case("sl", ARM::R10) in tryParseRegister()
4249 .Case("fp", ARM::R11) in tryParseRegister()
4265 if (!AllowOutOfBoundReg && !hasD32() && RegNum >= ARM::D16 && in tryParseRegister()
4266 RegNum <= ARM::D31) in tryParseRegister()
4577 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) in getNextRegister()
4581 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2; in getNextRegister()
4582 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4; in getNextRegister()
4583 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6; in getNextRegister()
4584 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8; in getNextRegister()
4585 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10; in getNextRegister()
4586 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12; in getNextRegister()
4587 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR; in getNextRegister()
4588 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0; in getNextRegister()
4625 if (!AllowRAAC && Reg == ARM::RA_AUTH_CODE) in parseRegisterList()
4633 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { in parseRegisterList()
4640 if (Reg == ARM::RA_AUTH_CODE || in parseRegisterList()
4641 ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) in parseRegisterList()
4642 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID]; in parseRegisterList()
4643 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) in parseRegisterList()
4644 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID]; in parseRegisterList()
4645 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg)) in parseRegisterList()
4646 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID]; in parseRegisterList()
4647 else if (ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains(Reg)) in parseRegisterList()
4648 RC = &ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID]; in parseRegisterList()
4662 if (Reg == ARM::RA_AUTH_CODE) in parseRegisterList()
4669 if (EndReg == ARM::RA_AUTH_CODE) in parseRegisterList()
4672 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) in parseRegisterList()
4704 if (!AllowRAAC && Reg == ARM::RA_AUTH_CODE) in parseRegisterList()
4708 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { in parseRegisterList()
4712 if (Reg != ARM::RA_AUTH_CODE && !RC->contains(Reg) && in parseRegisterList()
4713 RC->getID() == ARMMCRegisterClasses[ARM::GPRRegClassID].getID() && in parseRegisterList()
4714 ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains(Reg)) { in parseRegisterList()
4717 RC = &ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID]; in parseRegisterList()
4719 if (Reg == ARM::VPR && in parseRegisterList()
4720 (RC == &ARMMCRegisterClasses[ARM::SPRRegClassID] || in parseRegisterList()
4721 RC == &ARMMCRegisterClasses[ARM::DPRRegClassID] || in parseRegisterList()
4722 RC == &ARMMCRegisterClasses[ARM::FPWithVPRRegClassID])) { in parseRegisterList()
4723 RC = &ARMMCRegisterClasses[ARM::FPWithVPRRegClassID]; in parseRegisterList()
4732 if ((Reg == ARM::RA_AUTH_CODE && in parseRegisterList()
4733 RC != &ARMMCRegisterClasses[ARM::GPRRegClassID]) || in parseRegisterList()
4734 (Reg != ARM::RA_AUTH_CODE && !RC->contains(Reg))) in parseRegisterList()
4742 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) in parseRegisterList()
4744 else if (!ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains(Reg)) in parseRegisterList()
4748 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] && in parseRegisterList()
4749 RC != &ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID] && in parseRegisterList()
4841 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) { in parseVectorList()
4860 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { in parseVectorList()
4870 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0, in parseVectorList()
4871 &ARMMCRegisterClasses[ARM::DPairRegClassID]); in parseVectorList()
4899 if (hasMVE() && !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(Reg)) in parseVectorList()
4904 else if (!hasMVE() && ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { in parseVectorList()
4930 if (!hasMVE() && ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) in parseVectorList()
4938 !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(EndReg)) || in parseVectorList()
4940 !ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg))) in parseVectorList()
4966 if (!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(Reg)) in parseVectorList()
4976 else if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { in parseVectorList()
5030 &ARMMCRegisterClasses[ARM::DPairRegClassID] : in parseVectorList()
5031 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID]; in parseVectorList()
5032 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); in parseVectorList()
5855 case ARM::tBcc: Inst.setOpcode(ARM::tB); break; in cvtThumbBranches()
5856 case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break; in cvtThumbBranches()
5860 case ARM::tB: in cvtThumbBranches()
5861 case ARM::tBcc: in cvtThumbBranches()
5862 Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc); in cvtThumbBranches()
5864 case ARM::t2B: in cvtThumbBranches()
5865 case ARM::t2Bcc: in cvtThumbBranches()
5866 Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc); in cvtThumbBranches()
5874 case ARM::tB: { in cvtThumbBranches()
5877 Inst.setOpcode(ARM::t2B); in cvtThumbBranches()
5881 case ARM::tBcc: { in cvtThumbBranches()
5884 Inst.setOpcode(ARM::t2Bcc); in cvtThumbBranches()
6782 bool TryTransform = Op3Reg == ARM::PC || Op4Reg == ARM::PC || in tryConvertingToTwoOperandForm()
6783 (Op5.isReg() && Op5.getReg() == ARM::PC); in tryConvertingToTwoOperandForm()
6785 TryTransform = (Op3Reg == ARM::SP || Op4Reg == ARM::SP || in tryConvertingToTwoOperandForm()
6786 (Op5.isReg() && Op5.getReg() == ARM::SP)) && in tryConvertingToTwoOperandForm()
6787 !(Op3Reg == ARM::SP && Op4Reg == ARM::SP && in tryConvertingToTwoOperandForm()
6812 ((Mnemonic == "add" && Op4Reg != ARM::SP) || in tryConvertingToTwoOperandForm()
6881 (ARMMCRegisterClasses[ARM::SPRRegClassID].contains( in shouldOmitVectorPredicateOperand()
6883 ARMMCRegisterClasses[ARM::DPRRegClassID].contains( in shouldOmitVectorPredicateOperand()
6944 const MCRegisterClass &GPR = MRI->getRegClass(ARM::GPRRegClassID); in fixupGNULDRDAlias()
6954 if (Op2.getReg() == ARM::PC) in fixupGNULDRDAlias()
6957 if (!PairedReg || PairedReg == ARM::PC || in fixupGNULDRDAlias()
6958 (PairedReg == ARM::SP && !hasV8Ops())) in fixupGNULDRDAlias()
6991 case ARM::R0: in CDEConvertDualRegOperand()
6992 RNext = ARM::R1; in CDEConvertDualRegOperand()
6993 RPair = ARM::R0_R1; in CDEConvertDualRegOperand()
6995 case ARM::R2: in CDEConvertDualRegOperand()
6996 RNext = ARM::R3; in CDEConvertDualRegOperand()
6997 RPair = ARM::R2_R3; in CDEConvertDualRegOperand()
6999 case ARM::R4: in CDEConvertDualRegOperand()
7000 RNext = ARM::R5; in CDEConvertDualRegOperand()
7001 RPair = ARM::R4_R5; in CDEConvertDualRegOperand()
7003 case ARM::R6: in CDEConvertDualRegOperand()
7004 RNext = ARM::R7; in CDEConvertDualRegOperand()
7005 RPair = ARM::R6_R7; in CDEConvertDualRegOperand()
7007 case ARM::R8: in CDEConvertDualRegOperand()
7008 RNext = ARM::R9; in CDEConvertDualRegOperand()
7009 RPair = ARM::R8_R9; in CDEConvertDualRegOperand()
7011 case ARM::R10: in CDEConvertDualRegOperand()
7012 RNext = ARM::R11; in CDEConvertDualRegOperand()
7013 RPair = ARM::R10_R11; in CDEConvertDualRegOperand()
7169 ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0, Loc, *this)); in ParseInstruction()
7409 const MCRegisterClass &MRC = MRI->getRegClass(ARM::GPRRegClassID); in ParseInstruction()
7430 Reg1, ARM::gsub_0, &(MRI->getRegClass(ARM::GPRPairRegClassID))); in ParseInstruction()
7446 ARM::PC && in ParseInstruction()
7449 ARM::LR && in ParseInstruction()
7491 return Inst.getOpcode() == ARM::tBKPT || in instIsBreakpoint()
7492 Inst.getOpcode() == ARM::BKPT || in instIsBreakpoint()
7493 Inst.getOpcode() == ARM::tHLT || in instIsBreakpoint()
7494 Inst.getOpcode() == ARM::HLT; in instIsBreakpoint()
7512 bool ListContainsSP = listContainsReg(Inst, ListIndex, ARM::SP); in validatetLDMRegList()
7513 bool ListContainsLR = listContainsReg(Inst, ListIndex, ARM::LR); in validatetLDMRegList()
7514 bool ListContainsPC = listContainsReg(Inst, ListIndex, ARM::PC); in validatetLDMRegList()
7531 bool ListContainsSP = listContainsReg(Inst, ListIndex, ARM::SP); in validatetSTMRegList()
7532 bool ListContainsPC = listContainsReg(Inst, ListIndex, ARM::PC); in validatetSTMRegList()
7609 if (ARM::isVpred(MCID.operands()[i].OperandType)) in findFirstVectorPredOperandIdx()
7662 ARMCC::AL && Inst.getOpcode() != ARM::tBcc && in validateInstruction()
7663 Inst.getOpcode() != ARM::t2Bcc && in validateInstruction()
7664 Inst.getOpcode() != ARM::t2BFic) { in validateInstruction()
7714 case ARM::VLLDM: in validateInstruction()
7715 case ARM::VLLDM_T2: in validateInstruction()
7716 case ARM::VLSTM: in validateInstruction()
7717 case ARM::VLSTM_T2: { in validateInstruction()
7742 case ARM::t2IT: { in validateInstruction()
7756 case ARM::LDRD: in validateInstruction()
7761 case ARM::LDRD_PRE: in validateInstruction()
7762 case ARM::LDRD_POST: in validateInstruction()
7767 case ARM::t2LDRDi8: in validateInstruction()
7772 case ARM::t2LDRD_PRE: in validateInstruction()
7773 case ARM::t2LDRD_POST: in validateInstruction()
7778 case ARM::t2BXJ: { in validateInstruction()
7781 if (RmReg == ARM::SP && !hasV8Ops()) in validateInstruction()
7786 case ARM::STRD: in validateInstruction()
7791 case ARM::STRD_PRE: in validateInstruction()
7792 case ARM::STRD_POST: in validateInstruction()
7797 case ARM::t2STRD_PRE: in validateInstruction()
7798 case ARM::t2STRD_POST: in validateInstruction()
7803 case ARM::STR_PRE_IMM: in validateInstruction()
7804 case ARM::STR_PRE_REG: in validateInstruction()
7805 case ARM::t2STR_PRE: in validateInstruction()
7806 case ARM::STR_POST_IMM: in validateInstruction()
7807 case ARM::STR_POST_REG: in validateInstruction()
7808 case ARM::t2STR_POST: in validateInstruction()
7809 case ARM::STRH_PRE: in validateInstruction()
7810 case ARM::t2STRH_PRE: in validateInstruction()
7811 case ARM::STRH_POST: in validateInstruction()
7812 case ARM::t2STRH_POST: in validateInstruction()
7813 case ARM::STRB_PRE_IMM: in validateInstruction()
7814 case ARM::STRB_PRE_REG: in validateInstruction()
7815 case ARM::t2STRB_PRE: in validateInstruction()
7816 case ARM::STRB_POST_IMM: in validateInstruction()
7817 case ARM::STRB_POST_REG: in validateInstruction()
7818 case ARM::t2STRB_POST: { in validateInstruction()
7828 case ARM::t2LDR_PRE_imm: in validateInstruction()
7829 case ARM::t2LDR_POST_imm: in validateInstruction()
7830 case ARM::t2STR_PRE_imm: in validateInstruction()
7831 case ARM::t2STR_POST_imm: { in validateInstruction()
7839 if (Inst.getOpcode() == ARM::t2LDR_POST_imm || in validateInstruction()
7840 Inst.getOpcode() == ARM::t2STR_POST_imm) { in validateInstruction()
7846 if (Inst.getOpcode() == ARM::t2STR_PRE_imm || in validateInstruction()
7847 Inst.getOpcode() == ARM::t2STR_POST_imm) { in validateInstruction()
7848 if (Inst.getOperand(0).getReg() == ARM::PC) { in validateInstruction()
7856 case ARM::t2LDRB_OFFSET_imm: in validateInstruction()
7857 case ARM::t2LDRB_PRE_imm: in validateInstruction()
7858 case ARM::t2LDRB_POST_imm: in validateInstruction()
7859 case ARM::t2STRB_OFFSET_imm: in validateInstruction()
7860 case ARM::t2STRB_PRE_imm: in validateInstruction()
7861 case ARM::t2STRB_POST_imm: { in validateInstruction()
7862 if (Inst.getOpcode() == ARM::t2LDRB_POST_imm || in validateInstruction()
7863 Inst.getOpcode() == ARM::t2STRB_POST_imm || in validateInstruction()
7864 Inst.getOpcode() == ARM::t2LDRB_PRE_imm || in validateInstruction()
7865 Inst.getOpcode() == ARM::t2STRB_PRE_imm) { in validateInstruction()
7870 } else if (Inst.getOpcode() == ARM::t2LDRB_OFFSET_imm || in validateInstruction()
7871 Inst.getOpcode() == ARM::t2STRB_OFFSET_imm) { in validateInstruction()
7877 if (Inst.getOperand(0).getReg() == ARM::PC) { in validateInstruction()
7884 case ARM::t2LDRH_OFFSET_imm: in validateInstruction()
7885 case ARM::t2LDRH_PRE_imm: in validateInstruction()
7886 case ARM::t2LDRH_POST_imm: in validateInstruction()
7887 case ARM::t2STRH_OFFSET_imm: in validateInstruction()
7888 case ARM::t2STRH_PRE_imm: in validateInstruction()
7889 case ARM::t2STRH_POST_imm: { in validateInstruction()
7890 if (Inst.getOpcode() == ARM::t2LDRH_POST_imm || in validateInstruction()
7891 Inst.getOpcode() == ARM::t2STRH_POST_imm || in validateInstruction()
7892 Inst.getOpcode() == ARM::t2LDRH_PRE_imm || in validateInstruction()
7893 Inst.getOpcode() == ARM::t2STRH_PRE_imm) { in validateInstruction()
7898 } else if (Inst.getOpcode() == ARM::t2LDRH_OFFSET_imm || in validateInstruction()
7899 Inst.getOpcode() == ARM::t2STRH_OFFSET_imm) { in validateInstruction()
7905 if (Inst.getOperand(0).getReg() == ARM::PC) { in validateInstruction()
7912 case ARM::t2LDRSB_OFFSET_imm: in validateInstruction()
7913 case ARM::t2LDRSB_PRE_imm: in validateInstruction()
7914 case ARM::t2LDRSB_POST_imm: { in validateInstruction()
7915 if (Inst.getOpcode() == ARM::t2LDRSB_POST_imm || in validateInstruction()
7916 Inst.getOpcode() == ARM::t2LDRSB_PRE_imm) { in validateInstruction()
7921 } else if (Inst.getOpcode() == ARM::t2LDRSB_OFFSET_imm) { in validateInstruction()
7927 if (Inst.getOperand(0).getReg() == ARM::PC) { in validateInstruction()
7934 case ARM::t2LDRSH_OFFSET_imm: in validateInstruction()
7935 case ARM::t2LDRSH_PRE_imm: in validateInstruction()
7936 case ARM::t2LDRSH_POST_imm: { in validateInstruction()
7937 if (Inst.getOpcode() == ARM::t2LDRSH_POST_imm || in validateInstruction()
7938 Inst.getOpcode() == ARM::t2LDRSH_PRE_imm) { in validateInstruction()
7943 } else if (Inst.getOpcode() == ARM::t2LDRSH_OFFSET_imm) { in validateInstruction()
7949 if (Inst.getOperand(0).getReg() == ARM::PC) { in validateInstruction()
7956 case ARM::LDR_PRE_IMM: in validateInstruction()
7957 case ARM::LDR_PRE_REG: in validateInstruction()
7958 case ARM::t2LDR_PRE: in validateInstruction()
7959 case ARM::LDR_POST_IMM: in validateInstruction()
7960 case ARM::LDR_POST_REG: in validateInstruction()
7961 case ARM::t2LDR_POST: in validateInstruction()
7962 case ARM::LDRH_PRE: in validateInstruction()
7963 case ARM::t2LDRH_PRE: in validateInstruction()
7964 case ARM::LDRH_POST: in validateInstruction()
7965 case ARM::t2LDRH_POST: in validateInstruction()
7966 case ARM::LDRSH_PRE: in validateInstruction()
7967 case ARM::t2LDRSH_PRE: in validateInstruction()
7968 case ARM::LDRSH_POST: in validateInstruction()
7969 case ARM::t2LDRSH_POST: in validateInstruction()
7970 case ARM::LDRB_PRE_IMM: in validateInstruction()
7971 case ARM::LDRB_PRE_REG: in validateInstruction()
7972 case ARM::t2LDRB_PRE: in validateInstruction()
7973 case ARM::LDRB_POST_IMM: in validateInstruction()
7974 case ARM::LDRB_POST_REG: in validateInstruction()
7975 case ARM::t2LDRB_POST: in validateInstruction()
7976 case ARM::LDRSB_PRE: in validateInstruction()
7977 case ARM::t2LDRSB_PRE: in validateInstruction()
7978 case ARM::LDRSB_POST: in validateInstruction()
7979 case ARM::t2LDRSB_POST: { in validateInstruction()
7990 case ARM::MVE_VLDRBU8_rq: in validateInstruction()
7991 case ARM::MVE_VLDRBU16_rq: in validateInstruction()
7992 case ARM::MVE_VLDRBS16_rq: in validateInstruction()
7993 case ARM::MVE_VLDRBU32_rq: in validateInstruction()
7994 case ARM::MVE_VLDRBS32_rq: in validateInstruction()
7995 case ARM::MVE_VLDRHU16_rq: in validateInstruction()
7996 case ARM::MVE_VLDRHU16_rq_u: in validateInstruction()
7997 case ARM::MVE_VLDRHU32_rq: in validateInstruction()
7998 case ARM::MVE_VLDRHU32_rq_u: in validateInstruction()
7999 case ARM::MVE_VLDRHS32_rq: in validateInstruction()
8000 case ARM::MVE_VLDRHS32_rq_u: in validateInstruction()
8001 case ARM::MVE_VLDRWU32_rq: in validateInstruction()
8002 case ARM::MVE_VLDRWU32_rq_u: in validateInstruction()
8003 case ARM::MVE_VLDRDU64_rq: in validateInstruction()
8004 case ARM::MVE_VLDRDU64_rq_u: in validateInstruction()
8005 case ARM::MVE_VLDRWU32_qi: in validateInstruction()
8006 case ARM::MVE_VLDRWU32_qi_pre: in validateInstruction()
8007 case ARM::MVE_VLDRDU64_qi: in validateInstruction()
8008 case ARM::MVE_VLDRDU64_qi_pre: { in validateInstruction()
8013 case ARM::MVE_VLDRWU32_qi: in validateInstruction()
8014 case ARM::MVE_VLDRDU64_qi: in validateInstruction()
8018 case ARM::MVE_VLDRWU32_qi_pre: in validateInstruction()
8019 case ARM::MVE_VLDRDU64_qi_pre: in validateInstruction()
8037 case ARM::SBFX: in validateInstruction()
8038 case ARM::t2SBFX: in validateInstruction()
8039 case ARM::UBFX: in validateInstruction()
8040 case ARM::t2UBFX: { in validateInstruction()
8050 case ARM::tLDMIA: { in validateInstruction()
8085 case ARM::LDMIA_UPD: in validateInstruction()
8086 case ARM::LDMDB_UPD: in validateInstruction()
8087 case ARM::LDMIB_UPD: in validateInstruction()
8088 case ARM::LDMDA_UPD: in validateInstruction()
8097 case ARM::t2LDMIA: in validateInstruction()
8098 case ARM::t2LDMDB: in validateInstruction()
8102 case ARM::t2STMIA: in validateInstruction()
8103 case ARM::t2STMDB: in validateInstruction()
8107 case ARM::t2LDMIA_UPD: in validateInstruction()
8108 case ARM::t2LDMDB_UPD: in validateInstruction()
8109 case ARM::t2STMIA_UPD: in validateInstruction()
8110 case ARM::t2STMDB_UPD: in validateInstruction()
8115 if (Opcode == ARM::t2LDMIA_UPD || Opcode == ARM::t2LDMDB_UPD) { in validateInstruction()
8124 case ARM::sysLDMIA_UPD: in validateInstruction()
8125 case ARM::sysLDMDA_UPD: in validateInstruction()
8126 case ARM::sysLDMDB_UPD: in validateInstruction()
8127 case ARM::sysLDMIB_UPD: in validateInstruction()
8128 if (!listContainsReg(Inst, 3, ARM::PC)) in validateInstruction()
8133 case ARM::sysSTMIA_UPD: in validateInstruction()
8134 case ARM::sysSTMDA_UPD: in validateInstruction()
8135 case ARM::sysSTMDB_UPD: in validateInstruction()
8136 case ARM::sysSTMIB_UPD: in validateInstruction()
8142 case ARM::tPOP: { in validateInstruction()
8144 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, ListContainsBase) && in validateInstruction()
8152 case ARM::tPUSH: { in validateInstruction()
8154 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, ListContainsBase) && in validateInstruction()
8162 case ARM::tSTMIA_UPD: { in validateInstruction()
8181 case ARM::tADDrSP: in validateInstruction()
8191 case ARM::t2ADDrr: in validateInstruction()
8192 case ARM::t2ADDrs: in validateInstruction()
8193 case ARM::t2SUBrr: in validateInstruction()
8194 case ARM::t2SUBrs: in validateInstruction()
8195 if (Inst.getOperand(0).getReg() == ARM::SP && in validateInstruction()
8196 Inst.getOperand(1).getReg() != ARM::SP) in validateInstruction()
8202 case ARM::tB: in validateInstruction()
8208 case ARM::t2B: { in validateInstruction()
8219 case ARM::tBcc: in validateInstruction()
8225 case ARM::t2Bcc: { in validateInstruction()
8232 case ARM::tCBZ: in validateInstruction()
8233 case ARM::tCBNZ: { in validateInstruction()
8240 case ARM::MOVi16: in validateInstruction()
8241 case ARM::MOVTi16: in validateInstruction()
8242 case ARM::t2MOVi16: in validateInstruction()
8243 case ARM::t2MOVTi16: in validateInstruction()
8266 case ARM::tADDi8: { in validateInstruction()
8274 case ARM::tMOVi8: { in validateInstruction()
8282 case ARM::HINT: in validateInstruction()
8283 case ARM::t2HINT: { in validateInstruction()
8298 case ARM::t2BFi: in validateInstruction()
8299 case ARM::t2BFr: in validateInstruction()
8300 case ARM::t2BFLi: in validateInstruction()
8301 case ARM::t2BFLr: { in validateInstruction()
8309 if (Opcode == ARM::t2BFi) { in validateInstruction()
8314 } else if (Opcode == ARM::t2BFLi) { in validateInstruction()
8322 case ARM::t2BFic: { in validateInstruction()
8347 case ARM::t2CLRM: { in validateInstruction()
8350 !ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains( in validateInstruction()
8359 case ARM::DSB: in validateInstruction()
8360 case ARM::t2DSB: { in validateInstruction()
8379 case ARM::VMOVRRS: { in validateInstruction()
8388 case ARM::VMOVSRR: { in validateInstruction()
8397 case ARM::VLDMDIA: in validateInstruction()
8398 case ARM::VSTMDIA: { in validateInstruction()
8407 case ARM::MVE_VQDMULLs32bh: in validateInstruction()
8408 case ARM::MVE_VQDMULLs32th: in validateInstruction()
8409 case ARM::MVE_VCMULf32: in validateInstruction()
8410 case ARM::MVE_VMULLBs32: in validateInstruction()
8411 case ARM::MVE_VMULLTs32: in validateInstruction()
8412 case ARM::MVE_VMULLBu32: in validateInstruction()
8413 case ARM::MVE_VMULLTu32: { in validateInstruction()
8426 case ARM::MVE_VREV64_8: in validateInstruction()
8427 case ARM::MVE_VREV64_16: in validateInstruction()
8428 case ARM::MVE_VREV64_32: in validateInstruction()
8429 case ARM::MVE_VQDMULL_qr_s32bh: in validateInstruction()
8430 case ARM::MVE_VQDMULL_qr_s32th: { in validateInstruction()
8438 case ARM::MVE_VCADDi32: in validateInstruction()
8439 case ARM::MVE_VCADDf32: in validateInstruction()
8440 case ARM::MVE_VHCADDs32: { in validateInstruction()
8448 case ARM::MVE_VMOV_rr_q: { in validateInstruction()
8462 case ARM::MVE_VMOV_q_rr: { in validateInstruction()
8476 case ARM::MVE_SQRSHR: in validateInstruction()
8477 case ARM::MVE_UQRSHL: { in validateInstruction()
8485 case ARM::UMAAL: in validateInstruction()
8486 case ARM::UMLAL: in validateInstruction()
8487 case ARM::UMULL: in validateInstruction()
8488 case ARM::t2UMAAL: in validateInstruction()
8489 case ARM::t2UMLAL: in validateInstruction()
8490 case ARM::t2UMULL: in validateInstruction()
8491 case ARM::SMLAL: in validateInstruction()
8492 case ARM::SMLALBB: in validateInstruction()
8493 case ARM::SMLALBT: in validateInstruction()
8494 case ARM::SMLALD: in validateInstruction()
8495 case ARM::SMLALDX: in validateInstruction()
8496 case ARM::SMLALTB: in validateInstruction()
8497 case ARM::SMLALTT: in validateInstruction()
8498 case ARM::SMLSLD: in validateInstruction()
8499 case ARM::SMLSLDX: in validateInstruction()
8500 case ARM::SMULL: in validateInstruction()
8501 case ARM::t2SMLAL: in validateInstruction()
8502 case ARM::t2SMLALBB: in validateInstruction()
8503 case ARM::t2SMLALBT: in validateInstruction()
8504 case ARM::t2SMLALD: in validateInstruction()
8505 case ARM::t2SMLALDX: in validateInstruction()
8506 case ARM::t2SMLALTB: in validateInstruction()
8507 case ARM::t2SMLALTT: in validateInstruction()
8508 case ARM::t2SMLSLD: in validateInstruction()
8509 case ARM::t2SMLSLDX: in validateInstruction()
8510 case ARM::t2SMULL: { in validateInstruction()
8520 case ARM::CDE_CX1: in validateInstruction()
8521 case ARM::CDE_CX1A: in validateInstruction()
8522 case ARM::CDE_CX1D: in validateInstruction()
8523 case ARM::CDE_CX1DA: in validateInstruction()
8524 case ARM::CDE_CX2: in validateInstruction()
8525 case ARM::CDE_CX2A: in validateInstruction()
8526 case ARM::CDE_CX2D: in validateInstruction()
8527 case ARM::CDE_CX2DA: in validateInstruction()
8528 case ARM::CDE_CX3: in validateInstruction()
8529 case ARM::CDE_CX3A: in validateInstruction()
8530 case ARM::CDE_CX3D: in validateInstruction()
8531 case ARM::CDE_CX3DA: in validateInstruction()
8532 case ARM::CDE_VCX1_vec: in validateInstruction()
8533 case ARM::CDE_VCX1_fpsp: in validateInstruction()
8534 case ARM::CDE_VCX1_fpdp: in validateInstruction()
8535 case ARM::CDE_VCX1A_vec: in validateInstruction()
8536 case ARM::CDE_VCX1A_fpsp: in validateInstruction()
8537 case ARM::CDE_VCX1A_fpdp: in validateInstruction()
8538 case ARM::CDE_VCX2_vec: in validateInstruction()
8539 case ARM::CDE_VCX2_fpsp: in validateInstruction()
8540 case ARM::CDE_VCX2_fpdp: in validateInstruction()
8541 case ARM::CDE_VCX2A_vec: in validateInstruction()
8542 case ARM::CDE_VCX2A_fpsp: in validateInstruction()
8543 case ARM::CDE_VCX2A_fpdp: in validateInstruction()
8544 case ARM::CDE_VCX3_vec: in validateInstruction()
8545 case ARM::CDE_VCX3_fpsp: in validateInstruction()
8546 case ARM::CDE_VCX3_fpdp: in validateInstruction()
8547 case ARM::CDE_VCX3A_vec: in validateInstruction()
8548 case ARM::CDE_VCX3A_fpsp: in validateInstruction()
8549 case ARM::CDE_VCX3A_fpdp: { in validateInstruction()
8553 if (Coproc < 8 && !ARM::isCDECoproc(Coproc, *STI)) in validateInstruction()
8562 case ARM::t2CDP: in validateInstruction()
8563 case ARM::t2CDP2: in validateInstruction()
8564 case ARM::t2LDC2L_OFFSET: in validateInstruction()
8565 case ARM::t2LDC2L_OPTION: in validateInstruction()
8566 case ARM::t2LDC2L_POST: in validateInstruction()
8567 case ARM::t2LDC2L_PRE: in validateInstruction()
8568 case ARM::t2LDC2_OFFSET: in validateInstruction()
8569 case ARM::t2LDC2_OPTION: in validateInstruction()
8570 case ARM::t2LDC2_POST: in validateInstruction()
8571 case ARM::t2LDC2_PRE: in validateInstruction()
8572 case ARM::t2LDCL_OFFSET: in validateInstruction()
8573 case ARM::t2LDCL_OPTION: in validateInstruction()
8574 case ARM::t2LDCL_POST: in validateInstruction()
8575 case ARM::t2LDCL_PRE: in validateInstruction()
8576 case ARM::t2LDC_OFFSET: in validateInstruction()
8577 case ARM::t2LDC_OPTION: in validateInstruction()
8578 case ARM::t2LDC_POST: in validateInstruction()
8579 case ARM::t2LDC_PRE: in validateInstruction()
8580 case ARM::t2MCR: in validateInstruction()
8581 case ARM::t2MCR2: in validateInstruction()
8582 case ARM::t2MCRR: in validateInstruction()
8583 case ARM::t2MCRR2: in validateInstruction()
8584 case ARM::t2MRC: in validateInstruction()
8585 case ARM::t2MRC2: in validateInstruction()
8586 case ARM::t2MRRC: in validateInstruction()
8587 case ARM::t2MRRC2: in validateInstruction()
8588 case ARM::t2STC2L_OFFSET: in validateInstruction()
8589 case ARM::t2STC2L_OPTION: in validateInstruction()
8590 case ARM::t2STC2L_POST: in validateInstruction()
8591 case ARM::t2STC2L_PRE: in validateInstruction()
8592 case ARM::t2STC2_OFFSET: in validateInstruction()
8593 case ARM::t2STC2_OPTION: in validateInstruction()
8594 case ARM::t2STC2_POST: in validateInstruction()
8595 case ARM::t2STC2_PRE: in validateInstruction()
8596 case ARM::t2STCL_OFFSET: in validateInstruction()
8597 case ARM::t2STCL_OPTION: in validateInstruction()
8598 case ARM::t2STCL_POST: in validateInstruction()
8599 case ARM::t2STCL_PRE: in validateInstruction()
8600 case ARM::t2STC_OFFSET: in validateInstruction()
8601 case ARM::t2STC_OPTION: in validateInstruction()
8602 case ARM::t2STC_POST: in validateInstruction()
8603 case ARM::t2STC_PRE: { in validateInstruction()
8608 if (Opcode == ARM::t2MRRC || Opcode == ARM::t2MRRC2) in validateInstruction()
8610 else if (Opcode == ARM::t2MRC || Opcode == ARM::t2MRC2) in validateInstruction()
8616 if (ARM::isCDECoproc(Coproc, *STI)) in validateInstruction()
8630 case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD; in getRealVSTOpcode()
8631 case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD; in getRealVSTOpcode()
8632 case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD; in getRealVSTOpcode()
8633 case ARM::VST1LNdWB_register_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD; in getRealVSTOpcode()
8634 case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD; in getRealVSTOpcode()
8635 case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD; in getRealVSTOpcode()
8636 case ARM::VST1LNdAsm_8: Spacing = 1; return ARM::VST1LNd8; in getRealVSTOpcode()
8637 case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16; in getRealVSTOpcode()
8638 case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32; in getRealVSTOpcode()
8641 case ARM::VST2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD; in getRealVSTOpcode()
8642 case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD; in getRealVSTOpcode()
8643 case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD; in getRealVSTOpcode()
8644 case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD; in getRealVSTOpcode()
8645 case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD; in getRealVSTOpcode()
8647 case ARM::VST2LNdWB_register_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD; in getRealVSTOpcode()
8648 case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD; in getRealVSTOpcode()
8649 case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD; in getRealVSTOpcode()
8650 case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD; in getRealVSTOpcode()
8651 case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD; in getRealVSTOpcode()
8653 case ARM::VST2LNdAsm_8: Spacing = 1; return ARM::VST2LNd8; in getRealVSTOpcode()
8654 case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16; in getRealVSTOpcode()
8655 case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32; in getRealVSTOpcode()
8656 case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16; in getRealVSTOpcode()
8657 case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32; in getRealVSTOpcode()
8660 case ARM::VST3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD; in getRealVSTOpcode()
8661 case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD; in getRealVSTOpcode()
8662 case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD; in getRealVSTOpcode()
8663 case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD; in getRealVSTOpcode()
8664 case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD; in getRealVSTOpcode()
8665 case ARM::VST3LNdWB_register_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD; in getRealVSTOpcode()
8666 case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD; in getRealVSTOpcode()
8667 case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD; in getRealVSTOpcode()
8668 case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD; in getRealVSTOpcode()
8669 case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD; in getRealVSTOpcode()
8670 case ARM::VST3LNdAsm_8: Spacing = 1; return ARM::VST3LNd8; in getRealVSTOpcode()
8671 case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16; in getRealVSTOpcode()
8672 case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32; in getRealVSTOpcode()
8673 case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16; in getRealVSTOpcode()
8674 case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32; in getRealVSTOpcode()
8677 case ARM::VST3dWB_fixed_Asm_8: Spacing = 1; return ARM::VST3d8_UPD; in getRealVSTOpcode()
8678 case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD; in getRealVSTOpcode()
8679 case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD; in getRealVSTOpcode()
8680 case ARM::VST3qWB_fixed_Asm_8: Spacing = 2; return ARM::VST3q8_UPD; in getRealVSTOpcode()
8681 case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD; in getRealVSTOpcode()
8682 case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD; in getRealVSTOpcode()
8683 case ARM::VST3dWB_register_Asm_8: Spacing = 1; return ARM::VST3d8_UPD; in getRealVSTOpcode()
8684 case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD; in getRealVSTOpcode()
8685 case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD; in getRealVSTOpcode()
8686 case ARM::VST3qWB_register_Asm_8: Spacing = 2; return ARM::VST3q8_UPD; in getRealVSTOpcode()
8687 case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD; in getRealVSTOpcode()
8688 case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD; in getRealVSTOpcode()
8689 case ARM::VST3dAsm_8: Spacing = 1; return ARM::VST3d8; in getRealVSTOpcode()
8690 case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16; in getRealVSTOpcode()
8691 case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32; in getRealVSTOpcode()
8692 case ARM::VST3qAsm_8: Spacing = 2; return ARM::VST3q8; in getRealVSTOpcode()
8693 case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16; in getRealVSTOpcode()
8694 case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32; in getRealVSTOpcode()
8697 case ARM::VST4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD; in getRealVSTOpcode()
8698 case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD; in getRealVSTOpcode()
8699 case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD; in getRealVSTOpcode()
8700 case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD; in getRealVSTOpcode()
8701 case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD; in getRealVSTOpcode()
8702 case ARM::VST4LNdWB_register_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD; in getRealVSTOpcode()
8703 case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD; in getRealVSTOpcode()
8704 case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD; in getRealVSTOpcode()
8705 case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD; in getRealVSTOpcode()
8706 case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD; in getRealVSTOpcode()
8707 case ARM::VST4LNdAsm_8: Spacing = 1; return ARM::VST4LNd8; in getRealVSTOpcode()
8708 case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16; in getRealVSTOpcode()
8709 case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32; in getRealVSTOpcode()
8710 case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16; in getRealVSTOpcode()
8711 case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32; in getRealVSTOpcode()
8714 case ARM::VST4dWB_fixed_Asm_8: Spacing = 1; return ARM::VST4d8_UPD; in getRealVSTOpcode()
8715 case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD; in getRealVSTOpcode()
8716 case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD; in getRealVSTOpcode()
8717 case ARM::VST4qWB_fixed_Asm_8: Spacing = 2; return ARM::VST4q8_UPD; in getRealVSTOpcode()
8718 case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD; in getRealVSTOpcode()
8719 case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD; in getRealVSTOpcode()
8720 case ARM::VST4dWB_register_Asm_8: Spacing = 1; return ARM::VST4d8_UPD; in getRealVSTOpcode()
8721 case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD; in getRealVSTOpcode()
8722 case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD; in getRealVSTOpcode()
8723 case ARM::VST4qWB_register_Asm_8: Spacing = 2; return ARM::VST4q8_UPD; in getRealVSTOpcode()
8724 case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD; in getRealVSTOpcode()
8725 case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD; in getRealVSTOpcode()
8726 case ARM::VST4dAsm_8: Spacing = 1; return ARM::VST4d8; in getRealVSTOpcode()
8727 case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16; in getRealVSTOpcode()
8728 case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32; in getRealVSTOpcode()
8729 case ARM::VST4qAsm_8: Spacing = 2; return ARM::VST4q8; in getRealVSTOpcode()
8730 case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16; in getRealVSTOpcode()
8731 case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32; in getRealVSTOpcode()
8739 case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD; in getRealVLDOpcode()
8740 case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD; in getRealVLDOpcode()
8741 case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD; in getRealVLDOpcode()
8742 case ARM::VLD1LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD; in getRealVLDOpcode()
8743 case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD; in getRealVLDOpcode()
8744 case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD; in getRealVLDOpcode()
8745 case ARM::VLD1LNdAsm_8: Spacing = 1; return ARM::VLD1LNd8; in getRealVLDOpcode()
8746 case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16; in getRealVLDOpcode()
8747 case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32; in getRealVLDOpcode()
8750 case ARM::VLD2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD; in getRealVLDOpcode()
8751 case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD; in getRealVLDOpcode()
8752 case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD; in getRealVLDOpcode()
8753 case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD; in getRealVLDOpcode()
8754 case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD; in getRealVLDOpcode()
8755 case ARM::VLD2LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD; in getRealVLDOpcode()
8756 case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD; in getRealVLDOpcode()
8757 case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD; in getRealVLDOpcode()
8758 case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD; in getRealVLDOpcode()
8759 case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD; in getRealVLDOpcode()
8760 case ARM::VLD2LNdAsm_8: Spacing = 1; return ARM::VLD2LNd8; in getRealVLDOpcode()
8761 case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16; in getRealVLDOpcode()
8762 case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32; in getRealVLDOpcode()
8763 case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16; in getRealVLDOpcode()
8764 case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32; in getRealVLDOpcode()
8767 case ARM::VLD3DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD; in getRealVLDOpcode()
8768 case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD; in getRealVLDOpcode()
8769 case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD; in getRealVLDOpcode()
8770 case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD; in getRealVLDOpcode()
8771 case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD; in getRealVLDOpcode()
8772 case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD; in getRealVLDOpcode()
8773 case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD; in getRealVLDOpcode()
8774 case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD; in getRealVLDOpcode()
8775 case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD; in getRealVLDOpcode()
8776 case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD; in getRealVLDOpcode()
8777 case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD; in getRealVLDOpcode()
8778 case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD; in getRealVLDOpcode()
8779 case ARM::VLD3DUPdAsm_8: Spacing = 1; return ARM::VLD3DUPd8; in getRealVLDOpcode()
8780 case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16; in getRealVLDOpcode()
8781 case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32; in getRealVLDOpcode()
8782 case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8; in getRealVLDOpcode()
8783 case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16; in getRealVLDOpcode()
8784 case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32; in getRealVLDOpcode()
8787 case ARM::VLD3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD; in getRealVLDOpcode()
8788 case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD; in getRealVLDOpcode()
8789 case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD; in getRealVLDOpcode()
8790 case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD; in getRealVLDOpcode()
8791 case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD; in getRealVLDOpcode()
8792 case ARM::VLD3LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD; in getRealVLDOpcode()
8793 case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD; in getRealVLDOpcode()
8794 case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD; in getRealVLDOpcode()
8795 case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD; in getRealVLDOpcode()
8796 case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD; in getRealVLDOpcode()
8797 case ARM::VLD3LNdAsm_8: Spacing = 1; return ARM::VLD3LNd8; in getRealVLDOpcode()
8798 case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16; in getRealVLDOpcode()
8799 case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32; in getRealVLDOpcode()
8800 case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16; in getRealVLDOpcode()
8801 case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32; in getRealVLDOpcode()
8804 case ARM::VLD3dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD; in getRealVLDOpcode()
8805 case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD; in getRealVLDOpcode()
8806 case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD; in getRealVLDOpcode()
8807 case ARM::VLD3qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD; in getRealVLDOpcode()
8808 case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD; in getRealVLDOpcode()
8809 case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD; in getRealVLDOpcode()
8810 case ARM::VLD3dWB_register_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD; in getRealVLDOpcode()
8811 case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD; in getRealVLDOpcode()
8812 case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD; in getRealVLDOpcode()
8813 case ARM::VLD3qWB_register_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD; in getRealVLDOpcode()
8814 case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD; in getRealVLDOpcode()
8815 case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD; in getRealVLDOpcode()
8816 case ARM::VLD3dAsm_8: Spacing = 1; return ARM::VLD3d8; in getRealVLDOpcode()
8817 case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16; in getRealVLDOpcode()
8818 case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32; in getRealVLDOpcode()
8819 case ARM::VLD3qAsm_8: Spacing = 2; return ARM::VLD3q8; in getRealVLDOpcode()
8820 case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16; in getRealVLDOpcode()
8821 case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32; in getRealVLDOpcode()
8824 case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD; in getRealVLDOpcode()
8825 case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD; in getRealVLDOpcode()
8826 case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD; in getRealVLDOpcode()
8827 case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD; in getRealVLDOpcode()
8828 case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD; in getRealVLDOpcode()
8829 case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD; in getRealVLDOpcode()
8830 case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD; in getRealVLDOpcode()
8831 case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD; in getRealVLDOpcode()
8832 case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD; in getRealVLDOpcode()
8833 case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD; in getRealVLDOpcode()
8834 case ARM::VLD4LNdAsm_8: Spacing = 1; return ARM::VLD4LNd8; in getRealVLDOpcode()
8835 case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16; in getRealVLDOpcode()
8836 case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32; in getRealVLDOpcode()
8837 case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16; in getRealVLDOpcode()
8838 case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32; in getRealVLDOpcode()
8841 case ARM::VLD4DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD; in getRealVLDOpcode()
8842 case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD; in getRealVLDOpcode()
8843 case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD; in getRealVLDOpcode()
8844 case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD; in getRealVLDOpcode()
8845 case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD; in getRealVLDOpcode()
8846 case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD; in getRealVLDOpcode()
8847 case ARM::VLD4DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD; in getRealVLDOpcode()
8848 case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD; in getRealVLDOpcode()
8849 case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD; in getRealVLDOpcode()
8850 case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD; in getRealVLDOpcode()
8851 case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD; in getRealVLDOpcode()
8852 case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD; in getRealVLDOpcode()
8853 case ARM::VLD4DUPdAsm_8: Spacing = 1; return ARM::VLD4DUPd8; in getRealVLDOpcode()
8854 case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16; in getRealVLDOpcode()
8855 case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32; in getRealVLDOpcode()
8856 case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8; in getRealVLDOpcode()
8857 case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16; in getRealVLDOpcode()
8858 case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32; in getRealVLDOpcode()
8861 case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD; in getRealVLDOpcode()
8862 case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD; in getRealVLDOpcode()
8863 case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD; in getRealVLDOpcode()
8864 case ARM::VLD4qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD; in getRealVLDOpcode()
8865 case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD; in getRealVLDOpcode()
8866 case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD; in getRealVLDOpcode()
8867 case ARM::VLD4dWB_register_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD; in getRealVLDOpcode()
8868 case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD; in getRealVLDOpcode()
8869 case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD; in getRealVLDOpcode()
8870 case ARM::VLD4qWB_register_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD; in getRealVLDOpcode()
8871 case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD; in getRealVLDOpcode()
8872 case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD; in getRealVLDOpcode()
8873 case ARM::VLD4dAsm_8: Spacing = 1; return ARM::VLD4d8; in getRealVLDOpcode()
8874 case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16; in getRealVLDOpcode()
8875 case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32; in getRealVLDOpcode()
8876 case ARM::VLD4qAsm_8: Spacing = 2; return ARM::VLD4q8; in getRealVLDOpcode()
8877 case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16; in getRealVLDOpcode()
8878 case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32; in getRealVLDOpcode()
8898 case ARM::VLLDM: in processInstruction()
8899 case ARM::VLSTM: { in processInstruction()
8912 (Inst.getOpcode() == ARM::VLLDM) ? ARM::VLLDM_T2 : ARM::VLSTM_T2; in processInstruction()
8926 case ARM::LDRT_POST: in processInstruction()
8927 case ARM::LDRBT_POST: { in processInstruction()
8929 (Inst.getOpcode() == ARM::LDRT_POST) ? ARM::LDRT_POST_IMM in processInstruction()
8930 : ARM::LDRBT_POST_IMM; in processInstruction()
8944 case ARM::LDRSBTii: in processInstruction()
8945 case ARM::LDRHTii: in processInstruction()
8946 case ARM::LDRSHTii: { in processInstruction()
8949 if (Inst.getOpcode() == ARM::LDRSBTii) in processInstruction()
8950 TmpInst.setOpcode(ARM::LDRSBTi); in processInstruction()
8951 else if (Inst.getOpcode() == ARM::LDRHTii) in processInstruction()
8952 TmpInst.setOpcode(ARM::LDRHTi); in processInstruction()
8953 else if (Inst.getOpcode() == ARM::LDRSHTii) in processInstruction()
8954 TmpInst.setOpcode(ARM::LDRSHTi); in processInstruction()
8964 case ARM::STRT_POST: in processInstruction()
8965 case ARM::STRBT_POST: { in processInstruction()
8967 (Inst.getOpcode() == ARM::STRT_POST) ? ARM::STRT_POST_IMM in processInstruction()
8968 : ARM::STRBT_POST_IMM; in processInstruction()
8982 case ARM::ADDri: { in processInstruction()
8983 if (Inst.getOperand(1).getReg() != ARM::PC || in processInstruction()
8988 TmpInst.setOpcode(ARM::ADR); in processInstruction()
9019 case ARM::t2LDR_PRE_imm: in processInstruction()
9020 case ARM::t2LDR_POST_imm: { in processInstruction()
9022 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2LDR_PRE_imm ? ARM::t2LDR_PRE in processInstruction()
9023 : ARM::t2LDR_POST); in processInstruction()
9033 case ARM::t2STR_PRE_imm: in processInstruction()
9034 case ARM::t2STR_POST_imm: { in processInstruction()
9036 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2STR_PRE_imm ? ARM::t2STR_PRE in processInstruction()
9037 : ARM::t2STR_POST); in processInstruction()
9047 case ARM::t2LDRB_OFFSET_imm: { in processInstruction()
9049 TmpInst.setOpcode(ARM::t2LDRBi8); in processInstruction()
9057 case ARM::t2LDRB_PRE_imm: in processInstruction()
9058 case ARM::t2LDRB_POST_imm: { in processInstruction()
9060 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2LDRB_PRE_imm in processInstruction()
9061 ? ARM::t2LDRB_PRE in processInstruction()
9062 : ARM::t2LDRB_POST); in processInstruction()
9072 case ARM::t2STRB_OFFSET_imm: { in processInstruction()
9074 TmpInst.setOpcode(ARM::t2STRBi8); in processInstruction()
9082 case ARM::t2STRB_PRE_imm: in processInstruction()
9083 case ARM::t2STRB_POST_imm: { in processInstruction()
9085 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2STRB_PRE_imm in processInstruction()
9086 ? ARM::t2STRB_PRE in processInstruction()
9087 : ARM::t2STRB_POST); in processInstruction()
9097 case ARM::t2LDRH_OFFSET_imm: { in processInstruction()
9099 TmpInst.setOpcode(ARM::t2LDRHi8); in processInstruction()
9107 case ARM::t2LDRH_PRE_imm: in processInstruction()
9108 case ARM::t2LDRH_POST_imm: { in processInstruction()
9110 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2LDRH_PRE_imm in processInstruction()
9111 ? ARM::t2LDRH_PRE in processInstruction()
9112 : ARM::t2LDRH_POST); in processInstruction()
9122 case ARM::t2STRH_OFFSET_imm: { in processInstruction()
9124 TmpInst.setOpcode(ARM::t2STRHi8); in processInstruction()
9132 case ARM::t2STRH_PRE_imm: in processInstruction()
9133 case ARM::t2STRH_POST_imm: { in processInstruction()
9135 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2STRH_PRE_imm in processInstruction()
9136 ? ARM::t2STRH_PRE in processInstruction()
9137 : ARM::t2STRH_POST); in processInstruction()
9147 case ARM::t2LDRSB_OFFSET_imm: { in processInstruction()
9149 TmpInst.setOpcode(ARM::t2LDRSBi8); in processInstruction()
9157 case ARM::t2LDRSB_PRE_imm: in processInstruction()
9158 case ARM::t2LDRSB_POST_imm: { in processInstruction()
9160 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2LDRSB_PRE_imm in processInstruction()
9161 ? ARM::t2LDRSB_PRE in processInstruction()
9162 : ARM::t2LDRSB_POST); in processInstruction()
9172 case ARM::t2LDRSH_OFFSET_imm: { in processInstruction()
9174 TmpInst.setOpcode(ARM::t2LDRSHi8); in processInstruction()
9182 case ARM::t2LDRSH_PRE_imm: in processInstruction()
9183 case ARM::t2LDRSH_POST_imm: { in processInstruction()
9185 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2LDRSH_PRE_imm in processInstruction()
9186 ? ARM::t2LDRSH_PRE in processInstruction()
9187 : ARM::t2LDRSH_POST); in processInstruction()
9197 case ARM::t2LDRpcrel: in processInstruction()
9202 Inst.setOpcode(ARM::tLDRpci); in processInstruction()
9204 Inst.setOpcode(ARM::t2LDRpci); in processInstruction()
9206 case ARM::t2LDRBpcrel: in processInstruction()
9207 Inst.setOpcode(ARM::t2LDRBpci); in processInstruction()
9209 case ARM::t2LDRHpcrel: in processInstruction()
9210 Inst.setOpcode(ARM::t2LDRHpci); in processInstruction()
9212 case ARM::t2LDRSBpcrel: in processInstruction()
9213 Inst.setOpcode(ARM::t2LDRSBpci); in processInstruction()
9215 case ARM::t2LDRSHpcrel: in processInstruction()
9216 Inst.setOpcode(ARM::t2LDRSHpci); in processInstruction()
9218 case ARM::LDRConstPool: in processInstruction()
9219 case ARM::tLDRConstPool: in processInstruction()
9220 case ARM::t2LDRConstPool: { in processInstruction()
9225 if (Inst.getOpcode() == ARM::LDRConstPool) in processInstruction()
9226 TmpInst.setOpcode(ARM::LDRi12); in processInstruction()
9227 else if (Inst.getOpcode() == ARM::tLDRConstPool) in processInstruction()
9228 TmpInst.setOpcode(ARM::tLDRpci); in processInstruction()
9229 else if (Inst.getOpcode() == ARM::t2LDRConstPool) in processInstruction()
9230 TmpInst.setOpcode(ARM::t2LDRpci); in processInstruction()
9236 Inst.getOperand(0).getReg() != ARM::PC && in processInstruction()
9237 Inst.getOperand(0).getReg() != ARM::SP) { in processInstruction()
9242 if (Inst.getOpcode() == ARM::LDRConstPool) { in processInstruction()
9246 TmpInst.setOpcode(ARM::MOVi); in processInstruction()
9250 TmpInst.setOpcode(ARM::MVNi); in processInstruction()
9254 TmpInst.setOpcode(ARM::MOVi16); in processInstruction()
9264 TmpInst.setOpcode(ARM::t2MOVi); in processInstruction()
9267 TmpInst.setOpcode(ARM::t2MVNi); in processInstruction()
9272 TmpInst.setOpcode(ARM::t2MOVi16); in processInstruction()
9295 if (TmpInst.getOpcode() == ARM::LDRi12) in processInstruction()
9303 case ARM::VST1LNdWB_register_Asm_8: in processInstruction()
9304 case ARM::VST1LNdWB_register_Asm_16: in processInstruction()
9305 case ARM::VST1LNdWB_register_Asm_32: { in processInstruction()
9323 case ARM::VST2LNdWB_register_Asm_8: in processInstruction()
9324 case ARM::VST2LNdWB_register_Asm_16: in processInstruction()
9325 case ARM::VST2LNdWB_register_Asm_32: in processInstruction()
9326 case ARM::VST2LNqWB_register_Asm_16: in processInstruction()
9327 case ARM::VST2LNqWB_register_Asm_32: { in processInstruction()
9347 case ARM::VST3LNdWB_register_Asm_8: in processInstruction()
9348 case ARM::VST3LNdWB_register_Asm_16: in processInstruction()
9349 case ARM::VST3LNdWB_register_Asm_32: in processInstruction()
9350 case ARM::VST3LNqWB_register_Asm_16: in processInstruction()
9351 case ARM::VST3LNqWB_register_Asm_32: { in processInstruction()
9373 case ARM::VST4LNdWB_register_Asm_8: in processInstruction()
9374 case ARM::VST4LNdWB_register_Asm_16: in processInstruction()
9375 case ARM::VST4LNdWB_register_Asm_32: in processInstruction()
9376 case ARM::VST4LNqWB_register_Asm_16: in processInstruction()
9377 case ARM::VST4LNqWB_register_Asm_32: { in processInstruction()
9401 case ARM::VST1LNdWB_fixed_Asm_8: in processInstruction()
9402 case ARM::VST1LNdWB_fixed_Asm_16: in processInstruction()
9403 case ARM::VST1LNdWB_fixed_Asm_32: { in processInstruction()
9421 case ARM::VST2LNdWB_fixed_Asm_8: in processInstruction()
9422 case ARM::VST2LNdWB_fixed_Asm_16: in processInstruction()
9423 case ARM::VST2LNdWB_fixed_Asm_32: in processInstruction()
9424 case ARM::VST2LNqWB_fixed_Asm_16: in processInstruction()
9425 case ARM::VST2LNqWB_fixed_Asm_32: { in processInstruction()
9445 case ARM::VST3LNdWB_fixed_Asm_8: in processInstruction()
9446 case ARM::VST3LNdWB_fixed_Asm_16: in processInstruction()
9447 case ARM::VST3LNdWB_fixed_Asm_32: in processInstruction()
9448 case ARM::VST3LNqWB_fixed_Asm_16: in processInstruction()
9449 case ARM::VST3LNqWB_fixed_Asm_32: { in processInstruction()
9471 case ARM::VST4LNdWB_fixed_Asm_8: in processInstruction()
9472 case ARM::VST4LNdWB_fixed_Asm_16: in processInstruction()
9473 case ARM::VST4LNdWB_fixed_Asm_32: in processInstruction()
9474 case ARM::VST4LNqWB_fixed_Asm_16: in processInstruction()
9475 case ARM::VST4LNqWB_fixed_Asm_32: { in processInstruction()
9499 case ARM::VST1LNdAsm_8: in processInstruction()
9500 case ARM::VST1LNdAsm_16: in processInstruction()
9501 case ARM::VST1LNdAsm_32: { in processInstruction()
9517 case ARM::VST2LNdAsm_8: in processInstruction()
9518 case ARM::VST2LNdAsm_16: in processInstruction()
9519 case ARM::VST2LNdAsm_32: in processInstruction()
9520 case ARM::VST2LNqAsm_16: in processInstruction()
9521 case ARM::VST2LNqAsm_32: { in processInstruction()
9539 case ARM::VST3LNdAsm_8: in processInstruction()
9540 case ARM::VST3LNdAsm_16: in processInstruction()
9541 case ARM::VST3LNdAsm_32: in processInstruction()
9542 case ARM::VST3LNqAsm_16: in processInstruction()
9543 case ARM::VST3LNqAsm_32: { in processInstruction()
9563 case ARM::VST4LNdAsm_8: in processInstruction()
9564 case ARM::VST4LNdAsm_16: in processInstruction()
9565 case ARM::VST4LNdAsm_32: in processInstruction()
9566 case ARM::VST4LNqAsm_16: in processInstruction()
9567 case ARM::VST4LNqAsm_32: { in processInstruction()
9590 case ARM::VLD1LNdWB_register_Asm_8: in processInstruction()
9591 case ARM::VLD1LNdWB_register_Asm_16: in processInstruction()
9592 case ARM::VLD1LNdWB_register_Asm_32: { in processInstruction()
9611 case ARM::VLD2LNdWB_register_Asm_8: in processInstruction()
9612 case ARM::VLD2LNdWB_register_Asm_16: in processInstruction()
9613 case ARM::VLD2LNdWB_register_Asm_32: in processInstruction()
9614 case ARM::VLD2LNqWB_register_Asm_16: in processInstruction()
9615 case ARM::VLD2LNqWB_register_Asm_32: { in processInstruction()
9638 case ARM::VLD3LNdWB_register_Asm_8: in processInstruction()
9639 case ARM::VLD3LNdWB_register_Asm_16: in processInstruction()
9640 case ARM::VLD3LNdWB_register_Asm_32: in processInstruction()
9641 case ARM::VLD3LNqWB_register_Asm_16: in processInstruction()
9642 case ARM::VLD3LNqWB_register_Asm_32: { in processInstruction()
9669 case ARM::VLD4LNdWB_register_Asm_8: in processInstruction()
9670 case ARM::VLD4LNdWB_register_Asm_16: in processInstruction()
9671 case ARM::VLD4LNdWB_register_Asm_32: in processInstruction()
9672 case ARM::VLD4LNqWB_register_Asm_16: in processInstruction()
9673 case ARM::VLD4LNqWB_register_Asm_32: { in processInstruction()
9704 case ARM::VLD1LNdWB_fixed_Asm_8: in processInstruction()
9705 case ARM::VLD1LNdWB_fixed_Asm_16: in processInstruction()
9706 case ARM::VLD1LNdWB_fixed_Asm_32: { in processInstruction()
9725 case ARM::VLD2LNdWB_fixed_Asm_8: in processInstruction()
9726 case ARM::VLD2LNdWB_fixed_Asm_16: in processInstruction()
9727 case ARM::VLD2LNdWB_fixed_Asm_32: in processInstruction()
9728 case ARM::VLD2LNqWB_fixed_Asm_16: in processInstruction()
9729 case ARM::VLD2LNqWB_fixed_Asm_32: { in processInstruction()
9752 case ARM::VLD3LNdWB_fixed_Asm_8: in processInstruction()
9753 case ARM::VLD3LNdWB_fixed_Asm_16: in processInstruction()
9754 case ARM::VLD3LNdWB_fixed_Asm_32: in processInstruction()
9755 case ARM::VLD3LNqWB_fixed_Asm_16: in processInstruction()
9756 case ARM::VLD3LNqWB_fixed_Asm_32: { in processInstruction()
9783 case ARM::VLD4LNdWB_fixed_Asm_8: in processInstruction()
9784 case ARM::VLD4LNdWB_fixed_Asm_16: in processInstruction()
9785 case ARM::VLD4LNdWB_fixed_Asm_32: in processInstruction()
9786 case ARM::VLD4LNqWB_fixed_Asm_16: in processInstruction()
9787 case ARM::VLD4LNqWB_fixed_Asm_32: { in processInstruction()
9818 case ARM::VLD1LNdAsm_8: in processInstruction()
9819 case ARM::VLD1LNdAsm_16: in processInstruction()
9820 case ARM::VLD1LNdAsm_32: { in processInstruction()
9837 case ARM::VLD2LNdAsm_8: in processInstruction()
9838 case ARM::VLD2LNdAsm_16: in processInstruction()
9839 case ARM::VLD2LNdAsm_32: in processInstruction()
9840 case ARM::VLD2LNqAsm_16: in processInstruction()
9841 case ARM::VLD2LNqAsm_32: { in processInstruction()
9862 case ARM::VLD3LNdAsm_8: in processInstruction()
9863 case ARM::VLD3LNdAsm_16: in processInstruction()
9864 case ARM::VLD3LNdAsm_32: in processInstruction()
9865 case ARM::VLD3LNqAsm_16: in processInstruction()
9866 case ARM::VLD3LNqAsm_32: { in processInstruction()
9891 case ARM::VLD4LNdAsm_8: in processInstruction()
9892 case ARM::VLD4LNdAsm_16: in processInstruction()
9893 case ARM::VLD4LNdAsm_32: in processInstruction()
9894 case ARM::VLD4LNqAsm_16: in processInstruction()
9895 case ARM::VLD4LNqAsm_32: { in processInstruction()
9925 case ARM::VLD3DUPdAsm_8: in processInstruction()
9926 case ARM::VLD3DUPdAsm_16: in processInstruction()
9927 case ARM::VLD3DUPdAsm_32: in processInstruction()
9928 case ARM::VLD3DUPqAsm_8: in processInstruction()
9929 case ARM::VLD3DUPqAsm_16: in processInstruction()
9930 case ARM::VLD3DUPqAsm_32: { in processInstruction()
9947 case ARM::VLD3DUPdWB_fixed_Asm_8: in processInstruction()
9948 case ARM::VLD3DUPdWB_fixed_Asm_16: in processInstruction()
9949 case ARM::VLD3DUPdWB_fixed_Asm_32: in processInstruction()
9950 case ARM::VLD3DUPqWB_fixed_Asm_8: in processInstruction()
9951 case ARM::VLD3DUPqWB_fixed_Asm_16: in processInstruction()
9952 case ARM::VLD3DUPqWB_fixed_Asm_32: { in processInstruction()
9971 case ARM::VLD3DUPdWB_register_Asm_8: in processInstruction()
9972 case ARM::VLD3DUPdWB_register_Asm_16: in processInstruction()
9973 case ARM::VLD3DUPdWB_register_Asm_32: in processInstruction()
9974 case ARM::VLD3DUPqWB_register_Asm_8: in processInstruction()
9975 case ARM::VLD3DUPqWB_register_Asm_16: in processInstruction()
9976 case ARM::VLD3DUPqWB_register_Asm_32: { in processInstruction()
9996 case ARM::VLD3dAsm_8: in processInstruction()
9997 case ARM::VLD3dAsm_16: in processInstruction()
9998 case ARM::VLD3dAsm_32: in processInstruction()
9999 case ARM::VLD3qAsm_8: in processInstruction()
10000 case ARM::VLD3qAsm_16: in processInstruction()
10001 case ARM::VLD3qAsm_32: { in processInstruction()
10018 case ARM::VLD3dWB_fixed_Asm_8: in processInstruction()
10019 case ARM::VLD3dWB_fixed_Asm_16: in processInstruction()
10020 case ARM::VLD3dWB_fixed_Asm_32: in processInstruction()
10021 case ARM::VLD3qWB_fixed_Asm_8: in processInstruction()
10022 case ARM::VLD3qWB_fixed_Asm_16: in processInstruction()
10023 case ARM::VLD3qWB_fixed_Asm_32: { in processInstruction()
10042 case ARM::VLD3dWB_register_Asm_8: in processInstruction()
10043 case ARM::VLD3dWB_register_Asm_16: in processInstruction()
10044 case ARM::VLD3dWB_register_Asm_32: in processInstruction()
10045 case ARM::VLD3qWB_register_Asm_8: in processInstruction()
10046 case ARM::VLD3qWB_register_Asm_16: in processInstruction()
10047 case ARM::VLD3qWB_register_Asm_32: { in processInstruction()
10067 case ARM::VLD4DUPdAsm_8: in processInstruction()
10068 case ARM::VLD4DUPdAsm_16: in processInstruction()
10069 case ARM::VLD4DUPdAsm_32: in processInstruction()
10070 case ARM::VLD4DUPqAsm_8: in processInstruction()
10071 case ARM::VLD4DUPqAsm_16: in processInstruction()
10072 case ARM::VLD4DUPqAsm_32: { in processInstruction()
10091 case ARM::VLD4DUPdWB_fixed_Asm_8: in processInstruction()
10092 case ARM::VLD4DUPdWB_fixed_Asm_16: in processInstruction()
10093 case ARM::VLD4DUPdWB_fixed_Asm_32: in processInstruction()
10094 case ARM::VLD4DUPqWB_fixed_Asm_8: in processInstruction()
10095 case ARM::VLD4DUPqWB_fixed_Asm_16: in processInstruction()
10096 case ARM::VLD4DUPqWB_fixed_Asm_32: { in processInstruction()
10117 case ARM::VLD4DUPdWB_register_Asm_8: in processInstruction()
10118 case ARM::VLD4DUPdWB_register_Asm_16: in processInstruction()
10119 case ARM::VLD4DUPdWB_register_Asm_32: in processInstruction()
10120 case ARM::VLD4DUPqWB_register_Asm_8: in processInstruction()
10121 case ARM::VLD4DUPqWB_register_Asm_16: in processInstruction()
10122 case ARM::VLD4DUPqWB_register_Asm_32: { in processInstruction()
10144 case ARM::VLD4dAsm_8: in processInstruction()
10145 case ARM::VLD4dAsm_16: in processInstruction()
10146 case ARM::VLD4dAsm_32: in processInstruction()
10147 case ARM::VLD4qAsm_8: in processInstruction()
10148 case ARM::VLD4qAsm_16: in processInstruction()
10149 case ARM::VLD4qAsm_32: { in processInstruction()
10168 case ARM::VLD4dWB_fixed_Asm_8: in processInstruction()
10169 case ARM::VLD4dWB_fixed_Asm_16: in processInstruction()
10170 case ARM::VLD4dWB_fixed_Asm_32: in processInstruction()
10171 case ARM::VLD4qWB_fixed_Asm_8: in processInstruction()
10172 case ARM::VLD4qWB_fixed_Asm_16: in processInstruction()
10173 case ARM::VLD4qWB_fixed_Asm_32: { in processInstruction()
10194 case ARM::VLD4dWB_register_Asm_8: in processInstruction()
10195 case ARM::VLD4dWB_register_Asm_16: in processInstruction()
10196 case ARM::VLD4dWB_register_Asm_32: in processInstruction()
10197 case ARM::VLD4qWB_register_Asm_8: in processInstruction()
10198 case ARM::VLD4qWB_register_Asm_16: in processInstruction()
10199 case ARM::VLD4qWB_register_Asm_32: { in processInstruction()
10221 case ARM::VST3dAsm_8: in processInstruction()
10222 case ARM::VST3dAsm_16: in processInstruction()
10223 case ARM::VST3dAsm_32: in processInstruction()
10224 case ARM::VST3qAsm_8: in processInstruction()
10225 case ARM::VST3qAsm_16: in processInstruction()
10226 case ARM::VST3qAsm_32: { in processInstruction()
10243 case ARM::VST3dWB_fixed_Asm_8: in processInstruction()
10244 case ARM::VST3dWB_fixed_Asm_16: in processInstruction()
10245 case ARM::VST3dWB_fixed_Asm_32: in processInstruction()
10246 case ARM::VST3qWB_fixed_Asm_8: in processInstruction()
10247 case ARM::VST3qWB_fixed_Asm_16: in processInstruction()
10248 case ARM::VST3qWB_fixed_Asm_32: { in processInstruction()
10267 case ARM::VST3dWB_register_Asm_8: in processInstruction()
10268 case ARM::VST3dWB_register_Asm_16: in processInstruction()
10269 case ARM::VST3dWB_register_Asm_32: in processInstruction()
10270 case ARM::VST3qWB_register_Asm_8: in processInstruction()
10271 case ARM::VST3qWB_register_Asm_16: in processInstruction()
10272 case ARM::VST3qWB_register_Asm_32: { in processInstruction()
10292 case ARM::VST4dAsm_8: in processInstruction()
10293 case ARM::VST4dAsm_16: in processInstruction()
10294 case ARM::VST4dAsm_32: in processInstruction()
10295 case ARM::VST4qAsm_8: in processInstruction()
10296 case ARM::VST4qAsm_16: in processInstruction()
10297 case ARM::VST4qAsm_32: { in processInstruction()
10316 case ARM::VST4dWB_fixed_Asm_8: in processInstruction()
10317 case ARM::VST4dWB_fixed_Asm_16: in processInstruction()
10318 case ARM::VST4dWB_fixed_Asm_32: in processInstruction()
10319 case ARM::VST4qWB_fixed_Asm_8: in processInstruction()
10320 case ARM::VST4qWB_fixed_Asm_16: in processInstruction()
10321 case ARM::VST4qWB_fixed_Asm_32: { in processInstruction()
10342 case ARM::VST4dWB_register_Asm_8: in processInstruction()
10343 case ARM::VST4dWB_register_Asm_16: in processInstruction()
10344 case ARM::VST4dWB_register_Asm_32: in processInstruction()
10345 case ARM::VST4qWB_register_Asm_8: in processInstruction()
10346 case ARM::VST4qWB_register_Asm_16: in processInstruction()
10347 case ARM::VST4qWB_register_Asm_32: { in processInstruction()
10369 case ARM::t2LSLri: in processInstruction()
10370 case ARM::t2LSRri: in processInstruction()
10371 case ARM::t2ASRri: in processInstruction()
10374 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) && in processInstruction()
10379 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break; in processInstruction()
10380 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break; in processInstruction()
10381 case ARM::t2ASRri: NewOpc = ARM::tASRri; break; in processInstruction()
10398 case ARM::t2MOVsr: in processInstruction()
10399 case ARM::t2MOVSsr: { in processInstruction()
10408 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr) && in processInstruction()
10415 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break; in processInstruction()
10416 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break; in processInstruction()
10417 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break; in processInstruction()
10418 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break; in processInstruction()
10424 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); in processInstruction()
10431 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); in processInstruction()
10435 case ARM::t2MOVsi: in processInstruction()
10436 case ARM::t2MOVSsi: { in processInstruction()
10443 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi) && in processInstruction()
10461 newOpc = isNarrow ? ARM::tMOVSr : ARM::t2MOVr; in processInstruction()
10465 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break; in processInstruction()
10466 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break; in processInstruction()
10467 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break; in processInstruction()
10468 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break; in processInstruction()
10469 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break; in processInstruction()
10477 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); in processInstruction()
10479 if (newOpc != ARM::t2RRX && !isMov) in processInstruction()
10485 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); in processInstruction()
10490 case ARM::ASRr: in processInstruction()
10491 case ARM::LSRr: in processInstruction()
10492 case ARM::LSLr: in processInstruction()
10493 case ARM::RORr: { in processInstruction()
10497 case ARM::ASRr: ShiftTy = ARM_AM::asr; break; in processInstruction()
10498 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break; in processInstruction()
10499 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break; in processInstruction()
10500 case ARM::RORr: ShiftTy = ARM_AM::ror; break; in processInstruction()
10504 TmpInst.setOpcode(ARM::MOVsr); in processInstruction()
10515 case ARM::ASRi: in processInstruction()
10516 case ARM::LSRi: in processInstruction()
10517 case ARM::LSLi: in processInstruction()
10518 case ARM::RORi: { in processInstruction()
10522 case ARM::ASRi: ShiftTy = ARM_AM::asr; break; in processInstruction()
10523 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break; in processInstruction()
10524 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break; in processInstruction()
10525 case ARM::RORi: ShiftTy = ARM_AM::ror; break; in processInstruction()
10529 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi; in processInstruction()
10538 if (Opc == ARM::MOVsi) in processInstruction()
10546 case ARM::RRXi: { in processInstruction()
10549 TmpInst.setOpcode(ARM::MOVsi); in processInstruction()
10559 case ARM::t2LDMIA_UPD: { in processInstruction()
10565 TmpInst.setOpcode(ARM::t2LDR_POST); in processInstruction()
10575 case ARM::t2STMDB_UPD: { in processInstruction()
10581 TmpInst.setOpcode(ARM::t2STR_PRE); in processInstruction()
10591 case ARM::LDMIA_UPD: in processInstruction()
10597 TmpInst.setOpcode(ARM::LDR_POST_IMM); in processInstruction()
10609 case ARM::STMDB_UPD: in processInstruction()
10615 TmpInst.setOpcode(ARM::STR_PRE_IMM); in processInstruction()
10625 case ARM::t2ADDri12: in processInstruction()
10626 case ARM::t2SUBri12: in processInstruction()
10627 case ARM::t2ADDspImm12: in processInstruction()
10628 case ARM::t2SUBspImm12: { in processInstruction()
10636 case ARM::t2ADDri12: in processInstruction()
10637 Inst.setOpcode(ARM::t2ADDri); in processInstruction()
10639 case ARM::t2SUBri12: in processInstruction()
10640 Inst.setOpcode(ARM::t2SUBri); in processInstruction()
10642 case ARM::t2ADDspImm12: in processInstruction()
10643 Inst.setOpcode(ARM::t2ADDspImm); in processInstruction()
10645 case ARM::t2SUBspImm12: in processInstruction()
10646 Inst.setOpcode(ARM::t2SUBspImm); in processInstruction()
10653 case ARM::tADDi8: in processInstruction()
10661 Inst.setOpcode(ARM::tADDi3); in processInstruction()
10665 case ARM::tSUBi8: in processInstruction()
10672 Inst.setOpcode(ARM::tSUBi3); in processInstruction()
10676 case ARM::t2ADDri: in processInstruction()
10677 case ARM::t2SUBri: { in processInstruction()
10686 Inst.getOperand(5).getReg() != (inITBlock() ? 0 : ARM::CPSR) || in processInstruction()
10690 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ? in processInstruction()
10691 ARM::tADDi8 : ARM::tSUBi8); in processInstruction()
10701 case ARM::t2ADDspImm: in processInstruction()
10702 case ARM::t2SUBspImm: { in processInstruction()
10710 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDspImm ? ARM::tADDspi in processInstruction()
10711 : ARM::tSUBspi); in processInstruction()
10712 TmpInst.addOperand(MCOperand::createReg(ARM::SP)); // destination reg in processInstruction()
10713 TmpInst.addOperand(MCOperand::createReg(ARM::SP)); // source reg in processInstruction()
10720 case ARM::t2ADDrr: { in processInstruction()
10738 TmpInst.setOpcode(ARM::tADDhirr); in processInstruction()
10747 case ARM::tADDrSP: in processInstruction()
10751 Inst.setOpcode(ARM::t2ADDrr); in processInstruction()
10756 case ARM::tB: in processInstruction()
10759 Inst.setOpcode(ARM::tBcc); in processInstruction()
10763 case ARM::t2B: in processInstruction()
10766 Inst.setOpcode(ARM::t2Bcc); in processInstruction()
10770 case ARM::t2Bcc: in processInstruction()
10773 Inst.setOpcode(ARM::t2B); in processInstruction()
10777 case ARM::tBcc: in processInstruction()
10780 Inst.setOpcode(ARM::tB); in processInstruction()
10784 case ARM::tLDMIA: { in processInstruction()
10801 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA); in processInstruction()
10811 case ARM::tSTMIA_UPD: { in processInstruction()
10820 Inst.setOpcode(ARM::t2STMIA_UPD); in processInstruction()
10825 case ARM::tPOP: { in processInstruction()
10830 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase)) in processInstruction()
10833 Inst.setOpcode(ARM::t2LDMIA_UPD); in processInstruction()
10835 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP)); in processInstruction()
10836 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP)); in processInstruction()
10839 case ARM::tPUSH: { in processInstruction()
10841 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase)) in processInstruction()
10844 Inst.setOpcode(ARM::t2STMDB_UPD); in processInstruction()
10846 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP)); in processInstruction()
10847 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP)); in processInstruction()
10850 case ARM::t2MOVi: in processInstruction()
10856 Inst.getOperand(4).getReg() == (inITBlock() ? 0 : ARM::CPSR) && in processInstruction()
10860 TmpInst.setOpcode(ARM::tMOVi8); in processInstruction()
10871 case ARM::t2MOVr: in processInstruction()
10877 Inst.getOperand(4).getReg() == ARM::CPSR && in processInstruction()
10881 unsigned Op = Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr; in processInstruction()
10885 if (Op == ARM::tMOVr) { in processInstruction()
10894 case ARM::t2SXTH: in processInstruction()
10895 case ARM::t2SXTB: in processInstruction()
10896 case ARM::t2UXTH: in processInstruction()
10897 case ARM::t2UXTB: in processInstruction()
10907 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break; in processInstruction()
10908 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break; in processInstruction()
10909 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break; in processInstruction()
10910 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break; in processInstruction()
10924 case ARM::MOVsi: { in processInstruction()
10932 TmpInst.setOpcode(ARM::MOVr); in processInstruction()
10943 case ARM::ANDrsi: in processInstruction()
10944 case ARM::ORRrsi: in processInstruction()
10945 case ARM::EORrsi: in processInstruction()
10946 case ARM::BICrsi: in processInstruction()
10947 case ARM::SUBrsi: in processInstruction()
10948 case ARM::ADDrsi: { in processInstruction()
10954 case ARM::ANDrsi: newOpc = ARM::ANDrr; break; in processInstruction()
10955 case ARM::ORRrsi: newOpc = ARM::ORRrr; break; in processInstruction()
10956 case ARM::EORrsi: newOpc = ARM::EORrr; break; in processInstruction()
10957 case ARM::BICrsi: newOpc = ARM::BICrr; break; in processInstruction()
10958 case ARM::SUBrsi: newOpc = ARM::SUBrr; break; in processInstruction()
10959 case ARM::ADDrsi: newOpc = ARM::ADDrr; break; in processInstruction()
10978 case ARM::ITasm: in processInstruction()
10979 case ARM::t2IT: { in processInstruction()
10987 case ARM::t2LSLrr: in processInstruction()
10988 case ARM::t2LSRrr: in processInstruction()
10989 case ARM::t2ASRrr: in processInstruction()
10990 case ARM::t2SBCrr: in processInstruction()
10991 case ARM::t2RORrr: in processInstruction()
10992 case ARM::t2BICrr: in processInstruction()
10997 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) && in processInstruction()
11002 case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break; in processInstruction()
11003 case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break; in processInstruction()
11004 case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break; in processInstruction()
11005 case ARM::t2SBCrr: NewOpc = ARM::tSBC; break; in processInstruction()
11006 case ARM::t2RORrr: NewOpc = ARM::tROR; break; in processInstruction()
11007 case ARM::t2BICrr: NewOpc = ARM::tBIC; break; in processInstruction()
11022 case ARM::t2ANDrr: in processInstruction()
11023 case ARM::t2EORrr: in processInstruction()
11024 case ARM::t2ADCrr: in processInstruction()
11025 case ARM::t2ORRrr: in processInstruction()
11033 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) && in processInstruction()
11038 case ARM::t2ADCrr: NewOpc = ARM::tADC; break; in processInstruction()
11039 case ARM::t2ANDrr: NewOpc = ARM::tAND; break; in processInstruction()
11040 case ARM::t2EORrr: NewOpc = ARM::tEOR; break; in processInstruction()
11041 case ARM::t2ORRrr: NewOpc = ARM::tORR; break; in processInstruction()
11060 case ARM::MVE_VPST: in processInstruction()
11061 case ARM::MVE_VPTv16i8: in processInstruction()
11062 case ARM::MVE_VPTv8i16: in processInstruction()
11063 case ARM::MVE_VPTv4i32: in processInstruction()
11064 case ARM::MVE_VPTv16u8: in processInstruction()
11065 case ARM::MVE_VPTv8u16: in processInstruction()
11066 case ARM::MVE_VPTv4u32: in processInstruction()
11067 case ARM::MVE_VPTv16s8: in processInstruction()
11068 case ARM::MVE_VPTv8s16: in processInstruction()
11069 case ARM::MVE_VPTv4s32: in processInstruction()
11070 case ARM::MVE_VPTv4f32: in processInstruction()
11071 case ARM::MVE_VPTv8f16: in processInstruction()
11072 case ARM::MVE_VPTv16i8r: in processInstruction()
11073 case ARM::MVE_VPTv8i16r: in processInstruction()
11074 case ARM::MVE_VPTv4i32r: in processInstruction()
11075 case ARM::MVE_VPTv16u8r: in processInstruction()
11076 case ARM::MVE_VPTv8u16r: in processInstruction()
11077 case ARM::MVE_VPTv4u32r: in processInstruction()
11078 case ARM::MVE_VPTv16s8r: in processInstruction()
11079 case ARM::MVE_VPTv8s16r: in processInstruction()
11080 case ARM::MVE_VPTv4s32r: in processInstruction()
11081 case ARM::MVE_VPTv4f32r: in processInstruction()
11082 case ARM::MVE_VPTv8f16r: { in processInstruction()
11100 case ARM::tMOVr: { in checkEarlyTargetMatchPredicate()
11128 Inst.getOperand(OpNo).getReg() == ARM::CPSR) in checkTargetMatchPredicate()
11142 if (Opc == ARM::tLSLri && Inst.getOperand(3).getImm() == 0 && inITBlock()) in checkTargetMatchPredicate()
11147 if (Opc == ARM::tADDhirr && !hasV6MOps() && in checkTargetMatchPredicate()
11152 else if (Opc == ARM::tMOVr && !hasV6Ops() && in checkTargetMatchPredicate()
11161 if (Opc == ARM::t2MOVr && !hasV8Ops()) in checkTargetMatchPredicate()
11164 if (Inst.getOperand(0).getReg() == ARM::SP && in checkTargetMatchPredicate()
11165 Inst.getOperand(1).getReg() == ARM::SP) in checkTargetMatchPredicate()
11168 if (Inst.getOperand(4).getReg() == ARM::CPSR && in checkTargetMatchPredicate()
11169 (Inst.getOperand(0).getReg() == ARM::SP || in checkTargetMatchPredicate()
11170 Inst.getOperand(1).getReg() == ARM::SP)) in checkTargetMatchPredicate()
11175 case ARM::VMRS: in checkTargetMatchPredicate()
11176 case ARM::VMSR: in checkTargetMatchPredicate()
11177 case ARM::VMRS_FPCXTS: in checkTargetMatchPredicate()
11178 case ARM::VMRS_FPCXTNS: in checkTargetMatchPredicate()
11179 case ARM::VMSR_FPCXTS: in checkTargetMatchPredicate()
11180 case ARM::VMSR_FPCXTNS: in checkTargetMatchPredicate()
11181 case ARM::VMRS_FPSCR_NZCVQC: in checkTargetMatchPredicate()
11182 case ARM::VMSR_FPSCR_NZCVQC: in checkTargetMatchPredicate()
11183 case ARM::FMSTAT: in checkTargetMatchPredicate()
11184 case ARM::VMRS_VPR: in checkTargetMatchPredicate()
11185 case ARM::VMRS_P0: in checkTargetMatchPredicate()
11186 case ARM::VMSR_VPR: in checkTargetMatchPredicate()
11187 case ARM::VMSR_P0: in checkTargetMatchPredicate()
11190 if (Inst.getOperand(0).isReg() && Inst.getOperand(0).getReg() == ARM::SP && in checkTargetMatchPredicate()
11194 case ARM::t2TBB: in checkTargetMatchPredicate()
11195 case ARM::t2TBH: in checkTargetMatchPredicate()
11197 if (!hasV8Ops() && (Inst.getOperand(0).getReg() == ARM::SP)) in checkTargetMatchPredicate()
11200 case ARM::tMUL: in checkTargetMatchPredicate()
11213 if (MCID.operands()[I].RegClass == ARM::rGPRRegClassID) { in checkTargetMatchPredicate()
11229 if ((Reg == ARM::SP) && !hasV8Ops()) in checkTargetMatchPredicate()
11231 else if (Reg == ARM::PC) in checkTargetMatchPredicate()
11253 if (MCID.isTerminator() || (MCID.isCall() && Inst.getOpcode() != ARM::tSVC) || in isITBlockTerminator()
11259 if (MCID.hasDefOfPhysReg(Inst, ARM::PC, *MRI)) in isITBlockTerminator()
11313 if (Inst.getOpcode() == ARM::tBcc || Inst.getOpcode() == ARM::t2Bcc) { in MatchInstruction()
11404 if (Inst.getOpcode() == ARM::ITasm) in MatchAndEmitInstruction()
11788 ARM::ArchKind ID = ARM::parseArch(Arch); in parseDirectiveArch()
11790 if (ID == ARM::ArchKind::INVALID) in parseDirectiveArch()
11797 ("+" + ARM::getArchName(ID)).str()); in parseDirectiveArch()
11930 ARM::FPUKind ID = ARM::parseFPU(FPU); in parseDirectiveFPU()
11932 if (!ARM::getFPUFeatures(ID, Features)) in parseDirectiveFPU()
12090 check(SPReg != ARM::SP && SPReg != UC.getFPReg(), SPRegLoc, in parseDirectiveSetFP()
12317 if (CE->getValue() < 0 || CE->getValue() >= ARM::EHABI::NUM_PERSONALITY_INDEX) in parseDirectivePersonalityIndex()
12403 if (UC.getFPReg() != ARM::SP) in parseDirectiveMovSP()
12410 if (SPReg == ARM::SP || SPReg == ARM::PC) in parseDirectiveMovSP()
12451 ARM::ArchKind ID = ARM::parseArch(Arch); in parseDirectiveObjectArch()
12453 if (ID == ARM::ArchKind::INVALID) in parseDirectiveObjectArch()
12546 if (Reg == -1 || !MRI->getRegClass(ARM::GPRRegClassID).contains(Reg)) in parseDirectiveSEHSaveSP()
12909 {ARM::AEK_CRC, {Feature_HasV8Bit}, {ARM::FeatureCRC}}, in enableArchExtFeature()
12910 {ARM::AEK_AES, in enableArchExtFeature()
12912 {ARM::FeatureAES, ARM::FeatureNEON, ARM::FeatureFPARMv8}}, in enableArchExtFeature()
12913 {ARM::AEK_SHA2, in enableArchExtFeature()
12915 {ARM::FeatureSHA2, ARM::FeatureNEON, ARM::FeatureFPARMv8}}, in enableArchExtFeature()
12916 {ARM::AEK_CRYPTO, in enableArchExtFeature()
12918 {ARM::FeatureCrypto, ARM::FeatureNEON, ARM::FeatureFPARMv8}}, in enableArchExtFeature()
12919 {(ARM::AEK_DSP | ARM::AEK_SIMD | ARM::AEK_FP), in enableArchExtFeature()
12921 {ARM::HasMVEFloatOps}}, in enableArchExtFeature()
12922 {ARM::AEK_FP, in enableArchExtFeature()
12924 {ARM::FeatureVFP2_SP, ARM::FeatureFPARMv8}}, in enableArchExtFeature()
12925 {(ARM::AEK_HWDIVTHUMB | ARM::AEK_HWDIVARM), in enableArchExtFeature()
12927 {ARM::FeatureHWDivThumb, ARM::FeatureHWDivARM}}, in enableArchExtFeature()
12928 {ARM::AEK_MP, in enableArchExtFeature()
12930 {ARM::FeatureMP}}, in enableArchExtFeature()
12931 {ARM::AEK_SIMD, in enableArchExtFeature()
12933 {ARM::FeatureNEON, ARM::FeatureVFP2_SP, ARM::FeatureFPARMv8}}, in enableArchExtFeature()
12934 {ARM::AEK_SEC, {Feature_HasV6KBit}, {ARM::FeatureTrustZone}}, in enableArchExtFeature()
12936 {ARM::AEK_VIRT, {Feature_HasV7Bit}, {ARM::FeatureVirtualization}}, in enableArchExtFeature()
12937 {ARM::AEK_FP16, in enableArchExtFeature()
12939 {ARM::FeatureFPARMv8, ARM::FeatureFullFP16}}, in enableArchExtFeature()
12940 {ARM::AEK_RAS, {Feature_HasV8Bit}, {ARM::FeatureRAS}}, in enableArchExtFeature()
12941 {ARM::AEK_LOB, {Feature_HasV8_1MMainlineBit}, {ARM::FeatureLOB}}, in enableArchExtFeature()
12942 {ARM::AEK_PACBTI, {Feature_HasV8_1MMainlineBit}, {ARM::FeaturePACBTI}}, in enableArchExtFeature()
12944 {ARM::AEK_OS, {}, {}}, in enableArchExtFeature()
12945 {ARM::AEK_IWMMXT, {}, {}}, in enableArchExtFeature()
12946 {ARM::AEK_IWMMXT2, {}, {}}, in enableArchExtFeature()
12947 {ARM::AEK_MAVERICK, {}, {}}, in enableArchExtFeature()
12948 {ARM::AEK_XSCALE, {}, {}}, in enableArchExtFeature()
12951 uint64_t FeatureKind = ARM::parseArchExt(Name); in enableArchExtFeature()
12952 if (FeatureKind == ARM::AEK_INVALID) in enableArchExtFeature()
13047 if (hasV8Ops() && Op.isReg() && Op.getReg() == ARM::SP) in validateTargetOperandClass()