Lines Matching refs:ARM
119 Reg = CurDAG->getRegister(ARM::CPSR, MVT::i32); in SelectCMOVPred()
528 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD) in hasNoVMLxHazardUse()
1608 Opcode = ARM::LDR_PRE_IMM; in tryARMIndexedLoad()
1612 Opcode = ARM::LDR_POST_IMM; in tryARMIndexedLoad()
1616 Opcode = isPre ? ARM::LDR_PRE_REG : ARM::LDR_POST_REG; in tryARMIndexedLoad()
1623 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST) in tryARMIndexedLoad()
1624 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST); in tryARMIndexedLoad()
1629 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST; in tryARMIndexedLoad()
1635 Opcode = ARM::LDRB_PRE_IMM; in tryARMIndexedLoad()
1639 Opcode = ARM::LDRB_POST_IMM; in tryARMIndexedLoad()
1642 Opcode = isPre ? ARM::LDRB_PRE_REG : ARM::LDRB_POST_REG; in tryARMIndexedLoad()
1648 if (Opcode == ARM::LDR_PRE_IMM || Opcode == ARM::LDRB_PRE_IMM) { in tryARMIndexedLoad()
1694 SDNode *New = CurDAG->getMachineNode(ARM::tLDR_postidx, SDLoc(N), MVT::i32, in tryT1IndexedLoad()
1716 Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST; in tryT2IndexedLoad()
1720 Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST; in tryT2IndexedLoad()
1722 Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST; in tryT2IndexedLoad()
1727 Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST; in tryT2IndexedLoad()
1729 Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST; in tryT2IndexedLoad()
1805 Opcode = isPre ? ARM::MVE_VLDRHS32_pre : ARM::MVE_VLDRHS32_post; in tryMVEIndexedLoad()
1807 Opcode = isPre ? ARM::MVE_VLDRHU32_pre : ARM::MVE_VLDRHU32_post; in tryMVEIndexedLoad()
1811 Opcode = isPre ? ARM::MVE_VLDRBS16_pre : ARM::MVE_VLDRBS16_post; in tryMVEIndexedLoad()
1813 Opcode = isPre ? ARM::MVE_VLDRBU16_pre : ARM::MVE_VLDRBU16_post; in tryMVEIndexedLoad()
1817 Opcode = isPre ? ARM::MVE_VLDRBS32_pre : ARM::MVE_VLDRBS32_post; in tryMVEIndexedLoad()
1819 Opcode = isPre ? ARM::MVE_VLDRBU32_pre : ARM::MVE_VLDRBU32_post; in tryMVEIndexedLoad()
1824 Opcode = isPre ? ARM::MVE_VLDRWU32_pre : ARM::MVE_VLDRWU32_post; in tryMVEIndexedLoad()
1829 Opcode = isPre ? ARM::MVE_VLDRHU16_pre : ARM::MVE_VLDRHU16_post; in tryMVEIndexedLoad()
1832 Opcode = isPre ? ARM::MVE_VLDRBU8_pre : ARM::MVE_VLDRBU8_post; in tryMVEIndexedLoad()
1856 CurDAG->getTargetConstant(ARM::GPRPairRegClassID, dl, MVT::i32); in createGPRPairNode()
1857 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::gsub_0, dl, MVT::i32); in createGPRPairNode()
1858 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::gsub_1, dl, MVT::i32); in createGPRPairNode()
1867 CurDAG->getTargetConstant(ARM::DPR_VFP2RegClassID, dl, MVT::i32); in createSRegPairNode()
1868 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, dl, MVT::i32); in createSRegPairNode()
1869 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, dl, MVT::i32); in createSRegPairNode()
1877 SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, dl, in createDRegPairNode()
1879 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, dl, MVT::i32); in createDRegPairNode()
1880 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, dl, MVT::i32); in createDRegPairNode()
1888 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl, in createQRegPairNode()
1890 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, dl, MVT::i32); in createQRegPairNode()
1891 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, dl, MVT::i32); in createQRegPairNode()
1901 CurDAG->getTargetConstant(ARM::QPR_VFP2RegClassID, dl, MVT::i32); in createQuadSRegsNode()
1902 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, dl, MVT::i32); in createQuadSRegsNode()
1903 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, dl, MVT::i32); in createQuadSRegsNode()
1904 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::ssub_2, dl, MVT::i32); in createQuadSRegsNode()
1905 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::ssub_3, dl, MVT::i32); in createQuadSRegsNode()
1915 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl, in createQuadDRegsNode()
1917 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, dl, MVT::i32); in createQuadDRegsNode()
1918 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, dl, MVT::i32); in createQuadDRegsNode()
1919 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, dl, MVT::i32); in createQuadDRegsNode()
1920 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::dsub_3, dl, MVT::i32); in createQuadDRegsNode()
1930 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, dl, in createQuadQRegsNode()
1932 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, dl, MVT::i32); in createQuadQRegsNode()
1933 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, dl, MVT::i32); in createQuadQRegsNode()
1934 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::qsub_2, dl, MVT::i32); in createQuadQRegsNode()
1935 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::qsub_3, dl, MVT::i32); in createQuadQRegsNode()
1967 case ARM::VLD1d8wb_fixed : return true; in isVLDfixed()
1968 case ARM::VLD1d16wb_fixed : return true; in isVLDfixed()
1969 case ARM::VLD1d64Qwb_fixed : return true; in isVLDfixed()
1970 case ARM::VLD1d32wb_fixed : return true; in isVLDfixed()
1971 case ARM::VLD1d64wb_fixed : return true; in isVLDfixed()
1972 case ARM::VLD1d8TPseudoWB_fixed : return true; in isVLDfixed()
1973 case ARM::VLD1d16TPseudoWB_fixed : return true; in isVLDfixed()
1974 case ARM::VLD1d32TPseudoWB_fixed : return true; in isVLDfixed()
1975 case ARM::VLD1d64TPseudoWB_fixed : return true; in isVLDfixed()
1976 case ARM::VLD1d8QPseudoWB_fixed : return true; in isVLDfixed()
1977 case ARM::VLD1d16QPseudoWB_fixed : return true; in isVLDfixed()
1978 case ARM::VLD1d32QPseudoWB_fixed : return true; in isVLDfixed()
1979 case ARM::VLD1d64QPseudoWB_fixed : return true; in isVLDfixed()
1980 case ARM::VLD1q8wb_fixed : return true; in isVLDfixed()
1981 case ARM::VLD1q16wb_fixed : return true; in isVLDfixed()
1982 case ARM::VLD1q32wb_fixed : return true; in isVLDfixed()
1983 case ARM::VLD1q64wb_fixed : return true; in isVLDfixed()
1984 case ARM::VLD1DUPd8wb_fixed : return true; in isVLDfixed()
1985 case ARM::VLD1DUPd16wb_fixed : return true; in isVLDfixed()
1986 case ARM::VLD1DUPd32wb_fixed : return true; in isVLDfixed()
1987 case ARM::VLD1DUPq8wb_fixed : return true; in isVLDfixed()
1988 case ARM::VLD1DUPq16wb_fixed : return true; in isVLDfixed()
1989 case ARM::VLD1DUPq32wb_fixed : return true; in isVLDfixed()
1990 case ARM::VLD2d8wb_fixed : return true; in isVLDfixed()
1991 case ARM::VLD2d16wb_fixed : return true; in isVLDfixed()
1992 case ARM::VLD2d32wb_fixed : return true; in isVLDfixed()
1993 case ARM::VLD2q8PseudoWB_fixed : return true; in isVLDfixed()
1994 case ARM::VLD2q16PseudoWB_fixed : return true; in isVLDfixed()
1995 case ARM::VLD2q32PseudoWB_fixed : return true; in isVLDfixed()
1996 case ARM::VLD2DUPd8wb_fixed : return true; in isVLDfixed()
1997 case ARM::VLD2DUPd16wb_fixed : return true; in isVLDfixed()
1998 case ARM::VLD2DUPd32wb_fixed : return true; in isVLDfixed()
1999 case ARM::VLD2DUPq8OddPseudoWB_fixed: return true; in isVLDfixed()
2000 case ARM::VLD2DUPq16OddPseudoWB_fixed: return true; in isVLDfixed()
2001 case ARM::VLD2DUPq32OddPseudoWB_fixed: return true; in isVLDfixed()
2009 case ARM::VST1d8wb_fixed : return true; in isVSTfixed()
2010 case ARM::VST1d16wb_fixed : return true; in isVSTfixed()
2011 case ARM::VST1d32wb_fixed : return true; in isVSTfixed()
2012 case ARM::VST1d64wb_fixed : return true; in isVSTfixed()
2013 case ARM::VST1q8wb_fixed : return true; in isVSTfixed()
2014 case ARM::VST1q16wb_fixed : return true; in isVSTfixed()
2015 case ARM::VST1q32wb_fixed : return true; in isVSTfixed()
2016 case ARM::VST1q64wb_fixed : return true; in isVSTfixed()
2017 case ARM::VST1d8TPseudoWB_fixed : return true; in isVSTfixed()
2018 case ARM::VST1d16TPseudoWB_fixed : return true; in isVSTfixed()
2019 case ARM::VST1d32TPseudoWB_fixed : return true; in isVSTfixed()
2020 case ARM::VST1d64TPseudoWB_fixed : return true; in isVSTfixed()
2021 case ARM::VST1d8QPseudoWB_fixed : return true; in isVSTfixed()
2022 case ARM::VST1d16QPseudoWB_fixed : return true; in isVSTfixed()
2023 case ARM::VST1d32QPseudoWB_fixed : return true; in isVSTfixed()
2024 case ARM::VST1d64QPseudoWB_fixed : return true; in isVSTfixed()
2025 case ARM::VST2d8wb_fixed : return true; in isVSTfixed()
2026 case ARM::VST2d16wb_fixed : return true; in isVSTfixed()
2027 case ARM::VST2d32wb_fixed : return true; in isVSTfixed()
2028 case ARM::VST2q8PseudoWB_fixed : return true; in isVSTfixed()
2029 case ARM::VST2q16PseudoWB_fixed : return true; in isVSTfixed()
2030 case ARM::VST2q32PseudoWB_fixed : return true; in isVSTfixed()
2041 case ARM::VLD1d8wb_fixed: return ARM::VLD1d8wb_register; in getVLDSTRegisterUpdateOpcode()
2042 case ARM::VLD1d16wb_fixed: return ARM::VLD1d16wb_register; in getVLDSTRegisterUpdateOpcode()
2043 case ARM::VLD1d32wb_fixed: return ARM::VLD1d32wb_register; in getVLDSTRegisterUpdateOpcode()
2044 case ARM::VLD1d64wb_fixed: return ARM::VLD1d64wb_register; in getVLDSTRegisterUpdateOpcode()
2045 case ARM::VLD1q8wb_fixed: return ARM::VLD1q8wb_register; in getVLDSTRegisterUpdateOpcode()
2046 case ARM::VLD1q16wb_fixed: return ARM::VLD1q16wb_register; in getVLDSTRegisterUpdateOpcode()
2047 case ARM::VLD1q32wb_fixed: return ARM::VLD1q32wb_register; in getVLDSTRegisterUpdateOpcode()
2048 case ARM::VLD1q64wb_fixed: return ARM::VLD1q64wb_register; in getVLDSTRegisterUpdateOpcode()
2049 case ARM::VLD1d64Twb_fixed: return ARM::VLD1d64Twb_register; in getVLDSTRegisterUpdateOpcode()
2050 case ARM::VLD1d64Qwb_fixed: return ARM::VLD1d64Qwb_register; in getVLDSTRegisterUpdateOpcode()
2051 case ARM::VLD1d8TPseudoWB_fixed: return ARM::VLD1d8TPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2052 case ARM::VLD1d16TPseudoWB_fixed: return ARM::VLD1d16TPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2053 case ARM::VLD1d32TPseudoWB_fixed: return ARM::VLD1d32TPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2054 case ARM::VLD1d64TPseudoWB_fixed: return ARM::VLD1d64TPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2055 case ARM::VLD1d8QPseudoWB_fixed: return ARM::VLD1d8QPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2056 case ARM::VLD1d16QPseudoWB_fixed: return ARM::VLD1d16QPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2057 case ARM::VLD1d32QPseudoWB_fixed: return ARM::VLD1d32QPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2058 case ARM::VLD1d64QPseudoWB_fixed: return ARM::VLD1d64QPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2059 case ARM::VLD1DUPd8wb_fixed : return ARM::VLD1DUPd8wb_register; in getVLDSTRegisterUpdateOpcode()
2060 case ARM::VLD1DUPd16wb_fixed : return ARM::VLD1DUPd16wb_register; in getVLDSTRegisterUpdateOpcode()
2061 case ARM::VLD1DUPd32wb_fixed : return ARM::VLD1DUPd32wb_register; in getVLDSTRegisterUpdateOpcode()
2062 case ARM::VLD1DUPq8wb_fixed : return ARM::VLD1DUPq8wb_register; in getVLDSTRegisterUpdateOpcode()
2063 case ARM::VLD1DUPq16wb_fixed : return ARM::VLD1DUPq16wb_register; in getVLDSTRegisterUpdateOpcode()
2064 case ARM::VLD1DUPq32wb_fixed : return ARM::VLD1DUPq32wb_register; in getVLDSTRegisterUpdateOpcode()
2065 case ARM::VLD2DUPq8OddPseudoWB_fixed: return ARM::VLD2DUPq8OddPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2066 case ARM::VLD2DUPq16OddPseudoWB_fixed: return ARM::VLD2DUPq16OddPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2067 case ARM::VLD2DUPq32OddPseudoWB_fixed: return ARM::VLD2DUPq32OddPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2069 case ARM::VST1d8wb_fixed: return ARM::VST1d8wb_register; in getVLDSTRegisterUpdateOpcode()
2070 case ARM::VST1d16wb_fixed: return ARM::VST1d16wb_register; in getVLDSTRegisterUpdateOpcode()
2071 case ARM::VST1d32wb_fixed: return ARM::VST1d32wb_register; in getVLDSTRegisterUpdateOpcode()
2072 case ARM::VST1d64wb_fixed: return ARM::VST1d64wb_register; in getVLDSTRegisterUpdateOpcode()
2073 case ARM::VST1q8wb_fixed: return ARM::VST1q8wb_register; in getVLDSTRegisterUpdateOpcode()
2074 case ARM::VST1q16wb_fixed: return ARM::VST1q16wb_register; in getVLDSTRegisterUpdateOpcode()
2075 case ARM::VST1q32wb_fixed: return ARM::VST1q32wb_register; in getVLDSTRegisterUpdateOpcode()
2076 case ARM::VST1q64wb_fixed: return ARM::VST1q64wb_register; in getVLDSTRegisterUpdateOpcode()
2077 case ARM::VST1d8TPseudoWB_fixed: return ARM::VST1d8TPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2078 case ARM::VST1d16TPseudoWB_fixed: return ARM::VST1d16TPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2079 case ARM::VST1d32TPseudoWB_fixed: return ARM::VST1d32TPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2080 case ARM::VST1d64TPseudoWB_fixed: return ARM::VST1d64TPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2081 case ARM::VST1d8QPseudoWB_fixed: return ARM::VST1d8QPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2082 case ARM::VST1d16QPseudoWB_fixed: return ARM::VST1d16QPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2083 case ARM::VST1d32QPseudoWB_fixed: return ARM::VST1d32QPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2084 case ARM::VST1d64QPseudoWB_fixed: return ARM::VST1d64QPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2086 case ARM::VLD2d8wb_fixed: return ARM::VLD2d8wb_register; in getVLDSTRegisterUpdateOpcode()
2087 case ARM::VLD2d16wb_fixed: return ARM::VLD2d16wb_register; in getVLDSTRegisterUpdateOpcode()
2088 case ARM::VLD2d32wb_fixed: return ARM::VLD2d32wb_register; in getVLDSTRegisterUpdateOpcode()
2089 case ARM::VLD2q8PseudoWB_fixed: return ARM::VLD2q8PseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2090 case ARM::VLD2q16PseudoWB_fixed: return ARM::VLD2q16PseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2091 case ARM::VLD2q32PseudoWB_fixed: return ARM::VLD2q32PseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2093 case ARM::VST2d8wb_fixed: return ARM::VST2d8wb_register; in getVLDSTRegisterUpdateOpcode()
2094 case ARM::VST2d16wb_fixed: return ARM::VST2d16wb_register; in getVLDSTRegisterUpdateOpcode()
2095 case ARM::VST2d32wb_fixed: return ARM::VST2d32wb_register; in getVLDSTRegisterUpdateOpcode()
2096 case ARM::VST2q8PseudoWB_fixed: return ARM::VST2q8PseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2097 case ARM::VST2q16PseudoWB_fixed: return ARM::VST2q16PseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2098 case ARM::VST2q32PseudoWB_fixed: return ARM::VST2q32PseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2100 case ARM::VLD2DUPd8wb_fixed: return ARM::VLD2DUPd8wb_register; in getVLDSTRegisterUpdateOpcode()
2101 case ARM::VLD2DUPd16wb_fixed: return ARM::VLD2DUPd16wb_register; in getVLDSTRegisterUpdateOpcode()
2102 case ARM::VLD2DUPd32wb_fixed: return ARM::VLD2DUPd32wb_register; in getVLDSTRegisterUpdateOpcode()
2244 static_assert(ARM::dsub_7 == ARM::dsub_0 + 7 && in SelectVLD()
2245 ARM::qsub_3 == ARM::qsub_0 + 3, in SelectVLD()
2247 unsigned Sub0 = (is64BitVector ? ARM::dsub_0 : ARM::qsub_0); in SelectVLD()
2527 static_assert(ARM::dsub_7 == ARM::dsub_0 + 7 && in SelectVLDSTLane()
2528 ARM::qsub_3 == ARM::qsub_0 + 3, in SelectVLDSTLane()
2530 unsigned Sub0 = is64BitVector ? ARM::dsub_0 : ARM::qsub_0; in SelectVLDSTLane()
2700 CurDAG->SelectNodeTo(N, ARM::MVE_VSHLC, N->getVTList(), ArrayRef(Ops)); in SelectMVE_VSHLC()
2839 CurDAG->getTargetExtractSubreg(ARM::qsub_0 + i, Loc, VT, in SelectMVE_VLD()
2938 uint16_t SubRegs[2] = {ARM::gsub_0, ARM::gsub_1}; in SelectCDE_CXxD()
3066 static_assert(ARM::dsub_7 == ARM::dsub_0 + 7, "Unexpected subreg numbering"); in SelectVLDDup()
3067 unsigned SubIdx = is64BitVector ? ARM::dsub_0 : ARM::qsub_0; in SelectVLDDup()
3128 ARM::ssub_0 + ExtractLane2 / 2, dl, MVT::f32, Val1.getOperand(0)); in tryInsertVectorElt()
3130 ARM::ssub_0 + Lane2 / 2, dl, VT, Ins2.getOperand(0), in tryInsertVectorElt()
3140 ARM::ssub_0 + ExtractLane1 / 2, dl, MVT::f32, Val1.getOperand(0)); in tryInsertVectorElt()
3142 ARM::ssub_0 + ExtractLane2 / 2, dl, MVT::f32, Val2.getOperand(0)); in tryInsertVectorElt()
3144 Inp1 = SDValue(CurDAG->getMachineNode(ARM::VMOVH, dl, MVT::f32, Inp1), 0); in tryInsertVectorElt()
3146 Inp2 = SDValue(CurDAG->getMachineNode(ARM::VMOVH, dl, MVT::f32, Inp2), 0); in tryInsertVectorElt()
3147 SDNode *VINS = CurDAG->getMachineNode(ARM::VINSH, dl, MVT::f32, Inp2, Inp1); in tryInsertVectorElt()
3149 CurDAG->getTargetInsertSubreg(ARM::ssub_0 + Lane2 / 2, dl, MVT::v4f32, in tryInsertVectorElt()
3159 SDNode *VINS = CurDAG->getMachineNode(ARM::VINSH, dl, MVT::f32, Val2, Val1); in tryInsertVectorElt()
3161 CurDAG->getTargetInsertSubreg(ARM::ssub_0 + Lane2 / 2, dl, MVT::v4f32, in tryInsertVectorElt()
3253 Opcode = IsUnsigned ? ARM::MVE_VCVTf16u16_fix : ARM::MVE_VCVTf16s16_fix; in transformFixedFloatingPointConversion()
3255 Opcode = IsUnsigned ? ARM::MVE_VCVTu16f16_fix : ARM::MVE_VCVTs16f16_fix; in transformFixedFloatingPointConversion()
3259 Opcode = IsUnsigned ? ARM::MVE_VCVTf32u32_fix : ARM::MVE_VCVTf32s32_fix; in transformFixedFloatingPointConversion()
3261 Opcode = IsUnsigned ? ARM::MVE_VCVTu32f32_fix : ARM::MVE_VCVTs32f32_fix; in transformFixedFloatingPointConversion()
3299 Opcode = IsUnsigned ? ARM::MVE_VCVTu16f16_fix : ARM::MVE_VCVTs16f16_fix; in tryFP_TO_INT()
3302 Opcode = IsUnsigned ? ARM::MVE_VCVTu32f32_fix : ARM::MVE_VCVTs32f32_fix; in tryFP_TO_INT()
3340 ? (Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX) in tryV6T2BitfieldExtractOp()
3341 : (Subtarget->isThumb() ? ARM::t2UBFX : ARM::UBFX); in tryV6T2BitfieldExtractOp()
3372 Opc = isSigned ? ARM::t2ASRri : ARM::t2LSRri; in tryV6T2BitfieldExtractOp()
3387 CurDAG->SelectNodeTo(N, ARM::MOVsi, MVT::i32, Ops); in tryV6T2BitfieldExtractOp()
3502 unsigned Opcode = Subtarget->isThumb2() ? ARM::t2ABS : ARM::ABS; in tryABSOp()
3515 Opcode = Subtarget->isThumb() ? ARM::tCMP_SWAP_8 : ARM::CMP_SWAP_8; in SelectCMP_SWAP()
3517 Opcode = Subtarget->isThumb() ? ARM::tCMP_SWAP_16 : ARM::CMP_SWAP_16; in SelectCMP_SWAP()
3519 Opcode = Subtarget->isThumb() ? ARM::tCMP_SWAP_32 : ARM::CMP_SWAP_32; in SelectCMP_SWAP()
3578 Opc = (Opc == ARM::tLSLri) ? ARM::t2LSLri : ARM::t2LSRri; in SelectCMPZ()
3584 SDValue Ops[] = {CurDAG->getRegister(ARM::CPSR, MVT::i32), Src, in SelectCMPZ()
3593 NewN = EmitShift(ARM::tLSLri, X, 31 - Range->first); in SelectCMPZ()
3597 NewN = EmitShift(ARM::tLSRri, X, Range->second); in SelectCMPZ()
3602 NewN = EmitShift(ARM::tLSLri, X, 31 - Range->first); in SelectCMPZ()
3609 NewN = EmitShift(ARM::tLSLri, X, 31 - Range->first); in SelectCMPZ()
3610 NewN = EmitShift(ARM::tLSRri, SDValue(NewN, 0), in SelectCMPZ()
3662 cast<RegisterSDNode>(Ptr.getOperand(1))->getReg() == ARM::SP && in Select()
3665 CurDAG->getRegister(ARM::SP, MVT::i32), in Select()
3671 CurDAG->getMachineNode(ARM::tSTRspi, dl, MVT::Other, Ops); in Select()
3716 ResNode = CurDAG->getMachineNode(ARM::tLDRpci, dl, MVT::i32, MVT::Other, in Select()
3726 ResNode = CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other, in Select()
3757 CurDAG->SelectNodeTo(N, ARM::tADDframe, MVT::i32, TFI, in Select()
3762 ARM::t2ADDri : ARM::ADDri); in Select()
3811 CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops); in Select()
3816 CurDAG->SelectNodeTo(N, ARM::ADDrsi, MVT::i32, Ops); in Select()
3830 CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops); in Select()
3835 CurDAG->SelectNodeTo(N, ARM::RSBrsi, MVT::i32, Ops); in Select()
3872 SDValue Ops[] = {CurDAG->getRegister(ARM::CPSR, MVT::i32), in Select()
3875 ReplaceNode(N, CurDAG->getMachineNode(ARM::tBIC, dl, MVT::i32, Ops)); in Select()
3882 CurDAG->getMachineNode(ARM::t2BICrr, dl, MVT::i32, Ops)); in Select()
3897 ? ARM::t2MOVTi16 in Select()
3898 : (Subtarget->hasV6T2Ops() ? ARM::MOVTi16 : 0); in Select()
3927 unsigned Opc = Subtarget->isThumb() ? ARM::t2UMAAL : ARM::UMAAL; in Select()
3941 N, CurDAG->getMachineNode(ARM::t2UMLAL, dl, MVT::i32, MVT::i32, Ops)); in Select()
3949 Subtarget->hasV6Ops() ? ARM::UMLAL : ARM::UMLALv5, dl, in Select()
3960 N, CurDAG->getMachineNode(ARM::t2SMLAL, dl, MVT::i32, MVT::i32, Ops)); in Select()
3968 Subtarget->hasV6Ops() ? ARM::SMLAL : ARM::SMLALv5, dl, in Select()
3996 unsigned Opc = Subtarget->isThumb2() ? ARM::t2SMMLS : ARM::SMMLS; in Select()
4023 SDNode *New = CurDAG->getMachineNode(ARM::t2WhileLoopSetup, dl, MVT::i32, in Select()
4030 SDNode *New = CurDAG->getMachineNode(ARM::t2WhileLoopStart, dl, MVT::Other, in Select()
4041 unsigned Opc = ARM::t2LoopEnd; in Select()
4063 SDNode *New = CurDAG->getMachineNode(ARM::LOADDUAL, dl, in Select()
4065 SDValue Lo = CurDAG->getTargetExtractSubreg(ARM::gsub_0, dl, MVT::i32, in Select()
4067 SDValue Hi = CurDAG->getTargetExtractSubreg(ARM::gsub_1, dl, MVT::i32, in Select()
4094 SDNode *New = CurDAG->getMachineNode(ARM::STOREDUAL, dl, MVT::Other, Ops); in Select()
4105 CurDAG->getMachineNode(ARM::t2LoopDec, dl, in Select()
4125 ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc; in Select()
4150 CurDAG->getMachineNode(ARM::t2LoopDec, dl, in Select()
4157 CurDAG->getMachineNode(ARM::t2LoopEnd, dl, MVT::Other, EndArgs); in Select()
4219 Add = CurDAG->getMachineNode(ARM::t2ADDri, dl, MVT::i32, Ops); in Select()
4221 unsigned Opc = (Addend < 1<<3) ? ARM::tADDi3 : ARM::tADDi8; in Select()
4222 SDValue Ops[] = {CurDAG->getRegister(ARM::CPSR, MVT::i32), X, in Select()
4270 unsigned Opc64[] = {ARM::VZIPd8, ARM::VZIPd16, ARM::VTRNd32}; in Select()
4271 unsigned Opc128[] = {ARM::VZIPq8, ARM::VZIPq16, ARM::VZIPq32}; in Select()
4282 unsigned Opc64[] = {ARM::VUZPd8, ARM::VUZPd16, ARM::VTRNd32}; in Select()
4283 unsigned Opc128[] = {ARM::VUZPq8, ARM::VUZPq16, ARM::VUZPq32}; in Select()
4293 unsigned Opc64[] = {ARM::VTRNd8, ARM::VTRNd16, ARM::VTRNd32}; in Select()
4294 unsigned Opc128[] = {ARM::VTRNq8, ARM::VTRNq16, ARM::VTRNq32}; in Select()
4326 static const uint16_t DOpcodes[] = { ARM::VLD1DUPd8, ARM::VLD1DUPd16, in Select()
4327 ARM::VLD1DUPd32 }; in Select()
4328 static const uint16_t QOpcodes[] = { ARM::VLD1DUPq8, ARM::VLD1DUPq16, in Select()
4329 ARM::VLD1DUPq32 }; in Select()
4335 static const uint16_t Opcodes[] = { ARM::VLD2DUPd8, ARM::VLD2DUPd16, in Select()
4336 ARM::VLD2DUPd32 }; in Select()
4342 static const uint16_t Opcodes[] = { ARM::VLD3DUPd8Pseudo, in Select()
4343 ARM::VLD3DUPd16Pseudo, in Select()
4344 ARM::VLD3DUPd32Pseudo }; in Select()
4350 static const uint16_t Opcodes[] = { ARM::VLD4DUPd8Pseudo, in Select()
4351 ARM::VLD4DUPd16Pseudo, in Select()
4352 ARM::VLD4DUPd32Pseudo }; in Select()
4358 static const uint16_t DOpcodes[] = { ARM::VLD1DUPd8wb_fixed, in Select()
4359 ARM::VLD1DUPd16wb_fixed, in Select()
4360 ARM::VLD1DUPd32wb_fixed }; in Select()
4361 static const uint16_t QOpcodes[] = { ARM::VLD1DUPq8wb_fixed, in Select()
4362 ARM::VLD1DUPq16wb_fixed, in Select()
4363 ARM::VLD1DUPq32wb_fixed }; in Select()
4369 static const uint16_t DOpcodes[] = { ARM::VLD2DUPd8wb_fixed, in Select()
4370 ARM::VLD2DUPd16wb_fixed, in Select()
4371 ARM::VLD2DUPd32wb_fixed, in Select()
4372 ARM::VLD1q64wb_fixed }; in Select()
4373 static const uint16_t QOpcodes0[] = { ARM::VLD2DUPq8EvenPseudo, in Select()
4374 ARM::VLD2DUPq16EvenPseudo, in Select()
4375 ARM::VLD2DUPq32EvenPseudo }; in Select()
4376 static const uint16_t QOpcodes1[] = { ARM::VLD2DUPq8OddPseudoWB_fixed, in Select()
4377 ARM::VLD2DUPq16OddPseudoWB_fixed, in Select()
4378 ARM::VLD2DUPq32OddPseudoWB_fixed }; in Select()
4384 static const uint16_t DOpcodes[] = { ARM::VLD3DUPd8Pseudo_UPD, in Select()
4385 ARM::VLD3DUPd16Pseudo_UPD, in Select()
4386 ARM::VLD3DUPd32Pseudo_UPD, in Select()
4387 ARM::VLD1d64TPseudoWB_fixed }; in Select()
4388 static const uint16_t QOpcodes0[] = { ARM::VLD3DUPq8EvenPseudo, in Select()
4389 ARM::VLD3DUPq16EvenPseudo, in Select()
4390 ARM::VLD3DUPq32EvenPseudo }; in Select()
4391 static const uint16_t QOpcodes1[] = { ARM::VLD3DUPq8OddPseudo_UPD, in Select()
4392 ARM::VLD3DUPq16OddPseudo_UPD, in Select()
4393 ARM::VLD3DUPq32OddPseudo_UPD }; in Select()
4399 static const uint16_t DOpcodes[] = { ARM::VLD4DUPd8Pseudo_UPD, in Select()
4400 ARM::VLD4DUPd16Pseudo_UPD, in Select()
4401 ARM::VLD4DUPd32Pseudo_UPD, in Select()
4402 ARM::VLD1d64QPseudoWB_fixed }; in Select()
4403 static const uint16_t QOpcodes0[] = { ARM::VLD4DUPq8EvenPseudo, in Select()
4404 ARM::VLD4DUPq16EvenPseudo, in Select()
4405 ARM::VLD4DUPq32EvenPseudo }; in Select()
4406 static const uint16_t QOpcodes1[] = { ARM::VLD4DUPq8OddPseudo_UPD, in Select()
4407 ARM::VLD4DUPq16OddPseudo_UPD, in Select()
4408 ARM::VLD4DUPq32OddPseudo_UPD }; in Select()
4414 static const uint16_t DOpcodes[] = { ARM::VLD1d8wb_fixed, in Select()
4415 ARM::VLD1d16wb_fixed, in Select()
4416 ARM::VLD1d32wb_fixed, in Select()
4417 ARM::VLD1d64wb_fixed }; in Select()
4418 static const uint16_t QOpcodes[] = { ARM::VLD1q8wb_fixed, in Select()
4419 ARM::VLD1q16wb_fixed, in Select()
4420 ARM::VLD1q32wb_fixed, in Select()
4421 ARM::VLD1q64wb_fixed }; in Select()
4429 ARM::VLD2d8wb_fixed, ARM::VLD2d16wb_fixed, ARM::VLD2d32wb_fixed, in Select()
4430 ARM::VLD1q64wb_fixed}; in Select()
4431 static const uint16_t QOpcodes[] = {ARM::VLD2q8PseudoWB_fixed, in Select()
4432 ARM::VLD2q16PseudoWB_fixed, in Select()
4433 ARM::VLD2q32PseudoWB_fixed}; in Select()
4436 static const uint16_t Opcodes8[] = {ARM::MVE_VLD20_8, in Select()
4437 ARM::MVE_VLD21_8_wb}; in Select()
4438 static const uint16_t Opcodes16[] = {ARM::MVE_VLD20_16, in Select()
4439 ARM::MVE_VLD21_16_wb}; in Select()
4440 static const uint16_t Opcodes32[] = {ARM::MVE_VLD20_32, in Select()
4441 ARM::MVE_VLD21_32_wb}; in Select()
4449 static const uint16_t DOpcodes[] = { ARM::VLD3d8Pseudo_UPD, in Select()
4450 ARM::VLD3d16Pseudo_UPD, in Select()
4451 ARM::VLD3d32Pseudo_UPD, in Select()
4452 ARM::VLD1d64TPseudoWB_fixed}; in Select()
4453 static const uint16_t QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD, in Select()
4454 ARM::VLD3q16Pseudo_UPD, in Select()
4455 ARM::VLD3q32Pseudo_UPD }; in Select()
4456 static const uint16_t QOpcodes1[] = { ARM::VLD3q8oddPseudo_UPD, in Select()
4457 ARM::VLD3q16oddPseudo_UPD, in Select()
4458 ARM::VLD3q32oddPseudo_UPD }; in Select()
4466 ARM::VLD4d8Pseudo_UPD, ARM::VLD4d16Pseudo_UPD, ARM::VLD4d32Pseudo_UPD, in Select()
4467 ARM::VLD1d64QPseudoWB_fixed}; in Select()
4468 static const uint16_t QOpcodes0[] = {ARM::VLD4q8Pseudo_UPD, in Select()
4469 ARM::VLD4q16Pseudo_UPD, in Select()
4470 ARM::VLD4q32Pseudo_UPD}; in Select()
4471 static const uint16_t QOpcodes1[] = {ARM::VLD4q8oddPseudo_UPD, in Select()
4472 ARM::VLD4q16oddPseudo_UPD, in Select()
4473 ARM::VLD4q32oddPseudo_UPD}; in Select()
4476 static const uint16_t Opcodes8[] = {ARM::MVE_VLD40_8, ARM::MVE_VLD41_8, in Select()
4477 ARM::MVE_VLD42_8, in Select()
4478 ARM::MVE_VLD43_8_wb}; in Select()
4479 static const uint16_t Opcodes16[] = {ARM::MVE_VLD40_16, ARM::MVE_VLD41_16, in Select()
4480 ARM::MVE_VLD42_16, in Select()
4481 ARM::MVE_VLD43_16_wb}; in Select()
4482 static const uint16_t Opcodes32[] = {ARM::MVE_VLD40_32, ARM::MVE_VLD41_32, in Select()
4483 ARM::MVE_VLD42_32, in Select()
4484 ARM::MVE_VLD43_32_wb}; in Select()
4494 ARM::VLD1q8wb_fixed, ARM::VLD1q16wb_fixed, ARM::VLD1q32wb_fixed, in Select()
4495 ARM::VLD1q64wb_fixed}; in Select()
4497 ARM::VLD1d8QPseudoWB_fixed, ARM::VLD1d16QPseudoWB_fixed, in Select()
4498 ARM::VLD1d32QPseudoWB_fixed, ARM::VLD1d64QPseudoWB_fixed}; in Select()
4508 ARM::VLD1d8TPseudoWB_fixed, ARM::VLD1d16TPseudoWB_fixed, in Select()
4509 ARM::VLD1d32TPseudoWB_fixed, ARM::VLD1d64TPseudoWB_fixed}; in Select()
4511 ARM::VLD1q8LowTPseudo_UPD, ARM::VLD1q16LowTPseudo_UPD, in Select()
4512 ARM::VLD1q32LowTPseudo_UPD, ARM::VLD1q64LowTPseudo_UPD}; in Select()
4514 ARM::VLD1q8HighTPseudo_UPD, ARM::VLD1q16HighTPseudo_UPD, in Select()
4515 ARM::VLD1q32HighTPseudo_UPD, ARM::VLD1q64HighTPseudo_UPD}; in Select()
4525 ARM::VLD1d8QPseudoWB_fixed, ARM::VLD1d16QPseudoWB_fixed, in Select()
4526 ARM::VLD1d32QPseudoWB_fixed, ARM::VLD1d64QPseudoWB_fixed}; in Select()
4528 ARM::VLD1q8LowQPseudo_UPD, ARM::VLD1q16LowQPseudo_UPD, in Select()
4529 ARM::VLD1q32LowQPseudo_UPD, ARM::VLD1q64LowQPseudo_UPD}; in Select()
4531 ARM::VLD1q8HighQPseudo_UPD, ARM::VLD1q16HighQPseudo_UPD, in Select()
4532 ARM::VLD1q32HighQPseudo_UPD, ARM::VLD1q64HighQPseudo_UPD}; in Select()
4540 static const uint16_t DOpcodes[] = { ARM::VLD2LNd8Pseudo_UPD, in Select()
4541 ARM::VLD2LNd16Pseudo_UPD, in Select()
4542 ARM::VLD2LNd32Pseudo_UPD }; in Select()
4543 static const uint16_t QOpcodes[] = { ARM::VLD2LNq16Pseudo_UPD, in Select()
4544 ARM::VLD2LNq32Pseudo_UPD }; in Select()
4550 static const uint16_t DOpcodes[] = { ARM::VLD3LNd8Pseudo_UPD, in Select()
4551 ARM::VLD3LNd16Pseudo_UPD, in Select()
4552 ARM::VLD3LNd32Pseudo_UPD }; in Select()
4553 static const uint16_t QOpcodes[] = { ARM::VLD3LNq16Pseudo_UPD, in Select()
4554 ARM::VLD3LNq32Pseudo_UPD }; in Select()
4560 static const uint16_t DOpcodes[] = { ARM::VLD4LNd8Pseudo_UPD, in Select()
4561 ARM::VLD4LNd16Pseudo_UPD, in Select()
4562 ARM::VLD4LNd32Pseudo_UPD }; in Select()
4563 static const uint16_t QOpcodes[] = { ARM::VLD4LNq16Pseudo_UPD, in Select()
4564 ARM::VLD4LNq32Pseudo_UPD }; in Select()
4570 static const uint16_t DOpcodes[] = { ARM::VST1d8wb_fixed, in Select()
4571 ARM::VST1d16wb_fixed, in Select()
4572 ARM::VST1d32wb_fixed, in Select()
4573 ARM::VST1d64wb_fixed }; in Select()
4574 static const uint16_t QOpcodes[] = { ARM::VST1q8wb_fixed, in Select()
4575 ARM::VST1q16wb_fixed, in Select()
4576 ARM::VST1q32wb_fixed, in Select()
4577 ARM::VST1q64wb_fixed }; in Select()
4585 ARM::VST2d8wb_fixed, ARM::VST2d16wb_fixed, ARM::VST2d32wb_fixed, in Select()
4586 ARM::VST1q64wb_fixed}; in Select()
4587 static const uint16_t QOpcodes[] = {ARM::VST2q8PseudoWB_fixed, in Select()
4588 ARM::VST2q16PseudoWB_fixed, in Select()
4589 ARM::VST2q32PseudoWB_fixed}; in Select()
4597 static const uint16_t DOpcodes[] = { ARM::VST3d8Pseudo_UPD, in Select()
4598 ARM::VST3d16Pseudo_UPD, in Select()
4599 ARM::VST3d32Pseudo_UPD, in Select()
4600 ARM::VST1d64TPseudoWB_fixed}; in Select()
4601 static const uint16_t QOpcodes0[] = { ARM::VST3q8Pseudo_UPD, in Select()
4602 ARM::VST3q16Pseudo_UPD, in Select()
4603 ARM::VST3q32Pseudo_UPD }; in Select()
4604 static const uint16_t QOpcodes1[] = { ARM::VST3q8oddPseudo_UPD, in Select()
4605 ARM::VST3q16oddPseudo_UPD, in Select()
4606 ARM::VST3q32oddPseudo_UPD }; in Select()
4614 ARM::VST4d8Pseudo_UPD, ARM::VST4d16Pseudo_UPD, ARM::VST4d32Pseudo_UPD, in Select()
4615 ARM::VST1d64QPseudoWB_fixed}; in Select()
4616 static const uint16_t QOpcodes0[] = {ARM::VST4q8Pseudo_UPD, in Select()
4617 ARM::VST4q16Pseudo_UPD, in Select()
4618 ARM::VST4q32Pseudo_UPD}; in Select()
4619 static const uint16_t QOpcodes1[] = {ARM::VST4q8oddPseudo_UPD, in Select()
4620 ARM::VST4q16oddPseudo_UPD, in Select()
4621 ARM::VST4q32oddPseudo_UPD}; in Select()
4630 static const uint16_t DOpcodes[] = { ARM::VST1q8wb_fixed, in Select()
4631 ARM::VST1q16wb_fixed, in Select()
4632 ARM::VST1q32wb_fixed, in Select()
4633 ARM::VST1q64wb_fixed}; in Select()
4634 static const uint16_t QOpcodes[] = { ARM::VST1d8QPseudoWB_fixed, in Select()
4635 ARM::VST1d16QPseudoWB_fixed, in Select()
4636 ARM::VST1d32QPseudoWB_fixed, in Select()
4637 ARM::VST1d64QPseudoWB_fixed }; in Select()
4646 static const uint16_t DOpcodes[] = { ARM::VST1d8TPseudoWB_fixed, in Select()
4647 ARM::VST1d16TPseudoWB_fixed, in Select()
4648 ARM::VST1d32TPseudoWB_fixed, in Select()
4649 ARM::VST1d64TPseudoWB_fixed }; in Select()
4650 static const uint16_t QOpcodes0[] = { ARM::VST1q8LowTPseudo_UPD, in Select()
4651 ARM::VST1q16LowTPseudo_UPD, in Select()
4652 ARM::VST1q32LowTPseudo_UPD, in Select()
4653 ARM::VST1q64LowTPseudo_UPD }; in Select()
4654 static const uint16_t QOpcodes1[] = { ARM::VST1q8HighTPseudo_UPD, in Select()
4655 ARM::VST1q16HighTPseudo_UPD, in Select()
4656 ARM::VST1q32HighTPseudo_UPD, in Select()
4657 ARM::VST1q64HighTPseudo_UPD }; in Select()
4666 static const uint16_t DOpcodes[] = { ARM::VST1d8QPseudoWB_fixed, in Select()
4667 ARM::VST1d16QPseudoWB_fixed, in Select()
4668 ARM::VST1d32QPseudoWB_fixed, in Select()
4669 ARM::VST1d64QPseudoWB_fixed }; in Select()
4670 static const uint16_t QOpcodes0[] = { ARM::VST1q8LowQPseudo_UPD, in Select()
4671 ARM::VST1q16LowQPseudo_UPD, in Select()
4672 ARM::VST1q32LowQPseudo_UPD, in Select()
4673 ARM::VST1q64LowQPseudo_UPD }; in Select()
4674 static const uint16_t QOpcodes1[] = { ARM::VST1q8HighQPseudo_UPD, in Select()
4675 ARM::VST1q16HighQPseudo_UPD, in Select()
4676 ARM::VST1q32HighQPseudo_UPD, in Select()
4677 ARM::VST1q64HighQPseudo_UPD }; in Select()
4684 static const uint16_t DOpcodes[] = { ARM::VST2LNd8Pseudo_UPD, in Select()
4685 ARM::VST2LNd16Pseudo_UPD, in Select()
4686 ARM::VST2LNd32Pseudo_UPD }; in Select()
4687 static const uint16_t QOpcodes[] = { ARM::VST2LNq16Pseudo_UPD, in Select()
4688 ARM::VST2LNq32Pseudo_UPD }; in Select()
4694 static const uint16_t DOpcodes[] = { ARM::VST3LNd8Pseudo_UPD, in Select()
4695 ARM::VST3LNd16Pseudo_UPD, in Select()
4696 ARM::VST3LNd32Pseudo_UPD }; in Select()
4697 static const uint16_t QOpcodes[] = { ARM::VST3LNq16Pseudo_UPD, in Select()
4698 ARM::VST3LNq32Pseudo_UPD }; in Select()
4704 static const uint16_t DOpcodes[] = { ARM::VST4LNd8Pseudo_UPD, in Select()
4705 ARM::VST4LNd16Pseudo_UPD, in Select()
4706 ARM::VST4LNd32Pseudo_UPD }; in Select()
4707 static const uint16_t QOpcodes[] = { ARM::VST4LNq16Pseudo_UPD, in Select()
4708 ARM::VST4LNq32Pseudo_UPD }; in Select()
4727 Opc = (IntNo == Intrinsic::arm_mrrc ? ARM::t2MRRC : ARM::t2MRRC2); in Select()
4729 Opc = (IntNo == Intrinsic::arm_mrrc ? ARM::MRRC : ARM::MRRC2); in Select()
4739 if (Opc != ARM::MRRC2) { in Select()
4760 unsigned NewOpc = isThumb ? (IsAcquire ? ARM::t2LDAEXD : ARM::t2LDREXD) in Select()
4761 : (IsAcquire ? ARM::LDAEXD : ARM::LDREXD); in Select()
4788 CurDAG->getTargetConstant(ARM::gsub_0, dl, MVT::i32); in Select()
4801 CurDAG->getTargetConstant(ARM::gsub_1, dl, MVT::i32); in Select()
4839 unsigned NewOpc = isThumb ? (IsRelease ? ARM::t2STLEXD : ARM::t2STREXD) in Select()
4840 : (IsRelease ? ARM::STLEXD : ARM::STREXD); in Select()
4852 static const uint16_t DOpcodes[] = { ARM::VLD1d8, ARM::VLD1d16, in Select()
4853 ARM::VLD1d32, ARM::VLD1d64 }; in Select()
4854 static const uint16_t QOpcodes[] = { ARM::VLD1q8, ARM::VLD1q16, in Select()
4855 ARM::VLD1q32, ARM::VLD1q64}; in Select()
4861 static const uint16_t DOpcodes[] = { ARM::VLD1q8, ARM::VLD1q16, in Select()
4862 ARM::VLD1q32, ARM::VLD1q64 }; in Select()
4863 static const uint16_t QOpcodes[] = { ARM::VLD1d8QPseudo, in Select()
4864 ARM::VLD1d16QPseudo, in Select()
4865 ARM::VLD1d32QPseudo, in Select()
4866 ARM::VLD1d64QPseudo }; in Select()
4872 static const uint16_t DOpcodes[] = { ARM::VLD1d8TPseudo, in Select()
4873 ARM::VLD1d16TPseudo, in Select()
4874 ARM::VLD1d32TPseudo, in Select()
4875 ARM::VLD1d64TPseudo }; in Select()
4876 static const uint16_t QOpcodes0[] = { ARM::VLD1q8LowTPseudo_UPD, in Select()
4877 ARM::VLD1q16LowTPseudo_UPD, in Select()
4878 ARM::VLD1q32LowTPseudo_UPD, in Select()
4879 ARM::VLD1q64LowTPseudo_UPD }; in Select()
4880 static const uint16_t QOpcodes1[] = { ARM::VLD1q8HighTPseudo, in Select()
4881 ARM::VLD1q16HighTPseudo, in Select()
4882 ARM::VLD1q32HighTPseudo, in Select()
4883 ARM::VLD1q64HighTPseudo }; in Select()
4889 static const uint16_t DOpcodes[] = { ARM::VLD1d8QPseudo, in Select()
4890 ARM::VLD1d16QPseudo, in Select()
4891 ARM::VLD1d32QPseudo, in Select()
4892 ARM::VLD1d64QPseudo }; in Select()
4893 static const uint16_t QOpcodes0[] = { ARM::VLD1q8LowQPseudo_UPD, in Select()
4894 ARM::VLD1q16LowQPseudo_UPD, in Select()
4895 ARM::VLD1q32LowQPseudo_UPD, in Select()
4896 ARM::VLD1q64LowQPseudo_UPD }; in Select()
4897 static const uint16_t QOpcodes1[] = { ARM::VLD1q8HighQPseudo, in Select()
4898 ARM::VLD1q16HighQPseudo, in Select()
4899 ARM::VLD1q32HighQPseudo, in Select()
4900 ARM::VLD1q64HighQPseudo }; in Select()
4906 static const uint16_t DOpcodes[] = { ARM::VLD2d8, ARM::VLD2d16, in Select()
4907 ARM::VLD2d32, ARM::VLD1q64 }; in Select()
4908 static const uint16_t QOpcodes[] = { ARM::VLD2q8Pseudo, ARM::VLD2q16Pseudo, in Select()
4909 ARM::VLD2q32Pseudo }; in Select()
4915 static const uint16_t DOpcodes[] = { ARM::VLD3d8Pseudo, in Select()
4916 ARM::VLD3d16Pseudo, in Select()
4917 ARM::VLD3d32Pseudo, in Select()
4918 ARM::VLD1d64TPseudo }; in Select()
4919 static const uint16_t QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD, in Select()
4920 ARM::VLD3q16Pseudo_UPD, in Select()
4921 ARM::VLD3q32Pseudo_UPD }; in Select()
4922 static const uint16_t QOpcodes1[] = { ARM::VLD3q8oddPseudo, in Select()
4923 ARM::VLD3q16oddPseudo, in Select()
4924 ARM::VLD3q32oddPseudo }; in Select()
4930 static const uint16_t DOpcodes[] = { ARM::VLD4d8Pseudo, in Select()
4931 ARM::VLD4d16Pseudo, in Select()
4932 ARM::VLD4d32Pseudo, in Select()
4933 ARM::VLD1d64QPseudo }; in Select()
4934 static const uint16_t QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD, in Select()
4935 ARM::VLD4q16Pseudo_UPD, in Select()
4936 ARM::VLD4q32Pseudo_UPD }; in Select()
4937 static const uint16_t QOpcodes1[] = { ARM::VLD4q8oddPseudo, in Select()
4938 ARM::VLD4q16oddPseudo, in Select()
4939 ARM::VLD4q32oddPseudo }; in Select()
4945 static const uint16_t DOpcodes[] = { ARM::VLD2DUPd8, ARM::VLD2DUPd16, in Select()
4946 ARM::VLD2DUPd32, ARM::VLD1q64 }; in Select()
4947 static const uint16_t QOpcodes0[] = { ARM::VLD2DUPq8EvenPseudo, in Select()
4948 ARM::VLD2DUPq16EvenPseudo, in Select()
4949 ARM::VLD2DUPq32EvenPseudo }; in Select()
4950 static const uint16_t QOpcodes1[] = { ARM::VLD2DUPq8OddPseudo, in Select()
4951 ARM::VLD2DUPq16OddPseudo, in Select()
4952 ARM::VLD2DUPq32OddPseudo }; in Select()
4959 static const uint16_t DOpcodes[] = { ARM::VLD3DUPd8Pseudo, in Select()
4960 ARM::VLD3DUPd16Pseudo, in Select()
4961 ARM::VLD3DUPd32Pseudo, in Select()
4962 ARM::VLD1d64TPseudo }; in Select()
4963 static const uint16_t QOpcodes0[] = { ARM::VLD3DUPq8EvenPseudo, in Select()
4964 ARM::VLD3DUPq16EvenPseudo, in Select()
4965 ARM::VLD3DUPq32EvenPseudo }; in Select()
4966 static const uint16_t QOpcodes1[] = { ARM::VLD3DUPq8OddPseudo, in Select()
4967 ARM::VLD3DUPq16OddPseudo, in Select()
4968 ARM::VLD3DUPq32OddPseudo }; in Select()
4975 static const uint16_t DOpcodes[] = { ARM::VLD4DUPd8Pseudo, in Select()
4976 ARM::VLD4DUPd16Pseudo, in Select()
4977 ARM::VLD4DUPd32Pseudo, in Select()
4978 ARM::VLD1d64QPseudo }; in Select()
4979 static const uint16_t QOpcodes0[] = { ARM::VLD4DUPq8EvenPseudo, in Select()
4980 ARM::VLD4DUPq16EvenPseudo, in Select()
4981 ARM::VLD4DUPq32EvenPseudo }; in Select()
4982 static const uint16_t QOpcodes1[] = { ARM::VLD4DUPq8OddPseudo, in Select()
4983 ARM::VLD4DUPq16OddPseudo, in Select()
4984 ARM::VLD4DUPq32OddPseudo }; in Select()
4991 static const uint16_t DOpcodes[] = { ARM::VLD2LNd8Pseudo, in Select()
4992 ARM::VLD2LNd16Pseudo, in Select()
4993 ARM::VLD2LNd32Pseudo }; in Select()
4994 static const uint16_t QOpcodes[] = { ARM::VLD2LNq16Pseudo, in Select()
4995 ARM::VLD2LNq32Pseudo }; in Select()
5001 static const uint16_t DOpcodes[] = { ARM::VLD3LNd8Pseudo, in Select()
5002 ARM::VLD3LNd16Pseudo, in Select()
5003 ARM::VLD3LNd32Pseudo }; in Select()
5004 static const uint16_t QOpcodes[] = { ARM::VLD3LNq16Pseudo, in Select()
5005 ARM::VLD3LNq32Pseudo }; in Select()
5011 static const uint16_t DOpcodes[] = { ARM::VLD4LNd8Pseudo, in Select()
5012 ARM::VLD4LNd16Pseudo, in Select()
5013 ARM::VLD4LNd32Pseudo }; in Select()
5014 static const uint16_t QOpcodes[] = { ARM::VLD4LNq16Pseudo, in Select()
5015 ARM::VLD4LNq32Pseudo }; in Select()
5021 static const uint16_t DOpcodes[] = { ARM::VST1d8, ARM::VST1d16, in Select()
5022 ARM::VST1d32, ARM::VST1d64 }; in Select()
5023 static const uint16_t QOpcodes[] = { ARM::VST1q8, ARM::VST1q16, in Select()
5024 ARM::VST1q32, ARM::VST1q64 }; in Select()
5030 static const uint16_t DOpcodes[] = { ARM::VST1q8, ARM::VST1q16, in Select()
5031 ARM::VST1q32, ARM::VST1q64 }; in Select()
5032 static const uint16_t QOpcodes[] = { ARM::VST1d8QPseudo, in Select()
5033 ARM::VST1d16QPseudo, in Select()
5034 ARM::VST1d32QPseudo, in Select()
5035 ARM::VST1d64QPseudo }; in Select()
5041 static const uint16_t DOpcodes[] = { ARM::VST1d8TPseudo, in Select()
5042 ARM::VST1d16TPseudo, in Select()
5043 ARM::VST1d32TPseudo, in Select()
5044 ARM::VST1d64TPseudo }; in Select()
5045 static const uint16_t QOpcodes0[] = { ARM::VST1q8LowTPseudo_UPD, in Select()
5046 ARM::VST1q16LowTPseudo_UPD, in Select()
5047 ARM::VST1q32LowTPseudo_UPD, in Select()
5048 ARM::VST1q64LowTPseudo_UPD }; in Select()
5049 static const uint16_t QOpcodes1[] = { ARM::VST1q8HighTPseudo, in Select()
5050 ARM::VST1q16HighTPseudo, in Select()
5051 ARM::VST1q32HighTPseudo, in Select()
5052 ARM::VST1q64HighTPseudo }; in Select()
5058 static const uint16_t DOpcodes[] = { ARM::VST1d8QPseudo, in Select()
5059 ARM::VST1d16QPseudo, in Select()
5060 ARM::VST1d32QPseudo, in Select()
5061 ARM::VST1d64QPseudo }; in Select()
5062 static const uint16_t QOpcodes0[] = { ARM::VST1q8LowQPseudo_UPD, in Select()
5063 ARM::VST1q16LowQPseudo_UPD, in Select()
5064 ARM::VST1q32LowQPseudo_UPD, in Select()
5065 ARM::VST1q64LowQPseudo_UPD }; in Select()
5066 static const uint16_t QOpcodes1[] = { ARM::VST1q8HighQPseudo, in Select()
5067 ARM::VST1q16HighQPseudo, in Select()
5068 ARM::VST1q32HighQPseudo, in Select()
5069 ARM::VST1q64HighQPseudo }; in Select()
5075 static const uint16_t DOpcodes[] = { ARM::VST2d8, ARM::VST2d16, in Select()
5076 ARM::VST2d32, ARM::VST1q64 }; in Select()
5077 static const uint16_t QOpcodes[] = { ARM::VST2q8Pseudo, ARM::VST2q16Pseudo, in Select()
5078 ARM::VST2q32Pseudo }; in Select()
5084 static const uint16_t DOpcodes[] = { ARM::VST3d8Pseudo, in Select()
5085 ARM::VST3d16Pseudo, in Select()
5086 ARM::VST3d32Pseudo, in Select()
5087 ARM::VST1d64TPseudo }; in Select()
5088 static const uint16_t QOpcodes0[] = { ARM::VST3q8Pseudo_UPD, in Select()
5089 ARM::VST3q16Pseudo_UPD, in Select()
5090 ARM::VST3q32Pseudo_UPD }; in Select()
5091 static const uint16_t QOpcodes1[] = { ARM::VST3q8oddPseudo, in Select()
5092 ARM::VST3q16oddPseudo, in Select()
5093 ARM::VST3q32oddPseudo }; in Select()
5099 static const uint16_t DOpcodes[] = { ARM::VST4d8Pseudo, in Select()
5100 ARM::VST4d16Pseudo, in Select()
5101 ARM::VST4d32Pseudo, in Select()
5102 ARM::VST1d64QPseudo }; in Select()
5103 static const uint16_t QOpcodes0[] = { ARM::VST4q8Pseudo_UPD, in Select()
5104 ARM::VST4q16Pseudo_UPD, in Select()
5105 ARM::VST4q32Pseudo_UPD }; in Select()
5106 static const uint16_t QOpcodes1[] = { ARM::VST4q8oddPseudo, in Select()
5107 ARM::VST4q16oddPseudo, in Select()
5108 ARM::VST4q32oddPseudo }; in Select()
5114 static const uint16_t DOpcodes[] = { ARM::VST2LNd8Pseudo, in Select()
5115 ARM::VST2LNd16Pseudo, in Select()
5116 ARM::VST2LNd32Pseudo }; in Select()
5117 static const uint16_t QOpcodes[] = { ARM::VST2LNq16Pseudo, in Select()
5118 ARM::VST2LNq32Pseudo }; in Select()
5124 static const uint16_t DOpcodes[] = { ARM::VST3LNd8Pseudo, in Select()
5125 ARM::VST3LNd16Pseudo, in Select()
5126 ARM::VST3LNd32Pseudo }; in Select()
5127 static const uint16_t QOpcodes[] = { ARM::VST3LNq16Pseudo, in Select()
5128 ARM::VST3LNq32Pseudo }; in Select()
5134 static const uint16_t DOpcodes[] = { ARM::VST4LNd8Pseudo, in Select()
5135 ARM::VST4LNd16Pseudo, in Select()
5136 ARM::VST4LNd32Pseudo }; in Select()
5137 static const uint16_t QOpcodes[] = { ARM::VST4LNq16Pseudo, in Select()
5138 ARM::VST4LNq32Pseudo }; in Select()
5145 static const uint16_t Opcodes[] = {ARM::MVE_VLDRWU32_qi_pre, in Select()
5146 ARM::MVE_VLDRDU64_qi_pre}; in Select()
5153 static const uint16_t Opcodes8[] = {ARM::MVE_VLD20_8, ARM::MVE_VLD21_8}; in Select()
5154 static const uint16_t Opcodes16[] = {ARM::MVE_VLD20_16, in Select()
5155 ARM::MVE_VLD21_16}; in Select()
5156 static const uint16_t Opcodes32[] = {ARM::MVE_VLD20_32, in Select()
5157 ARM::MVE_VLD21_32}; in Select()
5164 static const uint16_t Opcodes8[] = {ARM::MVE_VLD40_8, ARM::MVE_VLD41_8, in Select()
5165 ARM::MVE_VLD42_8, ARM::MVE_VLD43_8}; in Select()
5166 static const uint16_t Opcodes16[] = {ARM::MVE_VLD40_16, ARM::MVE_VLD41_16, in Select()
5167 ARM::MVE_VLD42_16, in Select()
5168 ARM::MVE_VLD43_16}; in Select()
5169 static const uint16_t Opcodes32[] = {ARM::MVE_VLD40_32, ARM::MVE_VLD41_32, in Select()
5170 ARM::MVE_VLD42_32, in Select()
5171 ARM::MVE_VLD43_32}; in Select()
5194 CurDAG->SelectNodeTo(N, ARM::BF16_VCVTB, DestTy, Ops); in Select()
5205 CurDAG->SelectNodeTo(N, ARM::BF16_VCVT, MVT::v4bf16, Ops); in Select()
5210 SelectMVE_LongShift(N, ARM::MVE_URSHRL, true, false); in Select()
5213 SelectMVE_LongShift(N, ARM::MVE_UQSHLL, true, false); in Select()
5216 SelectMVE_LongShift(N, ARM::MVE_SRSHRL, true, false); in Select()
5219 SelectMVE_LongShift(N, ARM::MVE_SQSHLL, true, false); in Select()
5222 SelectMVE_LongShift(N, ARM::MVE_UQRSHLL, false, true); in Select()
5225 SelectMVE_LongShift(N, ARM::MVE_SQRSHRL, false, true); in Select()
5230 SelectMVE_VADCSBC(N, ARM::MVE_VADC, ARM::MVE_VADCI, true, in Select()
5235 SelectMVE_VADCSBC(N, ARM::MVE_VSBC, ARM::MVE_VSBCI, true, in Select()
5246 ARM::MVE_VMLALDAVu16, ARM::MVE_VMLALDAVu32, in Select()
5247 ARM::MVE_VMLALDAVau16, ARM::MVE_VMLALDAVau32, in Select()
5250 ARM::MVE_VMLALDAVs16, ARM::MVE_VMLALDAVs32, in Select()
5251 ARM::MVE_VMLALDAVas16, ARM::MVE_VMLALDAVas32, in Select()
5252 ARM::MVE_VMLALDAVxs16, ARM::MVE_VMLALDAVxs32, in Select()
5253 ARM::MVE_VMLALDAVaxs16, ARM::MVE_VMLALDAVaxs32, in Select()
5254 ARM::MVE_VMLSLDAVs16, ARM::MVE_VMLSLDAVs32, in Select()
5255 ARM::MVE_VMLSLDAVas16, ARM::MVE_VMLSLDAVas32, in Select()
5256 ARM::MVE_VMLSLDAVxs16, ARM::MVE_VMLSLDAVxs32, in Select()
5257 ARM::MVE_VMLSLDAVaxs16, ARM::MVE_VMLSLDAVaxs32, in Select()
5267 ARM::MVE_VRMLALDAVHu32, ARM::MVE_VRMLALDAVHau32, in Select()
5270 ARM::MVE_VRMLALDAVHs32, ARM::MVE_VRMLALDAVHas32, in Select()
5271 ARM::MVE_VRMLALDAVHxs32, ARM::MVE_VRMLALDAVHaxs32, in Select()
5272 ARM::MVE_VRMLSLDAVHs32, ARM::MVE_VRMLSLDAVHas32, in Select()
5273 ARM::MVE_VRMLSLDAVHxs32, ARM::MVE_VRMLSLDAVHaxs32, in Select()
5283 ARM::MVE_VIDUPu8, ARM::MVE_VIDUPu16, ARM::MVE_VIDUPu32, in Select()
5293 ARM::MVE_VDDUPu8, ARM::MVE_VDDUPu16, ARM::MVE_VDDUPu32, in Select()
5303 ARM::MVE_VIWDUPu8, ARM::MVE_VIWDUPu16, ARM::MVE_VIWDUPu32, in Select()
5313 ARM::MVE_VDWDUPu8, ARM::MVE_VDWDUPu16, ARM::MVE_VDWDUPu32, in Select()
5335 Opcode = HasAccum ? ARM::CDE_CX1DA : ARM::CDE_CX1D; in Select()
5340 Opcode = HasAccum ? ARM::CDE_CX2DA : ARM::CDE_CX2D; in Select()
5345 Opcode = HasAccum ? ARM::CDE_CX3DA : ARM::CDE_CX3D; in Select()
5507 Opcode = IsThumb2 ? ARM::t2MRC : ARM::MRC; in tryReadRegister()
5512 Opcode = IsThumb2 ? ARM::t2MRRC : ARM::MRRC; in tryReadRegister()
5531 N, CurDAG->getMachineNode(IsThumb2 ? ARM::t2MRSbanked : ARM::MRSbanked, in tryReadRegister()
5540 .Case("fpscr", ARM::VMRS) in tryReadRegister()
5541 .Case("fpexc", ARM::VMRS_FPEXC) in tryReadRegister()
5542 .Case("fpsid", ARM::VMRS_FPSID) in tryReadRegister()
5543 .Case("mvfr0", ARM::VMRS_MVFR0) in tryReadRegister()
5544 .Case("mvfr1", ARM::VMRS_MVFR1) in tryReadRegister()
5545 .Case("mvfr2", ARM::VMRS_MVFR2) in tryReadRegister()
5546 .Case("fpinst", ARM::VMRS_FPINST) in tryReadRegister()
5547 .Case("fpinst2", ARM::VMRS_FPINST2) in tryReadRegister()
5554 if (Opcode == ARM::VMRS_MVFR2 && !Subtarget->hasFPARMv8Base()) in tryReadRegister()
5576 N, CurDAG->getMachineNode(ARM::t2MRS_M, DL, MVT::i32, MVT::Other, Ops)); in tryReadRegister()
5585 ReplaceNode(N, CurDAG->getMachineNode(IsThumb2 ? ARM::t2MRS_AR : ARM::MRS, in tryReadRegister()
5594 N, CurDAG->getMachineNode(IsThumb2 ? ARM::t2MRSsys_AR : ARM::MRSsys, DL, in tryReadRegister()
5621 Opcode = IsThumb2 ? ARM::t2MCR : ARM::MCR; in tryWriteRegister()
5626 Opcode = IsThumb2 ? ARM::t2MCRR : ARM::MCRR; in tryWriteRegister()
5646 N, CurDAG->getMachineNode(IsThumb2 ? ARM::t2MSRbanked : ARM::MSRbanked, in tryWriteRegister()
5655 .Case("fpscr", ARM::VMSR) in tryWriteRegister()
5656 .Case("fpexc", ARM::VMSR_FPEXC) in tryWriteRegister()
5657 .Case("fpsid", ARM::VMSR_FPSID) in tryWriteRegister()
5658 .Case("fpinst", ARM::VMSR_FPINST) in tryWriteRegister()
5659 .Case("fpinst2", ARM::VMSR_FPINST2) in tryWriteRegister()
5686 ReplaceNode(N, CurDAG->getMachineNode(ARM::t2MSR_M, DL, MVT::Other, Ops)); in tryWriteRegister()
5698 ReplaceNode(N, CurDAG->getMachineNode(IsThumb2 ? ARM::t2MSR_AR : ARM::MSR, in tryWriteRegister()
5775 if ((!IsTiedToChangedOp && (!HasRC || RC != ARM::GPRRegClassID)) in tryInlineAsm()
5791 Register GPVR = MRI.createVirtualRegister(&ARM::GPRPairRegClass); in tryInlineAsm()
5800 SDValue Sub0 = CurDAG->getTargetExtractSubreg(ARM::gsub_0, dl, MVT::i32, in tryInlineAsm()
5802 SDValue Sub1 = CurDAG->getTargetExtractSubreg(ARM::gsub_1, dl, MVT::i32, in tryInlineAsm()
5826 Register GPVR = MRI.createVirtualRegister(&ARM::GPRPairRegClass); in tryInlineAsm()
5842 Flag.setRegClass(ARM::GPRPairRegClassID); in tryInlineAsm()