30   case ARM::MVE_VCTP8:  in VCTPOpcodeToLSTP()
31     return IsDoLoop ? ARM::MVE_DLSTP_8 : ARM::MVE_WLSTP_8;  in VCTPOpcodeToLSTP()
32   case ARM::MVE_VCTP16:  in VCTPOpcodeToLSTP()
33     return IsDoLoop ? ARM::MVE_DLSTP_16 : ARM::MVE_WLSTP_16;  in VCTPOpcodeToLSTP()
34   case ARM::MVE_VCTP32:  in VCTPOpcodeToLSTP()
35     return IsDoLoop ? ARM::MVE_DLSTP_32 : ARM::MVE_WLSTP_32;  in VCTPOpcodeToLSTP()
36   case ARM::MVE_VCTP64:  in VCTPOpcodeToLSTP()
37     return IsDoLoop ? ARM::MVE_DLSTP_64 : ARM::MVE_WLSTP_64;  in VCTPOpcodeToLSTP()
46   case ARM::MVE_VCTP8:  in getTailPredVectorWidth()
48   case ARM::MVE_VCTP16:  in getTailPredVectorWidth()
50   case ARM::MVE_VCTP32:  in getTailPredVectorWidth()
52   case ARM::MVE_VCTP64:  in getTailPredVectorWidth()
62   case ARM::MVE_VCTP8:  in isVCTP()
63   case ARM::MVE_VCTP16:  in isVCTP()
64   case ARM::MVE_VCTP32:  in isVCTP()
65   case ARM::MVE_VCTP64:  in isVCTP()
72   return MI.getOpcode() == ARM::t2DoLoopStart ||  in isDoLoopStart()
73          MI.getOpcode() == ARM::t2DoLoopStartTP;  in isDoLoopStart()
77   return MI.getOpcode() == ARM::t2WhileLoopStart ||  in isWhileLoopStart()
78          MI.getOpcode() == ARM::t2WhileLoopStartLR ||  in isWhileLoopStart()
79          MI.getOpcode() == ARM::t2WhileLoopStartTP;  in isWhileLoopStart()
89   unsigned Op = MI.getOpcode() == ARM::t2WhileLoopStartTP ? 3 : 2;  in getWhileLoopStartTargetBB()
99                                    unsigned BrOpc = ARM::t2Bcc,
102   assert((MI->getOpcode() == ARM::t2WhileLoopStartLR ||
103           MI->getOpcode() == ARM::t2WhileLoopStartTP) &&
109         BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(ARM::t2CMPri));
113     MIB.addReg(ARM::NoRegister);
116         BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(ARM::t2SUBri));
121     MIB.addReg(ARM::NoRegister);
122     MIB.addReg(ARM::CPSR, RegState::Define);
130   MIB.addReg(ARM::CPSR);
137   BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(ARM::tMOVr))  in RevertDoLoopStart()
150       BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(ARM::t2SUBri));
158     MIB.addReg(ARM::CPSR);
168                           unsigned BrOpc = ARM::t2Bcc, bool SkipCmp = false) {
174         BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(ARM::t2CMPri));
178     MIB.addReg(ARM::NoRegister);
186   MIB.addReg(ARM::CPSR);