/freebsd/sys/contrib/device-tree/Bindings/c6x/ |
H A D | clocks.txt | 1 C6X PLL Clock Controllers 2 ------------------------- 4 This is a first-cut support for the SoC clock controllers. This is still 10 - compatible: "ti,c64x+pll" 11 May also have SoC-specific value to support SoC-specific initialization 13 "ti,c6455-pll" 14 "ti,c6457-pll" 15 "ti,c6472-pll" 16 "ti,c6474-pll" 18 - reg: base address and size of register area [all …]
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/freebsd/sys/contrib/device-tree/Bindings/phy/ |
H A D | qcom,qmp-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 4 --- 5 $id: "http://devicetree.org/schemas/phy/qcom,qmp-phy.yaml#" 6 $schema: "http://devicetree.org/meta-schemas/core.yaml#" 11 - Vinod Koul <vkoul@kernel.org> 20 - qcom,ipq6018-qmp-pcie-phy 21 - qcom,ipq6018-qmp-usb3-phy 22 - qcom,ipq8074-qmp-gen3-pcie-phy 23 - qcom,ipq8074-qmp-pcie-phy 24 - qcom,ipq8074-qmp-usb3-phy [all …]
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H A D | nvidia,tegra124-xusb-padctl.txt | 11 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or 12 super-speed USB. Other lanes are for various types of low-speed, full-speed 13 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller 14 contains a software-configurable mux that sits between the I/O controller 17 In addition to per-lane configuration, USB 3.0 ports may require additional 18 settings on a per-board basis. 20 Pads will be represented as children of the top-level XUSB pad controller 23 PHY bindings, as described by the phy-bindings.txt file in this directory. 34 -------------------- 35 - compatible: Must be: [all …]
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H A D | nvidia,tegra124-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or 22 super-speed USB. Other lanes are for various types of low-speed, full-speed 23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller 24 contains a software-configurable mux that sits between the I/O controller [all …]
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H A D | nvidia,tegra210-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xus [all...] |
/freebsd/sys/contrib/device-tree/Bindings/usb/ |
H A D | nvidia,tegra124-xusb.txt | 8 -------------------- 9 - compatible: Must be: 10 - Tegra124: "nvidia,tegra124-xusb" 11 - Tegra132: "nvidia,tegra132-xusb", "nvidia,tegra124-xusb" 12 - Tegra210: "nvidia,tegra210-xusb" 13 - Tegra186: "nvidia,tegra186-xusb" 14 - reg: Must contain the base and length of the xHCI host registers, XUSB FPCI 16 - reg-names: Must contain the following entries: 17 - "hcd" 18 - "fpci" [all …]
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H A D | nvidia,tegra124-xusb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/usb/nvidia,tegra124-xusb.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 20 - description: NVIDIA Tegra124 21 const: nvidia,tegra124-xusb 23 - description: NVIDIA Tegra132 25 - const: nvidia,tegra132-xusb [all …]
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H A D | nvidia,tegra210-xusb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/usb/nvidia,tegra210-xusb.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 18 const: nvidia,tegra210-xusb 22 - description: base and length of the xHCI host registers 23 - description: base and length of the XUSB FPCI registers 24 - description: base and length of the XUSB IPFS registers [all …]
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/freebsd/sys/contrib/device-tree/Bindings/power/reset/ |
H A D | keystone-reset.txt | 1 * Device tree bindings for Texas Instruments keystone reset 3 This node is intended to allow SoC reset in case of software reset 6 The Keystone SoCs can contain up to 4 watchdog timers to reset 7 SoC. Each watchdog timer event input is connected to the Reset Mux 8 block. The Reset Mux block can be configured to cause reset or not. 10 Additionally soft or hard reset can be configured. 14 - compatible: ti,keystone-reset 16 - ti,syscon-pll: phandle/offset pair. The phandle to syscon used to 17 access pll controller registers and the offset to use 18 reset control registers. [all …]
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/freebsd/sys/contrib/device-tree/Bindings/clock/ |
H A D | xgene.txt | 1 Device Tree Clock bindings for APM X-Gene 5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt 8 - compatible : shall be one of the following: 9 "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock 10 "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock 11 "apm,xgene-pmd-clock" - for a X-Gene PMD clock 12 "apm,xgene-device-clock" - for a X-Gene device clock 13 "apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock 14 "apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock 16 Required properties for SoC or PCP PLL clocks: [all …]
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H A D | qcom,mmcc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Qualcomm Multimedia Clock & Reset Controller 10 - Jeffre [all...] |
H A D | baikal,bt1-ccu-div.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-div.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: Baikal-T1 Clock Control Unit Dividers 11 - Serge Semin <fancer.lancer@gmail.com> 14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller 18 IP-blocks or to groups of blocks (clock domains). The transformation is done 19 by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The 21 individually reset by using the domain clocks divider configuration [all …]
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H A D | rockchip,rk3328-cru.txt | 1 * Rockchip RK3328 Clock and Reset Unit 4 controllers within the SoC and also implements a reset controller for SoC 9 - compatible: should be "rockchip,rk3328-cru" 10 - reg: physical base address of the controller and length of memory mapped 12 - #clock-cells: should be 1. 13 - #reset-cells: should be 1. 17 - rockchip,grf: phandle to the syscon managing the "general register files" 18 If missing pll rates are not changeable, due to the missing pll lock status. 22 preprocessor macros in the dt-bindings/clock/rk3328-cru.h headers and can be 23 used in device tree sources. Similar macros exist for the reset sources in [all …]
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H A D | st,stm32-rcc.txt | 1 STMicroelectronics STM32 Reset and Clock Controller 4 The RCC IP is both a reset and a clock controller. 6 Please refer to clock-bindings.txt for common clock controller binding usage. 7 Please also refer to reset.txt for common reset controller binding usage. 10 - compatible: Should be: 11 "st,stm32f42xx-rcc" 12 "st,stm32f469-rcc" 13 "st,stm32f746-rcc" 14 "st,stm32f769-rcc" 16 - reg: should be register base and length as documented in the [all …]
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H A D | qcom,dispcc-sc8280xp.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/clock/qcom,dispcc-sc8280xp.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Qualcomm Display Clock & Reset Controller on SC8280XP 10 - Bjorn Andersson <bjorn.andersson@linaro.org> 17 include/dt-bindings/clock/qcom,dispcc-sc8280xp.h 22 - qcom,sc8280xp-dispcc0 23 - qcom,sc8280xp-dispcc1 27 - description: AHB interface clock, [all …]
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H A D | rockchip,rk3228-cru.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 --- 4 $id: http://devicetree.org/schemas/clock/rockchip,rk3228-cru.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Rockchip RK3228 Clock and Reset Unit (CRU) 10 - Elaine Zhang <zhangqing@rock-chips.com> 11 - Heiko Stuebner <heiko@sntech.de> 15 controllers within the SoC and also implements a reset controller for SoC 19 preprocessor macros in the dt-bindings/clock/rk3228-cru.h headers and can be 20 used in device tree sources. Similar macros exist for the reset sources in [all …]
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H A D | rockchip,rk3228-cru.txt | 1 * Rockchip RK3228 Clock and Reset Unit 4 controllers within the SoC and also implements a reset controller for SoC 9 - compatible: should be "rockchip,rk3228-cru" 10 - reg: physical base address of the controller and length of memory mapped 12 - #clock-cells: should be 1. 13 - #reset-cells: should be 1. 17 - rockchip,grf: phandle to the syscon managing the "general register files" 18 If missing pll rates are not changeable, due to the missing pll lock status. 22 preprocessor macros in the dt-bindings/clock/rk3228-cru.h headers and can be 23 used in device tree sources. Similar macros exist for the reset sources in [all …]
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H A D | rockchip,rk3368-cru.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 --- 4 $id: http://devicetree.org/schemas/clock/rockchip,rk3368-cru.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Rockchip RK3368 Clock and Reset Unit (CRU) 10 - Elaine Zhang <zhangqing@rock-chips.com> 11 - Heiko Stuebner <heiko@sntech.de> 15 controllers within the SoC and also implements a reset controller for SoC 19 preprocessor macros in the dt-bindings/clock/rk3368-cru.h headers and can be 20 used in device tree sources. Similar macros exist for the reset sources in [all …]
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H A D | rockchip,rk3368-cru.txt | 1 * Rockchip RK3368 Clock and Reset Unit 4 controllers within the SoC and also implements a reset controller for SoC 9 - compatible: should be "rockchip,rk3368-cru" 10 - reg: physical base address of the controller and length of memory mapped 12 - #clock-cells: should be 1. 13 - #reset-cells: should be 1. 17 - rockchip,grf: phandle to the syscon managing the "general register files" 18 If missing, pll rates are not changeable, due to the missing pll lock status. 22 preprocessor macros in the dt-bindings/clock/rk3368-cru.h headers and can be 23 used in device tree sources. Similar macros exist for the reset sources in [all …]
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H A D | silabs,si5351.txt | 5 https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf 8 clocks. Si5351a also has a reduced pin-count package (MSOP10) where only 15 - compatible: shall be one of the following: 16 "silabs,si5351a" - Si5351a, QFN20 package 17 "silabs,si5351a-msop" - Si5351a, MSOP10 package 18 "silabs,si5351b" - Si5351b, QFN20 package 19 "silabs,si5351c" - Si5351c, QFN20 package 20 - reg: i2c device address, shall be 0x60 or 0x61. 21 - #clock-cells: from common clock binding; shall be set to 1. 22 - clocks: from common clock binding; list of parent clock [all …]
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/freebsd/sys/contrib/device-tree/src/mips/qca/ |
H A D | ar9132.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 #include <dt-bindings/clock/ath79-clk.h> 7 #address-cells = <1>; 8 #size-cells = <1>; 11 #address-cells = <1>; 12 #size-cells = <0>; 17 clocks = <&pll ATH79_CLK_CPU>; 22 cpuintc: interrupt-controller { 23 compatible = "qca,ar9132-cpu-intc", "qca,ar7100-cpu-intc"; 25 interrupt-controller; [all …]
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H A D | ar9331.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 #include <dt-bindings/clock/ath79-clk.h> 7 #address-cells = <1>; 8 #size-cells = <1>; 11 #address-cells = <1>; 12 #size-cells = <0>; 17 clocks = <&pll ATH79_CLK_CPU>; 22 cpuintc: interrupt-controller { 23 compatible = "qca,ar7100-cpu-intc"; 25 interrupt-controller; [all …]
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/freebsd/sys/contrib/device-tree/Bindings/sound/ |
H A D | adi,adau1701.txt | 5 - compatible: Should contain "adi,adau1701" 6 - reg: The i2c address. Value depends on the state of ADDR0 11 - reset-gpio: A GPIO spec to define which pin is connected to the 12 chip's !RESET pin. If specified, the driver will 13 assert a hardware reset at probe time. 14 - adi,pll-mode-gpios: An array of two GPIO specs to describe the GPIOs 15 the ADAU's PLL config pins are connected to. 19 - adi,pin-config: An array of 12 numerical values selecting one of the 23 - avdd-supply: Power supply for AVDD, providing 3.3V 24 - dvdd-supply: Power supply for DVDD, providing 3.3V [all …]
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/freebsd/sys/contrib/device-tree/Bindings/display/tegra/ |
H A D | nvidia,tegra20-hdmi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-hdmi.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 15 pattern: "^hdmi@[0-9a-f]+$" 19 - enum: 20 - nvidia,tegra20-hdmi 21 - nvidia,tegra30-hdmi [all …]
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/freebsd/sys/contrib/device-tree/Bindings/ufs/ |
H A D | ufs-qcom.txt | 3 UFSPHY nodes are defined to describe on-chip UFS PHY hardware macro. 10 - compatible : compatible list, contains one of the following - 11 "qcom,ufs-phy-qmp-20nm" for 20nm ufs phy, 12 "qcom,ufs-phy-qmp-14nm" for legacy 14nm ufs phy, 13 "qcom,msm8996-ufs-phy-qmp-14nm" for 14nm ufs phy 15 - reg : should contain PHY register address space (mandatory), 16 - reg-names : indicates various resources passed to driver (via reg proptery) by name. 17 Required "reg-names" is "phy_mem". 18 - #phy-cells : This property shall be set to 0 19 - vdda-phy-supply : phandle to main PHY supply for analog domain [all …]
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