Lines Matching +full:pll +full:- +full:reset
1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Multimedia Clock & Reset Controller
10 - Jeffrey Hugo <quic_jhugo@quicinc.com>
11 - Taniya Das <quic_tdas@quicinc.com>
20 - qcom,mmcc-apq8064
21 - qcom,mmcc-apq8084
22 - qcom,mmcc-msm8226
23 - qcom,mmcc-msm8660
24 - qcom,mmcc-msm8960
25 - qcom,mmcc-msm8974
26 - qcom,mmcc-msm8992
27 - qcom,mmcc-msm8994
28 - qcom,mmcc-msm8996
29 - qcom,mmcc-msm8998
30 - qcom,mmcc-sdm630
31 - qcom,mmcc-sdm660
37 clock-names:
41 '#clock-cells':
44 '#reset-cells':
47 '#power-domain-cells':
53 protected-clocks:
57 vdd-gfx-supply:
62 - compatible
63 - reg
64 - '#clock-cells'
65 - '#reset-cells'
66 - '#power-domain-cells'
71 - if:
76 - qcom,mmcc-apq8064
77 - qcom,mmcc-msm8960
82 - description: Board PXO source
83 - description: PLL 3 clock
84 - description: PLL 3 Vote clock
85 - description: DSI phy instance 1 dsi clock
86 - description: DSI phy instance 1 byte clock
87 - description: DSI phy instance 2 dsi clock
88 - description: DSI phy instance 2 byte clock
89 - description: HDMI phy PLL clock
91 clock-names:
93 - const: pxo
94 - const: pll3
95 - const: pll8_vote
96 - const: dsi1pll
97 - const: dsi1pllbyte
98 - const: dsi2pll
99 - const: dsi2pllbyte
100 - const: hdmipll
102 - if:
107 - qcom,mmcc-msm8226
112 - description: Board XO source
113 - description: MMSS GPLL0 voted clock
114 - description: GPLL0 voted clock
115 - description: GPLL1 voted clock
116 - description: GFX3D clock source
117 - description: DSI phy instance 0 dsi clock
118 - description: DSI phy instance 0 byte clock
120 clock-names:
122 - const: xo
123 - const: mmss_gpll0_vote
124 - const: gpll0_vote
125 - const: gpll1_vote
126 - const: gfx3d_clk_src
127 - const: dsi0pll
128 - const: dsi0pllbyte
130 - if:
135 - qcom,mmcc-msm8974
140 - description: Board XO source
141 - description: MMSS GPLL0 voted clock
142 - description: GPLL0 voted clock
143 - description: GPLL1 voted clock
144 - description: GFX3D clock source
145 - description: DSI phy instance 0 dsi clock
146 - description: DSI phy instance 0 byte clock
147 - description: DSI phy instance 1 dsi clock
148 - description: DSI phy instance 1 byte clock
149 - description: HDMI phy PLL clock
150 - description: eDP phy PLL link clock
151 - description: eDP phy PLL vco clock
153 clock-names:
155 - const: xo
156 - const: mmss_gpll0_vote
157 - const: gpll0_vote
158 - const: gpll1_vote
159 - const: gfx3d_clk_src
160 - const: dsi0pll
161 - const: dsi0pllbyte
162 - const: dsi1pll
163 - const: dsi1pllbyte
164 - const: hdmipll
165 - const: edp_link_clk
166 - const: edp_vco_div
168 - if:
173 - qcom,mmcc-apq8084
178 - description: Board XO source
179 - description: Board sleep source
180 - description: MMSS GPLL0 voted clock
181 - description: GPLL0 clock
182 - description: GPLL0 voted clock
183 - description: GPLL1 clock
184 - description: DSI phy instance 0 dsi clock
185 - description: DSI phy instance 0 byte clock
186 - description: DSI phy instance 1 dsi clock
187 - description: DSI phy instance 1 byte clock
188 - description: HDMI phy PLL clock
189 - description: eDP phy PLL link clock
190 - description: eDP phy PLL vco clock
192 clock-names:
194 - const: xo
195 - const: sleep_clk
196 - const: mmss_gpll0_vote
197 - const: gpll0
198 - const: gpll0_vote
199 - const: gpll1
200 - const: dsi0pll
201 - const: dsi0pllbyte
202 - const: dsi1pll
203 - const: dsi1pllbyte
204 - const: hdmipll
205 - const: edp_link_clk
206 - const: edp_vco_div
208 - if:
213 - qcom,mmcc-msm8994
214 - qcom,mmcc-msm8998
215 - qcom,mmcc-sdm630
216 - qcom,mmcc-sdm660
219 - clocks
220 - clock-names
222 - if:
226 const: qcom,mmcc-msm8994
231 - description: Board XO source
232 - description: Global PLL 0 clock
233 - description: MMSS NoC AHB clock
234 - description: GFX3D clock
235 - description: DSI phy instance 0 dsi clock
236 - description: DSI phy instance 0 byte clock
237 - description: DSI phy instance 1 dsi clock
238 - description: DSI phy instance 1 byte clock
239 - description: HDMI phy PLL clock
241 clock-names:
243 - const: xo
244 - const: gpll0
245 - const: mmssnoc_ahb
246 - const: oxili_gfx3d_clk_src
247 - const: dsi0pll
248 - const: dsi0pllbyte
249 - const: dsi1pll
250 - const: dsi1pllbyte
251 - const: hdmipll
253 - if:
257 const: qcom,mmcc-msm8996
262 - description: Board XO source
263 - description: Global PLL 0 clock
264 - description: MMSS NoC AHB clock
265 - description: DSI phy instance 0 dsi clock
266 - description: DSI phy instance 0 byte clock
267 - description: DSI phy instance 1 dsi clock
268 - description: DSI phy instance 1 byte clock
269 - description: HDMI phy PLL clock
271 clock-names:
273 - const: xo
274 - const: gpll0
275 - const: gcc_mmss_noc_cfg_ahb_clk
276 - const: dsi0pll
277 - const: dsi0pllbyte
278 - const: dsi1pll
279 - const: dsi1pllbyte
280 - const: hdmipll
282 - if:
286 const: qcom,mmcc-msm8998
291 - description: Board XO source
292 - description: Global PLL 0 clock
293 - description: DSI phy instance 0 dsi clock
294 - description: DSI phy instance 0 byte clock
295 - description: DSI phy instance 1 dsi clock
296 - description: DSI phy instance 1 byte clock
297 - description: HDMI phy PLL clock
298 - description: DisplayPort phy PLL link clock
299 - description: DisplayPort phy PLL vco clock
300 - description: Global PLL 0 DIV clock
302 clock-names:
304 - const: xo
305 - const: gpll0
306 - const: dsi0dsi
307 - const: dsi0byte
308 - const: dsi1dsi
309 - const: dsi1byte
310 - const: hdmipll
311 - const: dplink
312 - const: dpvco
313 - const: gpll0_div
315 - if:
320 - qcom,mmcc-sdm630
321 - qcom,mmcc-sdm660
326 - description: Board XO source
327 - description: Board sleep source
328 - description: Global PLL 0 clock
329 - description: Global PLL 0 DIV clock
330 - description: DSI phy instance 0 dsi clock
331 - description: DSI phy instance 0 byte clock
332 - description: DSI phy instance 1 dsi clock
333 - description: DSI phy instance 1 byte clock
334 - description: DisplayPort phy PLL link clock
335 - description: DisplayPort phy PLL vco clock
337 clock-names:
339 - const: xo
340 - const: sleep_clk
341 - const: gpll0
342 - const: gpll0_div
343 - const: dsi0pll
344 - const: dsi0pllbyte
345 - const: dsi1pll
346 - const: dsi1pllbyte
347 - const: dp_link_2x_clk_divsel_five
348 - const: dp_vco_divided_clk_src_mux
352 - |
353 clock-controller@4000000 {
354 compatible = "qcom,mmcc-msm8960";
356 #clock-cells = <1>;
357 #reset-cells = <1>;
358 #power-domain-cells = <1>;