Lines Matching +full:pll +full:- +full:reset
3 UFSPHY nodes are defined to describe on-chip UFS PHY hardware macro.
10 - compatible : compatible list, contains one of the following -
11 "qcom,ufs-phy-qmp-20nm" for 20nm ufs phy,
12 "qcom,ufs-phy-qmp-14nm" for legacy 14nm ufs phy,
13 "qcom,msm8996-ufs-phy-qmp-14nm" for 14nm ufs phy
15 - reg : should contain PHY register address space (mandatory),
16 - reg-names : indicates various resources passed to driver (via reg proptery) by name.
17 Required "reg-names" is "phy_mem".
18 - #phy-cells : This property shall be set to 0
19 - vdda-phy-supply : phandle to main PHY supply for analog domain
20 - vdda-pll-supply : phandle to PHY PLL and Power-Gen block power supply
21 - clocks : List of phandle and clock specifier pairs
22 - clock-names : List of clock input name strings sorted in the same
28 - vdda-phy-max-microamp : specifies max. load that can be drawn from phy supply
29 - vdda-pll-max-microamp : specifies max. load that can be drawn from pll supply
30 - vddp-ref-clk-supply : phandle to UFS device ref_clk pad power supply
31 - vddp-ref-clk-max-microamp : specifies max. load that can be drawn from this supply
32 - resets : specifies the PHY reset in the UFS controller
37 compatible = "qcom,ufs-phy-qmp-20nm";
39 reg-names = "phy_mem";
40 #phy-cells = <0>;
41 vdda-phy-supply = <&pma8084_l4>;
42 vdda-pll-supply = <&pma8084_l12>;
43 vdda-phy-max-microamp = <50000>;
44 vdda-pll-max-microamp = <1000>;
45 clock-names = "ref_clk_src",
59 #reset-cells = <1>;
62 phy-names = "ufsphy";