Lines Matching +full:pll +full:- +full:reset
5 https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf
8 clocks. Si5351a also has a reduced pin-count package (MSOP10) where only
15 - compatible: shall be one of the following:
16 "silabs,si5351a" - Si5351a, QFN20 package
17 "silabs,si5351a-msop" - Si5351a, MSOP10 package
18 "silabs,si5351b" - Si5351b, QFN20 package
19 "silabs,si5351c" - Si5351c, QFN20 package
20 - reg: i2c device address, shall be 0x60 or 0x61.
21 - #clock-cells: from common clock binding; shall be set to 1.
22 - clocks: from common clock binding; list of parent clock
26 - #address-cells: shall be set to 1.
27 - #size-cells: shall be set to 0.
30 - silabs,pll-source: pair of (number, source) for each pll. Allows
31 to overwrite clock source of pll A (number=0) or B (number=1).
40 - reg: number of clock output.
43 - silabs,clock-source: source clock of the output divider stage N, shall be
45 1 = multisynth 0 for output clocks 0-3, else multisynth4
48 - silabs,drive-strength: output drive strength in mA, shall be one of {2,4,6,8}.
49 - silabs,multisynth-source: source pll A(0) or B(1) of corresponding multisynth
51 - silabs,pll-master: boolean, multisynth can change pll frequency.
52 - silabs,pll-reset: boolean, clock output can reset its pll.
53 - silabs,disable-state : clock output disable state, shall be
56 2 = clock output is FLOATING (HIGH-Z) when disabled
63 compatible = "fixed-clock";
64 #clock-cells = <0>;
65 clock-frequency = <25000000>;
68 i2c-master-node {
71 si5351a: clock-generator@60 {
72 compatible = "silabs,si5351a-msop";
74 #address-cells = <1>;
75 #size-cells = <0>;
76 #clock-cells = <1>;
80 clock-names = "xtal";
83 silabs,pll-source = <0 0>, <1 0>;
87 * - 8mA output drive strength
88 * - pll0 as clock source of multisynth0
89 * - multisynth0 as clock source of output divider
90 * - multisynth0 can change pll0
91 * - set initial clock frequency of 74.25MHz
95 silabs,drive-strength = <8>;
96 silabs,multisynth-source = <0>;
97 silabs,clock-source = <0>;
98 silabs,pll-master;
99 clock-frequency = <74250000>;
104 * - 4mA output drive strength
105 * - pll1 as clock source of multisynth1
106 * - multisynth1 as clock source of output divider
107 * - multisynth1 can change pll1
111 silabs,drive-strength = <4>;
112 silabs,multisynth-source = <1>;
113 silabs,clock-source = <0>;
114 pll-master;
119 * - xtal as clock source of output divider
123 silabs,clock-source = <2>;