Lines Matching +full:pll +full:- +full:reset

1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/clock/rockchip,rk3228-cru.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip RK3228 Clock and Reset Unit (CRU)
10   - Elaine Zhang <zhangqing@rock-chips.com>
11   - Heiko Stuebner <heiko@sntech.de>
15   controllers within the SoC and also implements a reset controller for SoC
19   preprocessor macros in the dt-bindings/clock/rk3228-cru.h headers and can be
20   used in device tree sources. Similar macros exist for the reset sources in
24   clock-output-names:
25     - "xin24m"      - crystal input                          - required
26     - "ext_i2s"     - external I2S clock                     - optional
27     - "ext_gmac"    - external GMAC clock                    - optional
28     - "ext_hsadc"   - external HSADC clock                   - optional
29     - "phy_50m_out" - output clock of the pll in the mac phy
34       - rockchip,rk3228-cru
39   "#clock-cells":
42   "#reset-cells":
48   clock-names:
55       if missing pll rates are not changeable, due to the missing pll
59   - compatible
60   - reg
61   - "#clock-cells"
62   - "#reset-cells"
67   - |
68     cru: clock-controller@20000000 {
69       compatible = "rockchip,rk3228-cru";
72       #clock-cells = <1>;
73       #reset-cells = <1>;