Lines Matching +full:pll +full:- +full:reset

1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/clock/rockchip,rk3368-cru.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip RK3368 Clock and Reset Unit (CRU)
10   - Elaine Zhang <zhangqing@rock-chips.com>
11   - Heiko Stuebner <heiko@sntech.de>
15   controllers within the SoC and also implements a reset controller for SoC
19   preprocessor macros in the dt-bindings/clock/rk3368-cru.h headers and can be
20   used in device tree sources. Similar macros exist for the reset sources in
24   clock-output-names:
25     - "xin24m"     - crystal input                          - required
26     - "xin32k"     - rtc clock                              - optional
27     - "ext_i2s"    - external I2S clock                     - optional
28     - "ext_gmac"   - external GMAC clock                    - optional
29     - "ext_hsadc"  - external HSADC clock                   - optional
30     - "ext_isp"    - external ISP clock                     - optional
31     - "ext_jtag"   - external JTAG clock                    - optional
32     - "ext_vip"    - external VIP clock                     - optional
33     - "usbotg_out" - output clock of the pll in the otg phy
38       - rockchip,rk3368-cru
43   "#clock-cells":
46   "#reset-cells":
52   clock-names:
59       if missing pll rates are not changeable, due to the missing pll
63   - compatible
64   - reg
65   - "#clock-cells"
66   - "#reset-cells"
71   - |
72     cru: clock-controller@ff760000 {
73       compatible = "rockchip,rk3368-cru";
76       #clock-cells = <1>;
77       #reset-cells = <1>;