Lines Matching +full:pll +full:- +full:reset

1 * Device tree bindings for Texas Instruments keystone reset
3 This node is intended to allow SoC reset in case of software reset
6 The Keystone SoCs can contain up to 4 watchdog timers to reset
7 SoC. Each watchdog timer event input is connected to the Reset Mux
8 block. The Reset Mux block can be configured to cause reset or not.
10 Additionally soft or hard reset can be configured.
14 - compatible:		ti,keystone-reset
16 - ti,syscon-pll:	phandle/offset pair. The phandle to syscon used to
17 			access pll controller registers and the offset to use
18 			reset control registers.
20 - ti,syscon-dev:	phandle/offset pair. The phandle to syscon used to
26 - ti,soft-reset:	Boolean option indicating soft reset.
27 			By default hard reset is used.
29 - ti,wdt-list:		WDT list that can cause SoC reset. It's not related
31 			reset that's triggered by one of WDTs. The list is
34 			reset watchdogs and can be in random order.
37 Setup keystone reset so that in case software reset or
38 WDT0 is triggered it issues hard reset for SoC.
40 pllctrl: pll-controller@2310000 {
41 	compatible = "ti,keystone-pllctrl", "syscon";
45 devctrl: device-state-control@2620000 {
46 	compatible = "ti,keystone-devctrl", "syscon";
50 rstctrl: reset-controller {
51 	compatible = "ti,keystone-reset";
52 	ti,syscon-pll = <&pllctrl 0xe4>;
53 	ti,syscon-dev = <&devctrl 0x328>;
54 	ti,wdt-list = <0>;
58 Setup keystone reset so that in case of software reset or
59 WDT0 or WDT2 is triggered it issues soft reset for SoC.
61 rstctrl: reset-controller {
62 	compatible = "ti,keystone-reset";
63 	ti,syscon-pll = <&pllctrl 0xe4>;
64 	ti,syscon-dev = <&devctrl 0x328>;
65 	ti,wdt-list = <0>, <2>;
66 	ti,soft-reset;