Lines Matching +full:pll +full:- +full:reset

1 STMicroelectronics STM32 Reset and Clock Controller
4 The RCC IP is both a reset and a clock controller.
6 Please refer to clock-bindings.txt for common clock controller binding usage.
7 Please also refer to reset.txt for common reset controller binding usage.
10 - compatible: Should be:
11   "st,stm32f42xx-rcc"
12   "st,stm32f469-rcc"
13   "st,stm32f746-rcc"
14   "st,stm32f769-rcc"
16 - reg: should be register base and length as documented in the
18 - #reset-cells: 1, see below
19 - #clock-cells: 2, device nodes should specify the clock in their "clocks"
23 - clocks: External oscillator clock phandle
24   - high speed external clock signal (HSE)
25   - external I2S clock (I2S_CKIN)
30 		#reset-cells = <1>;
31 		#clock-cells = <2>
32 		compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
48 To simplify the usage and to share bit definition with the reset and clock
50 human-readble format.
53  - include/dt-bindings/mfd/stm32f4-rcc.h
76 	2	CLK_LSI		(low-power clock source)
77 	3	CLK_LSE		(generated from a 32.768 kHz low-speed external
80 	5	CLK_RTC		(real-time clock)
81 	6	PLL_VCO_I2S	(vco frequency of I2S pll)
82 	7	PLL_VCO_SAI	(vco frequency of SAI pll)
83 	8	CLK_LCD		(LCD-TFT)
87 	12	CLK_I2SQ_PDIV	(post divisor of pll i2s q divisor)
88 	13	CLK_SAIQ_PDIV	(post divisor of pll sai q divisor)
92 	16	CLK_HDMI_CEC	(HDMI-CEC clock)
93 	17	CLK_SPDIF	(SPDIF-Rx clock)
124 Device nodes should specify the reset channel required in their "resets"
125 property, containing a phandle to the reset device node and an index specifying
131 For example, for CRC reset: