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/linux/Documentation/devicetree/bindings/net/
H A Dnvidia,tegra234-mgbe.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/nvidia,tegra234-mgbe.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra234 MGBE Multi-Gigabit Ethernet Controller
10 - Thierry Reding <treding@nvidia.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 const: nvidia,tegra234-mgbe
20 reg-names:
22 - const: hypervisor
[all …]
/linux/drivers/clk/
H A Dclk-aspeed.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 #include <linux/clk-provider.h>
10 #include <linux/reset-controller.h>
17 * struct aspeed_gate_data - Aspeed gated clocks
19 * @reset_idx: bit used to reset this IP in the reset register. -1 if no
34 * struct aspeed_clk_gate - Aspeed specific clk_gate structure
35 * @hw: handle between common and hardware-specific interfaces
38 * @reset_idx: bit used to reset this IP in the reset register. -1 if no
40 * @flags: hardware-specific flags
59 * struct aspeed_reset - Aspeed reset controller
[all …]
H A Dclk-aspeed.c1 // SPDX-License-Identifier: GPL-2.0+
4 #define pr_fmt(fmt) "clk-aspeed: " fmt
13 #include <dt-bindings/clock/aspeed-clock.h>
15 #include "clk-aspeed.h"
49 [ASPEED_CLK_GATE_ECLK] = { 0, 6, "eclk-gate", "eclk", 0 }, /* Video Engine */
50 [ASPEED_CLK_GATE_GCLK] = { 1, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
51 [ASPEED_CLK_GATE_MCLK] = { 2, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
52 [ASPEED_CLK_GATE_VCLK] = { 3, -1, "vclk-gate", NULL, 0 }, /* Video Capture */
53 [ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", CLK_IS_CRITICAL }, /* PCIe/PCI */
54 [ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, CLK_IS_CRITICAL }, /* DAC */
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6qdl-gw5904.dtsi4 * This file is dual-licensed: you can use it either under the terms
22 * MA 02110-1301 USA
48 #include <dt-bindings/gpio/gpio.h>
49 #include <dt-bindings/input/linux-event-codes.h>
50 #include <dt-bindings/interrupt-controller/irq.h>
68 stdout-path = &uart2;
72 compatible = "pwm-backlight";
74 brightness-levels = <0 4 8 16 32 64 128 255>;
75 default-brightness-level = <7>;
78 gpio-keys {
[all …]
H A Dimx7d-flex-concentrator.dts1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
11 #include "imx7d-tqma7.dtsi"
14 /delete-node/ &ds1339;
18 compatible = "kam,imx7d-flex-concentrator", "fsl,imx7d";
22 /* 1024 MB - TQMa7D board configuration */
26 reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
27 compatible = "regulator-fixed";
28 regulator-name = "VBUS_USBOTG2";
29 regulator-min-microvolt = <5000000>;
[all …]
/linux/arch/arm64/boot/dts/apm/
H A Dapm-storm.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dts file for AppliedMicro (APM) X-Gene Storm SOC
9 compatible = "apm,xgene-storm";
10 interrupt-parent = <&gic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <2>;
16 #size-cells = <0>;
22 enable-method = "spin-table";
23 cpu-release-addr = <0x1 0x0000fff8>;
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mm-venice-gw7901.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/phy/phy-imx8-pcie.h>
17 compatible = "gw,imx8mm-gw7901", "fsl,imx8mm";
32 stdout-path = &uart2;
40 gpio-keys {
41 compatible = "gpio-keys";
[all …]
H A Dimx8mm-venice-gw7902.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/net/ti-dp83867.h>
12 #include <dt-bindings/phy/phy-imx8-pcie.h>
18 compatible = "gw,imx8mm-gw7902", "fsl,imx8mm";
29 stdout-path = &uart2;
38 compatible = "fixed-clock";
[all …]
H A Dimx8mn-venice-gw7902.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/net/ti-dp83867.h>
17 compatible = "gw,imx8mn-gw7902", "fsl,imx8mn";
26 stdout-path = &uart2;
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
[all …]
H A Dimx8mm-venice-gw7904.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/phy/phy-imx8-pcie.h>
17 compatible = "gateworks,imx8mm-gw7904", "fsl,imx8mm";
25 stdout-path = &uart2;
33 gpio-keys {
34 compatible = "gpio-keys";
[all …]
H A Dimx8mm-venice-gw7903.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/phy/phy-imx8-pcie.h>
17 compatible = "gw,imx8mm-gw7903", "fsl,imx8mm";
27 stdout-path = &uart2;
35 gpio-keys {
36 compatible = "gpio-keys";
[all …]
/linux/drivers/clk/nxp/
H A Dclk-lpc32xx.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include <linux/clk-provider.h>
12 #include <dt-bindings/clock/lpc32xx-clock.h>
244 LPC32XX_CLK_DEFINE(MAC, "mac", 0x0, LPC32XX_CLK_HCLK),
253 * divider register does not contain information about selected rate.
393 regmap_read(clk_regmap, clk->reg, &val); in clk_mask_enable()
395 if (clk->busy_mask && (val & clk->busy_mask) == clk->busy) in clk_mask_enable()
396 return -EBUSY; in clk_mask_enable()
398 return regmap_update_bits(clk_regmap, clk->reg, in clk_mask_enable()
399 clk->enable_mask, clk->enable); in clk_mask_enable()
[all …]
/linux/arch/arm/boot/dts/intel/socfpga/
H A Dsocfpga_arria10.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 enable-method = "altr,socfpga-a10-smp";
19 compatible = "arm,cortex-a9";
22 next-level-cache = <&L2>;
[all …]
H A Dsocfpga.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/reset/altr,rst-mgr.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
22 #address-cells = <1>;
23 #size-cells = <0>;
24 enable-method = "altr,socfpga-smp";
27 compatible = "arm,cortex-a9";
30 next-level-cache = <&L2>;
33 compatible = "arm,cortex-a9";
[all …]
/linux/drivers/net/ethernet/actions/
H A Dowl-emac.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Actions Semi Owl SoCs Ethernet MAC driver
12 #define OWL_EMAC_DRVNAME "owl-emac"
49 #define OWL_EMAC_VAL_MAC_CSR5_TS_DATA 0x03 /* Transferring data HOST -> FIFO */
55 #define OWL_EMAC_VAL_MAC_CSR5_RS_DATA 0x07 /* Transferring data FIFO -> HOST */
59 #define OWL_EMAC_BIT_MAC_CSR5_GTE BIT(11) /* General-purpose timer expiration */
98 #define OWL_EMAC_BIT_MAC_CSR7_GTE BIT(11) /* General-purpose timer overflow */
125 #define OWL_EMAC_MSK_MAC_CSR10_CLKDIV GENMASK(30, 28) /* Clock divider */
133 #define OWL_EMAC_VAL_MAC_CSR10_OPCODE_CDS 0x03 /* Clock divider set */
140 /* General-purpose timer and interrupt mitigation control register */
[all …]
/linux/include/linux/
H A Dstmmac.h1 /* SPDX-License-Identifier: GPL-2.0-only */
51 * specified frequency limit 0f 2.5 MHz, by programming a clock divider
188 /* MAC ----- optional PCS ----- SerDes ----- optional PHY ----- Media
192 * mac_interface is the MAC-side interface, which may be the same
195 * MAC and PCS, and phy_interface describes the interface mode
199 /* phy_interface is the PHY-side interface - the interface used by
/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-tegra.c1 // SPDX-License-Identifier: GPL-2.0-only
11 "rx-pcs", "tx", "tx-pcs", "mac-divider", "mac", "mgbe", "ptp-ref", "mac"
64 clk_bulk_disable_unprepare(ARRAY_SIZE(mgbe_clks), mgbe->clks); in tegra_mgbe_suspend()
66 return reset_control_assert(mgbe->rst_mac); in tegra_mgbe_suspend()
75 err = clk_bulk_prepare_enable(ARRAY_SIZE(mgbe_clks), mgbe->clks); in tegra_mgbe_resume()
79 err = reset_control_deassert(mgbe->rst_mac); in tegra_mgbe_resume()
84 writel(MAC_SBD_INTR, mgbe->regs + MGBE_WRAP_COMMON_INTR_ENABLE); in tegra_mgbe_resume()
87 writel(MGBE_SID, mgbe->hv + MGBE_WRAP_AXI_ASID0_CTRL); in tegra_mgbe_resume()
89 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_STATUS); in tegra_mgbe_resume()
91 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL); in tegra_mgbe_resume()
[all …]
/linux/drivers/net/ethernet/rdc/
H A Dr6040.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * RDC R6040 Fast Ethernet MAC support
7 * Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
8 * Copyright (C) 2007-2012 Florian Fainelli <f.fainelli@gmail.com>
43 /* RDC MAC I/O Size */
46 /* MAX RDC MAC */
49 /* MAC registers */
57 #define MAC_RST 0x0001 /* Reset the MAC */
62 #define TM2TX 0x0001 /* Trigger MAC to transmit */
66 #define TX_FIFO_UNDR 0x0200 /* TX FIFO under-run */
[all …]
/linux/drivers/net/dsa/b53/
H A Db53_regs.h5 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
101 /* Power-down mode control */
121 * Override Ports 0-7 State on devices with xMII interfaces (8 bit)
236 /* Ingress mirror divider register (16 bit) */
240 /* Ingress mirror MAC address register (48 bit) */
246 /* Egress mirror divider register (16 bit) */
249 /* Egress mirror MAC address register (48 bit) */
300 /* MAC Address Index Register (48 bit) */
306 /* ARL Table MAC/VID Entry N Registers (64 bit)
344 /* ARL Search MAC/VID Result (64 bit) */
/linux/drivers/gpu/drm/i915/display/
H A Dintel_lvds.c2 * Copyright © 2006-2007 Intel Corporation
67 int divider; member
110 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_lvds_get_hw_state()
115 wakeref = intel_display_power_get_if_enabled(i915, encoder->power_domain); in intel_lvds_get_hw_state()
119 ret = intel_lvds_port_enabled(i915, lvds_encoder->reg, pipe); in intel_lvds_get_hw_state()
121 intel_display_power_put(i915, encoder->power_domain, wakeref); in intel_lvds_get_hw_state()
129 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_lvds_get_config()
133 crtc_state->output_types |= BIT(INTEL_OUTPUT_LVDS); in intel_lvds_get_config()
135 tmp = intel_de_read(dev_priv, lvds_encoder->reg); in intel_lvds_get_config()
145 crtc_state->hw.adjusted_mode.flags |= flags; in intel_lvds_get_config()
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Dam43xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 sys_clkin_ck: clock-sys-clkin-31@40 {
9 #clock-cells = <0>;
10 compatible = "ti,mux-clock";
11 clock-output-names = "sys_clkin_ck";
13 ti,bit-shift = <31>;
17 crystal_freq_sel_ck: clock-crystal-freq-sel-29@40 {
18 #clock-cells = <0>;
19 compatible = "ti,mux-clock";
20 clock-output-names = "crystal_freq_sel_ck";
[all …]
/linux/drivers/clk/ingenic/
H A Dx1000-cgu.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/ingenic,x1000-cgu.h>
70 usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); in x1000_otg_phy_recalc_rate()
119 return -EINVAL; in x1000_otg_phy_set_rate()
122 spin_lock_irqsave(&cgu->lock, flags); in x1000_otg_phy_set_rate()
124 usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); in x1000_otg_phy_set_rate()
127 writel(usbpcr1, cgu->base + CGU_REG_USBPCR1); in x1000_otg_phy_set_rate()
129 spin_unlock_irqrestore(&cgu->lock, flags); in x1000_otg_phy_set_rate()
135 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in x1000_usb_phy_enable()
[all …]
/linux/drivers/net/ethernet/mediatek/
H A Dmtk_eth_soc.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
24 #include <linux/pcs/pcs-mtk-lynxi.h>
34 static int mtk_msg_level = -1;
36 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
294 __raw_writel(val, eth->base + reg); in mtk_w32()
299 return __raw_readl(eth->base + reg); in mtk_r32()
325 dev_err(eth->dev, "mdio: MDIO timeout\n"); in mtk_mdio_busy_wait()
[all …]
/linux/drivers/net/ethernet/alacritech/
H A Dslic.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 #include <linux/dma-mapping.h>
133 * 31-8 - phy addr of set of contiguous hdr buffers
134 * 7-0 - number of buffers passed
135 * Buffers are 256 bytes long on 256-byte boundaries.
144 * 31-5 - phy addr of host command buffer
145 * 4-0 - length of cmd in multiples of 32 bytes
152 * 31-8 - phy addr of set of contiguous response buffers
153 * 7-0 - number of buffers passed
154 * Buffers are 32 bytes long on 32-byte boundaries.
[all …]
/linux/drivers/net/dsa/sja1105/
H A Dsja1105_clocking.c1 // SPDX-License-Identifier: BSD-3-Clause
2 /* Copyright 2016-2018 NXP
3 * Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
107 sja1105_packing(buf, &idiv->clksrc, 28, 24, size, op); in sja1105_cgu_idiv_packing()
108 sja1105_packing(buf, &idiv->autoblock, 11, 11, size, op); in sja1105_cgu_idiv_packing()
109 sja1105_packing(buf, &idiv->idiv, 5, 2, size, op); in sja1105_cgu_idiv_packing()
110 sja1105_packing(buf, &idiv->pd, 0, 0, size, op); in sja1105_cgu_idiv_packing()
116 const struct sja1105_regs *regs = priv->info->regs; in sja1105_cgu_idiv_config()
117 struct device *dev = priv->ds->dev; in sja1105_cgu_idiv_config()
121 if (regs->cgu_idiv[port] == SJA1105_RSV_ADDR) in sja1105_cgu_idiv_config()
[all …]

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