Lines Matching +full:mac +full:- +full:divider
1 // SPDX-License-Identifier: GPL-2.0-only
11 "rx-pcs", "tx", "tx-pcs", "mac-divider", "mac", "mgbe", "ptp-ref", "mac"
64 clk_bulk_disable_unprepare(ARRAY_SIZE(mgbe_clks), mgbe->clks); in tegra_mgbe_suspend()
66 return reset_control_assert(mgbe->rst_mac); in tegra_mgbe_suspend()
75 err = clk_bulk_prepare_enable(ARRAY_SIZE(mgbe_clks), mgbe->clks); in tegra_mgbe_resume()
79 err = reset_control_deassert(mgbe->rst_mac); in tegra_mgbe_resume()
84 writel(MAC_SBD_INTR, mgbe->regs + MGBE_WRAP_COMMON_INTR_ENABLE); in tegra_mgbe_resume()
87 writel(MGBE_SID, mgbe->hv + MGBE_WRAP_AXI_ASID0_CTRL); in tegra_mgbe_resume()
89 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_STATUS); in tegra_mgbe_resume()
91 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL); in tegra_mgbe_resume()
93 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL); in tegra_mgbe_resume()
96 err = readl_poll_timeout(mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL, value, in tegra_mgbe_resume()
100 dev_err(mgbe->dev, "timeout waiting for TX lane to become enabled\n"); in tegra_mgbe_resume()
101 clk_bulk_disable_unprepare(ARRAY_SIZE(mgbe_clks), mgbe->clks); in tegra_mgbe_resume()
107 clk_bulk_disable_unprepare(ARRAY_SIZE(mgbe_clks), mgbe->clks); in tegra_mgbe_resume()
118 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_up()
120 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_up()
122 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_up()
124 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_up()
126 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_up()
128 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_up()
131 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_up()
133 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_up()
136 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_up()
138 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_up()
140 err = readl_poll_timeout(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL, value, in mgbe_uphy_lane_bringup_serdes_up()
144 dev_err(mgbe->dev, "timeout waiting for RX calibration to become enabled\n"); in mgbe_uphy_lane_bringup_serdes_up()
149 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_up()
151 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_up()
153 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_up()
155 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_up()
158 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_up()
160 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_up()
163 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_up()
165 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_up()
168 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_up()
170 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_up()
172 err = readl_poll_timeout(mgbe->xpcs + XPCS_WRAP_IRQ_STATUS, value, in mgbe_uphy_lane_bringup_serdes_up()
176 dev_err(mgbe->dev, "timeout waiting for link to become ready\n"); in mgbe_uphy_lane_bringup_serdes_up()
181 writel(value, mgbe->xpcs + XPCS_WRAP_IRQ_STATUS); in mgbe_uphy_lane_bringup_serdes_up()
191 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_down()
193 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_down()
195 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_down()
197 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_down()
199 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_down()
201 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_down()
203 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_down()
205 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_down()
207 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_down()
209 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_down()
220 mgbe = devm_kzalloc(&pdev->dev, sizeof(*mgbe), GFP_KERNEL); in tegra_mgbe_probe()
222 return -ENOMEM; in tegra_mgbe_probe()
224 mgbe->dev = &pdev->dev; in tegra_mgbe_probe()
232 mgbe->hv = devm_platform_ioremap_resource_byname(pdev, "hypervisor"); in tegra_mgbe_probe()
233 if (IS_ERR(mgbe->hv)) in tegra_mgbe_probe()
234 return PTR_ERR(mgbe->hv); in tegra_mgbe_probe()
236 mgbe->regs = devm_platform_ioremap_resource_byname(pdev, "mac"); in tegra_mgbe_probe()
237 if (IS_ERR(mgbe->regs)) in tegra_mgbe_probe()
238 return PTR_ERR(mgbe->regs); in tegra_mgbe_probe()
240 mgbe->xpcs = devm_platform_ioremap_resource_byname(pdev, "xpcs"); in tegra_mgbe_probe()
241 if (IS_ERR(mgbe->xpcs)) in tegra_mgbe_probe()
242 return PTR_ERR(mgbe->xpcs); in tegra_mgbe_probe()
244 res.addr = mgbe->regs; in tegra_mgbe_probe()
247 mgbe->clks = devm_kcalloc(&pdev->dev, ARRAY_SIZE(mgbe_clks), in tegra_mgbe_probe()
248 sizeof(*mgbe->clks), GFP_KERNEL); in tegra_mgbe_probe()
249 if (!mgbe->clks) in tegra_mgbe_probe()
250 return -ENOMEM; in tegra_mgbe_probe()
253 mgbe->clks[i].id = mgbe_clks[i]; in tegra_mgbe_probe()
255 err = devm_clk_bulk_get(mgbe->dev, ARRAY_SIZE(mgbe_clks), mgbe->clks); in tegra_mgbe_probe()
259 err = clk_bulk_prepare_enable(ARRAY_SIZE(mgbe_clks), mgbe->clks); in tegra_mgbe_probe()
263 /* Perform MAC reset */ in tegra_mgbe_probe()
264 mgbe->rst_mac = devm_reset_control_get(&pdev->dev, "mac"); in tegra_mgbe_probe()
265 if (IS_ERR(mgbe->rst_mac)) { in tegra_mgbe_probe()
266 err = PTR_ERR(mgbe->rst_mac); in tegra_mgbe_probe()
270 err = reset_control_assert(mgbe->rst_mac); in tegra_mgbe_probe()
276 err = reset_control_deassert(mgbe->rst_mac); in tegra_mgbe_probe()
281 mgbe->rst_pcs = devm_reset_control_get(&pdev->dev, "pcs"); in tegra_mgbe_probe()
282 if (IS_ERR(mgbe->rst_pcs)) { in tegra_mgbe_probe()
283 err = PTR_ERR(mgbe->rst_pcs); in tegra_mgbe_probe()
287 err = reset_control_assert(mgbe->rst_pcs); in tegra_mgbe_probe()
293 err = reset_control_deassert(mgbe->rst_pcs); in tegra_mgbe_probe()
297 plat = devm_stmmac_probe_config_dt(pdev, res.mac); in tegra_mgbe_probe()
303 plat->has_xgmac = 1; in tegra_mgbe_probe()
304 plat->flags |= STMMAC_FLAG_TSO_EN; in tegra_mgbe_probe()
305 plat->pmt = 1; in tegra_mgbe_probe()
306 plat->bsp_priv = mgbe; in tegra_mgbe_probe()
308 if (!plat->mdio_node) in tegra_mgbe_probe()
309 plat->mdio_node = of_get_child_by_name(pdev->dev.of_node, "mdio"); in tegra_mgbe_probe()
311 if (!plat->mdio_bus_data) { in tegra_mgbe_probe()
312 plat->mdio_bus_data = devm_kzalloc(&pdev->dev, sizeof(*plat->mdio_bus_data), in tegra_mgbe_probe()
314 if (!plat->mdio_bus_data) { in tegra_mgbe_probe()
315 err = -ENOMEM; in tegra_mgbe_probe()
320 plat->mdio_bus_data->needs_reset = true; in tegra_mgbe_probe()
322 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_STATUS); in tegra_mgbe_probe()
324 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL); in tegra_mgbe_probe()
326 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL); in tegra_mgbe_probe()
329 err = readl_poll_timeout(mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL, value, in tegra_mgbe_probe()
333 dev_err(mgbe->dev, "timeout waiting for TX lane to become enabled\n"); in tegra_mgbe_probe()
337 plat->serdes_powerup = mgbe_uphy_lane_bringup_serdes_up; in tegra_mgbe_probe()
338 plat->serdes_powerdown = mgbe_uphy_lane_bringup_serdes_down; in tegra_mgbe_probe()
340 /* Tx FIFO Size - 128KB */ in tegra_mgbe_probe()
341 plat->tx_fifo_size = 131072; in tegra_mgbe_probe()
342 /* Rx FIFO Size - 192KB */ in tegra_mgbe_probe()
343 plat->rx_fifo_size = 196608; in tegra_mgbe_probe()
346 writel(MAC_SBD_INTR, mgbe->regs + MGBE_WRAP_COMMON_INTR_ENABLE); in tegra_mgbe_probe()
349 writel(MGBE_SID, mgbe->hv + MGBE_WRAP_AXI_ASID0_CTRL); in tegra_mgbe_probe()
351 plat->flags |= STMMAC_FLAG_SERDES_UP_AFTER_PHY_LINKUP; in tegra_mgbe_probe()
353 err = stmmac_dvr_probe(&pdev->dev, plat, &res); in tegra_mgbe_probe()
360 clk_bulk_disable_unprepare(ARRAY_SIZE(mgbe_clks), mgbe->clks); in tegra_mgbe_probe()
367 struct tegra_mgbe *mgbe = get_stmmac_bsp_priv(&pdev->dev); in tegra_mgbe_remove()
369 clk_bulk_disable_unprepare(ARRAY_SIZE(mgbe_clks), mgbe->clks); in tegra_mgbe_remove()
375 { .compatible = "nvidia,tegra234-mgbe", },
386 .name = "tegra-mgbe",