1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0-only 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Device Tree Source for AM43xx clock data 4*724ba675SRob Herring * 5*724ba675SRob Herring * Copyright (C) 2013 Texas Instruments, Inc. 6*724ba675SRob Herring */ 7*724ba675SRob Herring&scm_clocks { 8*724ba675SRob Herring sys_clkin_ck: clock-sys-clkin-31@40 { 9*724ba675SRob Herring #clock-cells = <0>; 10*724ba675SRob Herring compatible = "ti,mux-clock"; 11*724ba675SRob Herring clock-output-names = "sys_clkin_ck"; 12*724ba675SRob Herring clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>; 13*724ba675SRob Herring ti,bit-shift = <31>; 14*724ba675SRob Herring reg = <0x0040>; 15*724ba675SRob Herring }; 16*724ba675SRob Herring 17*724ba675SRob Herring crystal_freq_sel_ck: clock-crystal-freq-sel-29@40 { 18*724ba675SRob Herring #clock-cells = <0>; 19*724ba675SRob Herring compatible = "ti,mux-clock"; 20*724ba675SRob Herring clock-output-names = "crystal_freq_sel_ck"; 21*724ba675SRob Herring clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; 22*724ba675SRob Herring ti,bit-shift = <29>; 23*724ba675SRob Herring reg = <0x0040>; 24*724ba675SRob Herring }; 25*724ba675SRob Herring 26*724ba675SRob Herring sysboot_freq_sel_ck: clock-sysboot-freq-sel-22@44e10040 { 27*724ba675SRob Herring #clock-cells = <0>; 28*724ba675SRob Herring compatible = "ti,mux-clock"; 29*724ba675SRob Herring clock-output-names = "sysboot_freq_sel_ck"; 30*724ba675SRob Herring clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; 31*724ba675SRob Herring ti,bit-shift = <22>; 32*724ba675SRob Herring reg = <0x0040>; 33*724ba675SRob Herring }; 34*724ba675SRob Herring 35*724ba675SRob Herring adc_tsc_fck: clock-adc-tsc-fck { 36*724ba675SRob Herring #clock-cells = <0>; 37*724ba675SRob Herring compatible = "fixed-factor-clock"; 38*724ba675SRob Herring clock-output-names = "adc_tsc_fck"; 39*724ba675SRob Herring clocks = <&sys_clkin_ck>; 40*724ba675SRob Herring clock-mult = <1>; 41*724ba675SRob Herring clock-div = <1>; 42*724ba675SRob Herring }; 43*724ba675SRob Herring 44*724ba675SRob Herring dcan0_fck: clock-dcan0-fck { 45*724ba675SRob Herring #clock-cells = <0>; 46*724ba675SRob Herring compatible = "fixed-factor-clock"; 47*724ba675SRob Herring clock-output-names = "dcan0_fck"; 48*724ba675SRob Herring clocks = <&sys_clkin_ck>; 49*724ba675SRob Herring clock-mult = <1>; 50*724ba675SRob Herring clock-div = <1>; 51*724ba675SRob Herring }; 52*724ba675SRob Herring 53*724ba675SRob Herring dcan1_fck: clock-dcan1-fck { 54*724ba675SRob Herring #clock-cells = <0>; 55*724ba675SRob Herring compatible = "fixed-factor-clock"; 56*724ba675SRob Herring clock-output-names = "dcan1_fck"; 57*724ba675SRob Herring clocks = <&sys_clkin_ck>; 58*724ba675SRob Herring clock-mult = <1>; 59*724ba675SRob Herring clock-div = <1>; 60*724ba675SRob Herring }; 61*724ba675SRob Herring 62*724ba675SRob Herring mcasp0_fck: clock-mcasp0-fck { 63*724ba675SRob Herring #clock-cells = <0>; 64*724ba675SRob Herring compatible = "fixed-factor-clock"; 65*724ba675SRob Herring clock-output-names = "mcasp0_fck"; 66*724ba675SRob Herring clocks = <&sys_clkin_ck>; 67*724ba675SRob Herring clock-mult = <1>; 68*724ba675SRob Herring clock-div = <1>; 69*724ba675SRob Herring }; 70*724ba675SRob Herring 71*724ba675SRob Herring mcasp1_fck: clock-mcasp1-fck { 72*724ba675SRob Herring #clock-cells = <0>; 73*724ba675SRob Herring compatible = "fixed-factor-clock"; 74*724ba675SRob Herring clock-output-names = "mcasp1_fck"; 75*724ba675SRob Herring clocks = <&sys_clkin_ck>; 76*724ba675SRob Herring clock-mult = <1>; 77*724ba675SRob Herring clock-div = <1>; 78*724ba675SRob Herring }; 79*724ba675SRob Herring 80*724ba675SRob Herring smartreflex0_fck: clock-smartreflex0-fck { 81*724ba675SRob Herring #clock-cells = <0>; 82*724ba675SRob Herring compatible = "fixed-factor-clock"; 83*724ba675SRob Herring clock-output-names = "smartreflex0_fck"; 84*724ba675SRob Herring clocks = <&sys_clkin_ck>; 85*724ba675SRob Herring clock-mult = <1>; 86*724ba675SRob Herring clock-div = <1>; 87*724ba675SRob Herring }; 88*724ba675SRob Herring 89*724ba675SRob Herring smartreflex1_fck: clock-smartreflex1-fck { 90*724ba675SRob Herring #clock-cells = <0>; 91*724ba675SRob Herring compatible = "fixed-factor-clock"; 92*724ba675SRob Herring clock-output-names = "smartreflex1_fck"; 93*724ba675SRob Herring clocks = <&sys_clkin_ck>; 94*724ba675SRob Herring clock-mult = <1>; 95*724ba675SRob Herring clock-div = <1>; 96*724ba675SRob Herring }; 97*724ba675SRob Herring 98*724ba675SRob Herring sha0_fck: clock-sha0-fck { 99*724ba675SRob Herring #clock-cells = <0>; 100*724ba675SRob Herring compatible = "fixed-factor-clock"; 101*724ba675SRob Herring clock-output-names = "sha0_fck"; 102*724ba675SRob Herring clocks = <&sys_clkin_ck>; 103*724ba675SRob Herring clock-mult = <1>; 104*724ba675SRob Herring clock-div = <1>; 105*724ba675SRob Herring }; 106*724ba675SRob Herring 107*724ba675SRob Herring aes0_fck: clock-aes0-fck { 108*724ba675SRob Herring #clock-cells = <0>; 109*724ba675SRob Herring compatible = "fixed-factor-clock"; 110*724ba675SRob Herring clock-output-names = "aes0_fck"; 111*724ba675SRob Herring clocks = <&sys_clkin_ck>; 112*724ba675SRob Herring clock-mult = <1>; 113*724ba675SRob Herring clock-div = <1>; 114*724ba675SRob Herring }; 115*724ba675SRob Herring 116*724ba675SRob Herring rng_fck: clock-rng-fck { 117*724ba675SRob Herring #clock-cells = <0>; 118*724ba675SRob Herring compatible = "fixed-factor-clock"; 119*724ba675SRob Herring clock-output-names = "rng_fck"; 120*724ba675SRob Herring clocks = <&sys_clkin_ck>; 121*724ba675SRob Herring clock-mult = <1>; 122*724ba675SRob Herring clock-div = <1>; 123*724ba675SRob Herring }; 124*724ba675SRob Herring 125*724ba675SRob Herring ehrpwm0_tbclk: clock-ehrpwm0-tbclk-0@664 { 126*724ba675SRob Herring #clock-cells = <0>; 127*724ba675SRob Herring compatible = "ti,gate-clock"; 128*724ba675SRob Herring clock-output-names = "ehrpwm0_tbclk"; 129*724ba675SRob Herring clocks = <&l4ls_gclk>; 130*724ba675SRob Herring ti,bit-shift = <0>; 131*724ba675SRob Herring reg = <0x0664>; 132*724ba675SRob Herring }; 133*724ba675SRob Herring 134*724ba675SRob Herring ehrpwm1_tbclk: clock-ehrpwm1-tbclk-1@664 { 135*724ba675SRob Herring #clock-cells = <0>; 136*724ba675SRob Herring compatible = "ti,gate-clock"; 137*724ba675SRob Herring clock-output-names = "ehrpwm1_tbclk"; 138*724ba675SRob Herring clocks = <&l4ls_gclk>; 139*724ba675SRob Herring ti,bit-shift = <1>; 140*724ba675SRob Herring reg = <0x0664>; 141*724ba675SRob Herring }; 142*724ba675SRob Herring 143*724ba675SRob Herring ehrpwm2_tbclk: clock-ehrpwm2-tbclk-2@664 { 144*724ba675SRob Herring #clock-cells = <0>; 145*724ba675SRob Herring compatible = "ti,gate-clock"; 146*724ba675SRob Herring clock-output-names = "ehrpwm2_tbclk"; 147*724ba675SRob Herring clocks = <&l4ls_gclk>; 148*724ba675SRob Herring ti,bit-shift = <2>; 149*724ba675SRob Herring reg = <0x0664>; 150*724ba675SRob Herring }; 151*724ba675SRob Herring 152*724ba675SRob Herring ehrpwm3_tbclk: clock-ehrpwm3-tbclk-4@664 { 153*724ba675SRob Herring #clock-cells = <0>; 154*724ba675SRob Herring compatible = "ti,gate-clock"; 155*724ba675SRob Herring clock-output-names = "ehrpwm3_tbclk"; 156*724ba675SRob Herring clocks = <&l4ls_gclk>; 157*724ba675SRob Herring ti,bit-shift = <4>; 158*724ba675SRob Herring reg = <0x0664>; 159*724ba675SRob Herring }; 160*724ba675SRob Herring 161*724ba675SRob Herring ehrpwm4_tbclk: clock-ehrpwm4-tbclk-5@664 { 162*724ba675SRob Herring #clock-cells = <0>; 163*724ba675SRob Herring compatible = "ti,gate-clock"; 164*724ba675SRob Herring clock-output-names = "ehrpwm4_tbclk"; 165*724ba675SRob Herring clocks = <&l4ls_gclk>; 166*724ba675SRob Herring ti,bit-shift = <5>; 167*724ba675SRob Herring reg = <0x0664>; 168*724ba675SRob Herring }; 169*724ba675SRob Herring 170*724ba675SRob Herring ehrpwm5_tbclk: clock-ehrpwm5-tbclk-6@664 { 171*724ba675SRob Herring #clock-cells = <0>; 172*724ba675SRob Herring compatible = "ti,gate-clock"; 173*724ba675SRob Herring clock-output-names = "ehrpwm5_tbclk"; 174*724ba675SRob Herring clocks = <&l4ls_gclk>; 175*724ba675SRob Herring ti,bit-shift = <6>; 176*724ba675SRob Herring reg = <0x0664>; 177*724ba675SRob Herring }; 178*724ba675SRob Herring}; 179*724ba675SRob Herring&prcm_clocks { 180*724ba675SRob Herring clk_32768_ck: clock-clk-32768 { 181*724ba675SRob Herring #clock-cells = <0>; 182*724ba675SRob Herring compatible = "fixed-clock"; 183*724ba675SRob Herring clock-output-names = "clk_32768_ck"; 184*724ba675SRob Herring clock-frequency = <32768>; 185*724ba675SRob Herring }; 186*724ba675SRob Herring 187*724ba675SRob Herring clk_rc32k_ck: clock-clk-rc32k { 188*724ba675SRob Herring #clock-cells = <0>; 189*724ba675SRob Herring compatible = "fixed-clock"; 190*724ba675SRob Herring clock-output-names = "clk_rc32k_ck"; 191*724ba675SRob Herring clock-frequency = <32768>; 192*724ba675SRob Herring }; 193*724ba675SRob Herring 194*724ba675SRob Herring virt_19200000_ck: clock-virt-19200000 { 195*724ba675SRob Herring #clock-cells = <0>; 196*724ba675SRob Herring compatible = "fixed-clock"; 197*724ba675SRob Herring clock-output-names = "virt_19200000_ck"; 198*724ba675SRob Herring clock-frequency = <19200000>; 199*724ba675SRob Herring }; 200*724ba675SRob Herring 201*724ba675SRob Herring virt_24000000_ck: clock-virt-24000000 { 202*724ba675SRob Herring #clock-cells = <0>; 203*724ba675SRob Herring compatible = "fixed-clock"; 204*724ba675SRob Herring clock-output-names = "virt_24000000_ck"; 205*724ba675SRob Herring clock-frequency = <24000000>; 206*724ba675SRob Herring }; 207*724ba675SRob Herring 208*724ba675SRob Herring virt_25000000_ck: clock-virt-25000000 { 209*724ba675SRob Herring #clock-cells = <0>; 210*724ba675SRob Herring compatible = "fixed-clock"; 211*724ba675SRob Herring clock-output-names = "virt_25000000_ck"; 212*724ba675SRob Herring clock-frequency = <25000000>; 213*724ba675SRob Herring }; 214*724ba675SRob Herring 215*724ba675SRob Herring virt_26000000_ck: clock-virt-26000000 { 216*724ba675SRob Herring #clock-cells = <0>; 217*724ba675SRob Herring compatible = "fixed-clock"; 218*724ba675SRob Herring clock-output-names = "virt_26000000_ck"; 219*724ba675SRob Herring clock-frequency = <26000000>; 220*724ba675SRob Herring }; 221*724ba675SRob Herring 222*724ba675SRob Herring tclkin_ck: clock-tclkin { 223*724ba675SRob Herring #clock-cells = <0>; 224*724ba675SRob Herring compatible = "fixed-clock"; 225*724ba675SRob Herring clock-output-names = "tclkin_ck"; 226*724ba675SRob Herring clock-frequency = <26000000>; 227*724ba675SRob Herring }; 228*724ba675SRob Herring 229*724ba675SRob Herring dpll_core_ck: clock@2d20 { 230*724ba675SRob Herring #clock-cells = <0>; 231*724ba675SRob Herring compatible = "ti,am3-dpll-core-clock"; 232*724ba675SRob Herring clock-output-names = "dpll_core_ck"; 233*724ba675SRob Herring clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; 234*724ba675SRob Herring reg = <0x2d20>, <0x2d24>, <0x2d2c>, <0x2d48>, <0x2d4c>; 235*724ba675SRob Herring }; 236*724ba675SRob Herring 237*724ba675SRob Herring dpll_core_x2_ck: clock-dpll-core-x2 { 238*724ba675SRob Herring #clock-cells = <0>; 239*724ba675SRob Herring compatible = "ti,am3-dpll-x2-clock"; 240*724ba675SRob Herring clock-output-names = "dpll_core_x2_ck"; 241*724ba675SRob Herring clocks = <&dpll_core_ck>; 242*724ba675SRob Herring }; 243*724ba675SRob Herring 244*724ba675SRob Herring dpll_core_m4_ck: clock-dpll-core-m4-8@2d38 { 245*724ba675SRob Herring #clock-cells = <0>; 246*724ba675SRob Herring compatible = "ti,divider-clock"; 247*724ba675SRob Herring clock-output-names = "dpll_core_m4_ck"; 248*724ba675SRob Herring clocks = <&dpll_core_x2_ck>; 249*724ba675SRob Herring ti,max-div = <31>; 250*724ba675SRob Herring ti,autoidle-shift = <8>; 251*724ba675SRob Herring reg = <0x2d38>; 252*724ba675SRob Herring ti,index-starts-at-one; 253*724ba675SRob Herring ti,invert-autoidle-bit; 254*724ba675SRob Herring }; 255*724ba675SRob Herring 256*724ba675SRob Herring dpll_core_m5_ck: clock-dpll-core-m5-8@2d3c { 257*724ba675SRob Herring #clock-cells = <0>; 258*724ba675SRob Herring compatible = "ti,divider-clock"; 259*724ba675SRob Herring clock-output-names = "dpll_core_m5_ck"; 260*724ba675SRob Herring clocks = <&dpll_core_x2_ck>; 261*724ba675SRob Herring ti,max-div = <31>; 262*724ba675SRob Herring ti,autoidle-shift = <8>; 263*724ba675SRob Herring reg = <0x2d3c>; 264*724ba675SRob Herring ti,index-starts-at-one; 265*724ba675SRob Herring ti,invert-autoidle-bit; 266*724ba675SRob Herring }; 267*724ba675SRob Herring 268*724ba675SRob Herring dpll_core_m6_ck: clock-dpll-core-m6-8@2d40 { 269*724ba675SRob Herring #clock-cells = <0>; 270*724ba675SRob Herring compatible = "ti,divider-clock"; 271*724ba675SRob Herring clock-output-names = "dpll_core_m6_ck"; 272*724ba675SRob Herring clocks = <&dpll_core_x2_ck>; 273*724ba675SRob Herring ti,max-div = <31>; 274*724ba675SRob Herring ti,autoidle-shift = <8>; 275*724ba675SRob Herring reg = <0x2d40>; 276*724ba675SRob Herring ti,index-starts-at-one; 277*724ba675SRob Herring ti,invert-autoidle-bit; 278*724ba675SRob Herring }; 279*724ba675SRob Herring 280*724ba675SRob Herring dpll_mpu_ck: clock@2d60 { 281*724ba675SRob Herring #clock-cells = <0>; 282*724ba675SRob Herring compatible = "ti,am3-dpll-clock"; 283*724ba675SRob Herring clock-output-names = "dpll_mpu_ck"; 284*724ba675SRob Herring clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; 285*724ba675SRob Herring reg = <0x2d60>, <0x2d64>, <0x2d6c>, <0x2d88>, <0x2d8c>; 286*724ba675SRob Herring }; 287*724ba675SRob Herring 288*724ba675SRob Herring dpll_mpu_m2_ck: clock-dpll-mpu-m2-8@2d70 { 289*724ba675SRob Herring #clock-cells = <0>; 290*724ba675SRob Herring compatible = "ti,divider-clock"; 291*724ba675SRob Herring clock-output-names = "dpll_mpu_m2_ck"; 292*724ba675SRob Herring clocks = <&dpll_mpu_ck>; 293*724ba675SRob Herring ti,max-div = <31>; 294*724ba675SRob Herring ti,autoidle-shift = <8>; 295*724ba675SRob Herring reg = <0x2d70>; 296*724ba675SRob Herring ti,index-starts-at-one; 297*724ba675SRob Herring ti,invert-autoidle-bit; 298*724ba675SRob Herring }; 299*724ba675SRob Herring 300*724ba675SRob Herring mpu_periphclk: clock-mpu-periphclk { 301*724ba675SRob Herring #clock-cells = <0>; 302*724ba675SRob Herring compatible = "fixed-factor-clock"; 303*724ba675SRob Herring clock-output-names = "mpu_periphclk"; 304*724ba675SRob Herring clocks = <&dpll_mpu_m2_ck>; 305*724ba675SRob Herring clock-mult = <1>; 306*724ba675SRob Herring clock-div = <2>; 307*724ba675SRob Herring }; 308*724ba675SRob Herring 309*724ba675SRob Herring dpll_ddr_ck: clock@2da0 { 310*724ba675SRob Herring #clock-cells = <0>; 311*724ba675SRob Herring compatible = "ti,am3-dpll-clock"; 312*724ba675SRob Herring clock-output-names = "dpll_ddr_ck"; 313*724ba675SRob Herring clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; 314*724ba675SRob Herring reg = <0x2da0>, <0x2da4>, <0x2dac>, <0x2dc8>, <0x2dcc>; 315*724ba675SRob Herring }; 316*724ba675SRob Herring 317*724ba675SRob Herring dpll_ddr_m2_ck: clock-dpll-ddr-m2-8@2db0 { 318*724ba675SRob Herring #clock-cells = <0>; 319*724ba675SRob Herring compatible = "ti,divider-clock"; 320*724ba675SRob Herring clock-output-names = "dpll_ddr_m2_ck"; 321*724ba675SRob Herring clocks = <&dpll_ddr_ck>; 322*724ba675SRob Herring ti,max-div = <31>; 323*724ba675SRob Herring ti,autoidle-shift = <8>; 324*724ba675SRob Herring reg = <0x2db0>; 325*724ba675SRob Herring ti,index-starts-at-one; 326*724ba675SRob Herring ti,invert-autoidle-bit; 327*724ba675SRob Herring }; 328*724ba675SRob Herring 329*724ba675SRob Herring dpll_disp_ck: clock@2e20 { 330*724ba675SRob Herring #clock-cells = <0>; 331*724ba675SRob Herring compatible = "ti,am3-dpll-clock"; 332*724ba675SRob Herring clock-output-names = "dpll_disp_ck"; 333*724ba675SRob Herring clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; 334*724ba675SRob Herring reg = <0x2e20>, <0x2e24>, <0x2e2c>, <0x2e48>, <0x2e4c>; 335*724ba675SRob Herring }; 336*724ba675SRob Herring 337*724ba675SRob Herring dpll_disp_m2_ck: clock-dpll-disp-m2-8@2e30 { 338*724ba675SRob Herring #clock-cells = <0>; 339*724ba675SRob Herring compatible = "ti,divider-clock"; 340*724ba675SRob Herring clock-output-names = "dpll_disp_m2_ck"; 341*724ba675SRob Herring clocks = <&dpll_disp_ck>; 342*724ba675SRob Herring ti,max-div = <31>; 343*724ba675SRob Herring ti,autoidle-shift = <8>; 344*724ba675SRob Herring reg = <0x2e30>; 345*724ba675SRob Herring ti,index-starts-at-one; 346*724ba675SRob Herring ti,invert-autoidle-bit; 347*724ba675SRob Herring ti,set-rate-parent; 348*724ba675SRob Herring }; 349*724ba675SRob Herring 350*724ba675SRob Herring dpll_per_ck: clock@2de0 { 351*724ba675SRob Herring #clock-cells = <0>; 352*724ba675SRob Herring compatible = "ti,am3-dpll-j-type-clock"; 353*724ba675SRob Herring clock-output-names = "dpll_per_ck"; 354*724ba675SRob Herring clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; 355*724ba675SRob Herring reg = <0x2de0>, <0x2de4>, <0x2dec>, <0x2e08>, <0x2e0c>; 356*724ba675SRob Herring }; 357*724ba675SRob Herring 358*724ba675SRob Herring dpll_per_m2_ck: clock-dpll-per-m2-8@2df0 { 359*724ba675SRob Herring #clock-cells = <0>; 360*724ba675SRob Herring compatible = "ti,divider-clock"; 361*724ba675SRob Herring clock-output-names = "dpll_per_m2_ck"; 362*724ba675SRob Herring clocks = <&dpll_per_ck>; 363*724ba675SRob Herring ti,max-div = <127>; 364*724ba675SRob Herring ti,autoidle-shift = <8>; 365*724ba675SRob Herring reg = <0x2df0>; 366*724ba675SRob Herring ti,index-starts-at-one; 367*724ba675SRob Herring ti,invert-autoidle-bit; 368*724ba675SRob Herring }; 369*724ba675SRob Herring 370*724ba675SRob Herring dpll_per_m2_div4_wkupdm_ck: clock-dpll-per-m2-div4-wkupdm { 371*724ba675SRob Herring #clock-cells = <0>; 372*724ba675SRob Herring compatible = "fixed-factor-clock"; 373*724ba675SRob Herring clock-output-names = "dpll_per_m2_div4_wkupdm_ck"; 374*724ba675SRob Herring clocks = <&dpll_per_m2_ck>; 375*724ba675SRob Herring clock-mult = <1>; 376*724ba675SRob Herring clock-div = <4>; 377*724ba675SRob Herring }; 378*724ba675SRob Herring 379*724ba675SRob Herring dpll_per_m2_div4_ck: clock-dpll-per-m2-div4 { 380*724ba675SRob Herring #clock-cells = <0>; 381*724ba675SRob Herring compatible = "fixed-factor-clock"; 382*724ba675SRob Herring clock-output-names = "dpll_per_m2_div4_ck"; 383*724ba675SRob Herring clocks = <&dpll_per_m2_ck>; 384*724ba675SRob Herring clock-mult = <1>; 385*724ba675SRob Herring clock-div = <4>; 386*724ba675SRob Herring }; 387*724ba675SRob Herring 388*724ba675SRob Herring clk_24mhz: clock-clk-24mhz { 389*724ba675SRob Herring #clock-cells = <0>; 390*724ba675SRob Herring compatible = "fixed-factor-clock"; 391*724ba675SRob Herring clock-output-names = "clk_24mhz"; 392*724ba675SRob Herring clocks = <&dpll_per_m2_ck>; 393*724ba675SRob Herring clock-mult = <1>; 394*724ba675SRob Herring clock-div = <8>; 395*724ba675SRob Herring }; 396*724ba675SRob Herring 397*724ba675SRob Herring clkdiv32k_ck: clock-clkdiv32k { 398*724ba675SRob Herring #clock-cells = <0>; 399*724ba675SRob Herring compatible = "fixed-factor-clock"; 400*724ba675SRob Herring clock-output-names = "clkdiv32k_ck"; 401*724ba675SRob Herring clocks = <&clk_24mhz>; 402*724ba675SRob Herring clock-mult = <1>; 403*724ba675SRob Herring clock-div = <732>; 404*724ba675SRob Herring }; 405*724ba675SRob Herring 406*724ba675SRob Herring clkdiv32k_ick: clock-clkdiv32k-ick-8@2a38 { 407*724ba675SRob Herring #clock-cells = <0>; 408*724ba675SRob Herring compatible = "ti,gate-clock"; 409*724ba675SRob Herring clock-output-names = "clkdiv32k_ick"; 410*724ba675SRob Herring clocks = <&clkdiv32k_ck>; 411*724ba675SRob Herring ti,bit-shift = <8>; 412*724ba675SRob Herring reg = <0x2a38>; 413*724ba675SRob Herring }; 414*724ba675SRob Herring 415*724ba675SRob Herring sysclk_div: clock-sysclk-div { 416*724ba675SRob Herring #clock-cells = <0>; 417*724ba675SRob Herring compatible = "fixed-factor-clock"; 418*724ba675SRob Herring clock-output-names = "sysclk_div"; 419*724ba675SRob Herring clocks = <&dpll_core_m4_ck>; 420*724ba675SRob Herring clock-mult = <1>; 421*724ba675SRob Herring clock-div = <1>; 422*724ba675SRob Herring }; 423*724ba675SRob Herring 424*724ba675SRob Herring pruss_ocp_gclk: clock-pruss-ocp-gclk@4248 { 425*724ba675SRob Herring #clock-cells = <0>; 426*724ba675SRob Herring compatible = "ti,mux-clock"; 427*724ba675SRob Herring clock-output-names = "pruss_ocp_gclk"; 428*724ba675SRob Herring clocks = <&sysclk_div>, <&dpll_disp_m2_ck>; 429*724ba675SRob Herring reg = <0x4248>; 430*724ba675SRob Herring }; 431*724ba675SRob Herring 432*724ba675SRob Herring clk_32k_tpm_ck: clock-clk-32k-tpm { 433*724ba675SRob Herring #clock-cells = <0>; 434*724ba675SRob Herring compatible = "fixed-clock"; 435*724ba675SRob Herring clock-output-names = "clk_32k_tpm_ck"; 436*724ba675SRob Herring clock-frequency = <32768>; 437*724ba675SRob Herring }; 438*724ba675SRob Herring 439*724ba675SRob Herring timer1_fck: clock-timer1-fck@4200 { 440*724ba675SRob Herring #clock-cells = <0>; 441*724ba675SRob Herring compatible = "ti,mux-clock"; 442*724ba675SRob Herring clock-output-names = "timer1_fck"; 443*724ba675SRob Herring clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_32k_tpm_ck>; 444*724ba675SRob Herring reg = <0x4200>; 445*724ba675SRob Herring }; 446*724ba675SRob Herring 447*724ba675SRob Herring timer2_fck: clock-timer2-fck@4204 { 448*724ba675SRob Herring #clock-cells = <0>; 449*724ba675SRob Herring compatible = "ti,mux-clock"; 450*724ba675SRob Herring clock-output-names = "timer2_fck"; 451*724ba675SRob Herring clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; 452*724ba675SRob Herring reg = <0x4204>; 453*724ba675SRob Herring }; 454*724ba675SRob Herring 455*724ba675SRob Herring timer3_fck: clock-timer3-fck@4208 { 456*724ba675SRob Herring #clock-cells = <0>; 457*724ba675SRob Herring compatible = "ti,mux-clock"; 458*724ba675SRob Herring clock-output-names = "timer3_fck"; 459*724ba675SRob Herring clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; 460*724ba675SRob Herring reg = <0x4208>; 461*724ba675SRob Herring }; 462*724ba675SRob Herring 463*724ba675SRob Herring timer4_fck: clock-timer4-fck@420c { 464*724ba675SRob Herring #clock-cells = <0>; 465*724ba675SRob Herring compatible = "ti,mux-clock"; 466*724ba675SRob Herring clock-output-names = "timer4_fck"; 467*724ba675SRob Herring clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; 468*724ba675SRob Herring reg = <0x420c>; 469*724ba675SRob Herring }; 470*724ba675SRob Herring 471*724ba675SRob Herring timer5_fck: clock-timer5-fck@4210 { 472*724ba675SRob Herring #clock-cells = <0>; 473*724ba675SRob Herring compatible = "ti,mux-clock"; 474*724ba675SRob Herring clock-output-names = "timer5_fck"; 475*724ba675SRob Herring clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; 476*724ba675SRob Herring reg = <0x4210>; 477*724ba675SRob Herring }; 478*724ba675SRob Herring 479*724ba675SRob Herring timer6_fck: clock-timer6-fck@4214 { 480*724ba675SRob Herring #clock-cells = <0>; 481*724ba675SRob Herring compatible = "ti,mux-clock"; 482*724ba675SRob Herring clock-output-names = "timer6_fck"; 483*724ba675SRob Herring clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; 484*724ba675SRob Herring reg = <0x4214>; 485*724ba675SRob Herring }; 486*724ba675SRob Herring 487*724ba675SRob Herring timer7_fck: clock-timer7-fck@4218 { 488*724ba675SRob Herring #clock-cells = <0>; 489*724ba675SRob Herring compatible = "ti,mux-clock"; 490*724ba675SRob Herring clock-output-names = "timer7_fck"; 491*724ba675SRob Herring clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; 492*724ba675SRob Herring reg = <0x4218>; 493*724ba675SRob Herring }; 494*724ba675SRob Herring 495*724ba675SRob Herring wdt1_fck: clock-wdt1-fck@422c { 496*724ba675SRob Herring #clock-cells = <0>; 497*724ba675SRob Herring compatible = "ti,mux-clock"; 498*724ba675SRob Herring clock-output-names = "wdt1_fck"; 499*724ba675SRob Herring clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>; 500*724ba675SRob Herring reg = <0x422c>; 501*724ba675SRob Herring }; 502*724ba675SRob Herring 503*724ba675SRob Herring adc_mag_fck: adc_mag_fck@424c { 504*724ba675SRob Herring #clock-cells = <0>; 505*724ba675SRob Herring compatible = "ti,mux-clock"; 506*724ba675SRob Herring clocks = <&sys_clkin_ck>, <&dpll_per_m2_ck>; 507*724ba675SRob Herring reg = <0x424c>; 508*724ba675SRob Herring }; 509*724ba675SRob Herring 510*724ba675SRob Herring l3_gclk: clock-l3-gclk { 511*724ba675SRob Herring #clock-cells = <0>; 512*724ba675SRob Herring compatible = "fixed-factor-clock"; 513*724ba675SRob Herring clock-output-names = "l3_gclk"; 514*724ba675SRob Herring clocks = <&dpll_core_m4_ck>; 515*724ba675SRob Herring clock-mult = <1>; 516*724ba675SRob Herring clock-div = <1>; 517*724ba675SRob Herring }; 518*724ba675SRob Herring 519*724ba675SRob Herring dpll_core_m4_div2_ck: clock-dpll-core-m4-div2 { 520*724ba675SRob Herring #clock-cells = <0>; 521*724ba675SRob Herring compatible = "fixed-factor-clock"; 522*724ba675SRob Herring clock-output-names = "dpll_core_m4_div2_ck"; 523*724ba675SRob Herring clocks = <&sysclk_div>; 524*724ba675SRob Herring clock-mult = <1>; 525*724ba675SRob Herring clock-div = <2>; 526*724ba675SRob Herring }; 527*724ba675SRob Herring 528*724ba675SRob Herring l4hs_gclk: clock-l4hs-gclk { 529*724ba675SRob Herring #clock-cells = <0>; 530*724ba675SRob Herring compatible = "fixed-factor-clock"; 531*724ba675SRob Herring clock-output-names = "l4hs_gclk"; 532*724ba675SRob Herring clocks = <&dpll_core_m4_ck>; 533*724ba675SRob Herring clock-mult = <1>; 534*724ba675SRob Herring clock-div = <1>; 535*724ba675SRob Herring }; 536*724ba675SRob Herring 537*724ba675SRob Herring l3s_gclk: clock-l3s-gclk { 538*724ba675SRob Herring #clock-cells = <0>; 539*724ba675SRob Herring compatible = "fixed-factor-clock"; 540*724ba675SRob Herring clock-output-names = "l3s_gclk"; 541*724ba675SRob Herring clocks = <&dpll_core_m4_div2_ck>; 542*724ba675SRob Herring clock-mult = <1>; 543*724ba675SRob Herring clock-div = <1>; 544*724ba675SRob Herring }; 545*724ba675SRob Herring 546*724ba675SRob Herring l4ls_gclk: clock-l4ls-gclk { 547*724ba675SRob Herring #clock-cells = <0>; 548*724ba675SRob Herring compatible = "fixed-factor-clock"; 549*724ba675SRob Herring clock-output-names = "l4ls_gclk"; 550*724ba675SRob Herring clocks = <&dpll_core_m4_div2_ck>; 551*724ba675SRob Herring clock-mult = <1>; 552*724ba675SRob Herring clock-div = <1>; 553*724ba675SRob Herring }; 554*724ba675SRob Herring 555*724ba675SRob Herring cpsw_125mhz_gclk: clock-cpsw-125mhz-gclk { 556*724ba675SRob Herring #clock-cells = <0>; 557*724ba675SRob Herring compatible = "fixed-factor-clock"; 558*724ba675SRob Herring clock-output-names = "cpsw_125mhz_gclk"; 559*724ba675SRob Herring clocks = <&dpll_core_m5_ck>; 560*724ba675SRob Herring clock-mult = <1>; 561*724ba675SRob Herring clock-div = <2>; 562*724ba675SRob Herring }; 563*724ba675SRob Herring 564*724ba675SRob Herring cpsw_cpts_rft_clk: clock-cpsw-cpts-rft@4238 { 565*724ba675SRob Herring #clock-cells = <0>; 566*724ba675SRob Herring compatible = "ti,mux-clock"; 567*724ba675SRob Herring clock-output-names = "cpsw_cpts_rft_clk"; 568*724ba675SRob Herring clocks = <&sysclk_div>, <&dpll_core_m5_ck>, <&dpll_disp_m2_ck>; 569*724ba675SRob Herring reg = <0x4238>; 570*724ba675SRob Herring }; 571*724ba675SRob Herring 572*724ba675SRob Herring dpll_clksel_mac_clk: clock-dpll-clksel-mac-2@4234 { 573*724ba675SRob Herring #clock-cells = <0>; 574*724ba675SRob Herring compatible = "ti,divider-clock"; 575*724ba675SRob Herring clock-output-names = "dpll_clksel_mac_clk"; 576*724ba675SRob Herring clocks = <&dpll_core_m5_ck>; 577*724ba675SRob Herring reg = <0x4234>; 578*724ba675SRob Herring ti,bit-shift = <2>; 579*724ba675SRob Herring ti,dividers = <2>, <5>; 580*724ba675SRob Herring }; 581*724ba675SRob Herring 582*724ba675SRob Herring clk_32k_mosc_ck: clock-clk-32k-mosc { 583*724ba675SRob Herring #clock-cells = <0>; 584*724ba675SRob Herring compatible = "fixed-clock"; 585*724ba675SRob Herring clock-output-names = "clk_32k_mosc_ck"; 586*724ba675SRob Herring clock-frequency = <32768>; 587*724ba675SRob Herring }; 588*724ba675SRob Herring 589*724ba675SRob Herring gpio0_dbclk_mux_ck: clock-gpio0-dbclk-mux@4240 { 590*724ba675SRob Herring #clock-cells = <0>; 591*724ba675SRob Herring compatible = "ti,mux-clock"; 592*724ba675SRob Herring clock-output-names = "gpio0_dbclk_mux_ck"; 593*724ba675SRob Herring clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>, <&clk_32k_mosc_ck>, <&clk_32k_tpm_ck>; 594*724ba675SRob Herring reg = <0x4240>; 595*724ba675SRob Herring }; 596*724ba675SRob Herring 597*724ba675SRob Herring mmc_clk: clock-mmc { 598*724ba675SRob Herring #clock-cells = <0>; 599*724ba675SRob Herring compatible = "fixed-factor-clock"; 600*724ba675SRob Herring clock-output-names = "mmc_clk"; 601*724ba675SRob Herring clocks = <&dpll_per_m2_ck>; 602*724ba675SRob Herring clock-mult = <1>; 603*724ba675SRob Herring clock-div = <2>; 604*724ba675SRob Herring }; 605*724ba675SRob Herring 606*724ba675SRob Herring gfx_fclk_clksel_ck: clock-gfx-fclk-clksel-1@423c { 607*724ba675SRob Herring #clock-cells = <0>; 608*724ba675SRob Herring compatible = "ti,mux-clock"; 609*724ba675SRob Herring clock-output-names = "gfx_fclk_clksel_ck"; 610*724ba675SRob Herring clocks = <&sysclk_div>, <&dpll_per_m2_ck>; 611*724ba675SRob Herring ti,bit-shift = <1>; 612*724ba675SRob Herring reg = <0x423c>; 613*724ba675SRob Herring }; 614*724ba675SRob Herring 615*724ba675SRob Herring gfx_fck_div_ck: clock-gfx-fck-div@423c { 616*724ba675SRob Herring #clock-cells = <0>; 617*724ba675SRob Herring compatible = "ti,divider-clock"; 618*724ba675SRob Herring clock-output-names = "gfx_fck_div_ck"; 619*724ba675SRob Herring clocks = <&gfx_fclk_clksel_ck>; 620*724ba675SRob Herring reg = <0x423c>; 621*724ba675SRob Herring ti,max-div = <2>; 622*724ba675SRob Herring }; 623*724ba675SRob Herring 624*724ba675SRob Herring disp_clk: clock-disp@4244 { 625*724ba675SRob Herring #clock-cells = <0>; 626*724ba675SRob Herring compatible = "ti,mux-clock"; 627*724ba675SRob Herring clock-output-names = "disp_clk"; 628*724ba675SRob Herring clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>; 629*724ba675SRob Herring reg = <0x4244>; 630*724ba675SRob Herring ti,set-rate-parent; 631*724ba675SRob Herring }; 632*724ba675SRob Herring 633*724ba675SRob Herring dpll_extdev_ck: clock@2e60 { 634*724ba675SRob Herring #clock-cells = <0>; 635*724ba675SRob Herring compatible = "ti,am3-dpll-clock"; 636*724ba675SRob Herring clock-output-names = "dpll_extdev_ck"; 637*724ba675SRob Herring clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; 638*724ba675SRob Herring reg = <0x2e60>, <0x2e64>, <0x2e6c>, <0x2e88>, <0x2e8c>; 639*724ba675SRob Herring }; 640*724ba675SRob Herring 641*724ba675SRob Herring dpll_extdev_m2_ck: clock-dpll-extdev-m2-8@2e70 { 642*724ba675SRob Herring #clock-cells = <0>; 643*724ba675SRob Herring compatible = "ti,divider-clock"; 644*724ba675SRob Herring clock-output-names = "dpll_extdev_m2_ck"; 645*724ba675SRob Herring clocks = <&dpll_extdev_ck>; 646*724ba675SRob Herring ti,max-div = <127>; 647*724ba675SRob Herring ti,autoidle-shift = <8>; 648*724ba675SRob Herring reg = <0x2e70>; 649*724ba675SRob Herring ti,index-starts-at-one; 650*724ba675SRob Herring ti,invert-autoidle-bit; 651*724ba675SRob Herring }; 652*724ba675SRob Herring 653*724ba675SRob Herring mux_synctimer32k_ck: clock-mux-synctimer32k@4230 { 654*724ba675SRob Herring #clock-cells = <0>; 655*724ba675SRob Herring compatible = "ti,mux-clock"; 656*724ba675SRob Herring clock-output-names = "mux_synctimer32k_ck"; 657*724ba675SRob Herring clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>, <&clkdiv32k_ick>; 658*724ba675SRob Herring reg = <0x4230>; 659*724ba675SRob Herring }; 660*724ba675SRob Herring 661*724ba675SRob Herring timer8_fck: clock-timer8-fck@421c { 662*724ba675SRob Herring #clock-cells = <0>; 663*724ba675SRob Herring compatible = "ti,mux-clock"; 664*724ba675SRob Herring clock-output-names = "timer8_fck"; 665*724ba675SRob Herring clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; 666*724ba675SRob Herring reg = <0x421c>; 667*724ba675SRob Herring }; 668*724ba675SRob Herring 669*724ba675SRob Herring timer9_fck: clock-timer9-fck@4220 { 670*724ba675SRob Herring #clock-cells = <0>; 671*724ba675SRob Herring compatible = "ti,mux-clock"; 672*724ba675SRob Herring clock-output-names = "timer9_fck"; 673*724ba675SRob Herring clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; 674*724ba675SRob Herring reg = <0x4220>; 675*724ba675SRob Herring }; 676*724ba675SRob Herring 677*724ba675SRob Herring timer10_fck: clock-timer10-fck@4224 { 678*724ba675SRob Herring #clock-cells = <0>; 679*724ba675SRob Herring compatible = "ti,mux-clock"; 680*724ba675SRob Herring clock-output-names = "timer10_fck"; 681*724ba675SRob Herring clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; 682*724ba675SRob Herring reg = <0x4224>; 683*724ba675SRob Herring }; 684*724ba675SRob Herring 685*724ba675SRob Herring timer11_fck: clock-timer11-fck@4228 { 686*724ba675SRob Herring #clock-cells = <0>; 687*724ba675SRob Herring compatible = "ti,mux-clock"; 688*724ba675SRob Herring clock-output-names = "timer11_fck"; 689*724ba675SRob Herring clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; 690*724ba675SRob Herring reg = <0x4228>; 691*724ba675SRob Herring }; 692*724ba675SRob Herring 693*724ba675SRob Herring cpsw_50m_clkdiv: clock-cpsw-50m-clkdiv { 694*724ba675SRob Herring #clock-cells = <0>; 695*724ba675SRob Herring compatible = "fixed-factor-clock"; 696*724ba675SRob Herring clock-output-names = "cpsw_50m_clkdiv"; 697*724ba675SRob Herring clocks = <&dpll_core_m5_ck>; 698*724ba675SRob Herring clock-mult = <1>; 699*724ba675SRob Herring clock-div = <1>; 700*724ba675SRob Herring }; 701*724ba675SRob Herring 702*724ba675SRob Herring cpsw_5m_clkdiv: clock-cpsw-5m-clkdiv { 703*724ba675SRob Herring #clock-cells = <0>; 704*724ba675SRob Herring compatible = "fixed-factor-clock"; 705*724ba675SRob Herring clock-output-names = "cpsw_5m_clkdiv"; 706*724ba675SRob Herring clocks = <&cpsw_50m_clkdiv>; 707*724ba675SRob Herring clock-mult = <1>; 708*724ba675SRob Herring clock-div = <10>; 709*724ba675SRob Herring }; 710*724ba675SRob Herring 711*724ba675SRob Herring dpll_ddr_x2_ck: clock-dpll-ddr-x2 { 712*724ba675SRob Herring #clock-cells = <0>; 713*724ba675SRob Herring compatible = "ti,am3-dpll-x2-clock"; 714*724ba675SRob Herring clock-output-names = "dpll_ddr_x2_ck"; 715*724ba675SRob Herring clocks = <&dpll_ddr_ck>; 716*724ba675SRob Herring }; 717*724ba675SRob Herring 718*724ba675SRob Herring dpll_ddr_m4_ck: clock-dpll-ddr-m4-8@2db8 { 719*724ba675SRob Herring #clock-cells = <0>; 720*724ba675SRob Herring compatible = "ti,divider-clock"; 721*724ba675SRob Herring clock-output-names = "dpll_ddr_m4_ck"; 722*724ba675SRob Herring clocks = <&dpll_ddr_x2_ck>; 723*724ba675SRob Herring ti,max-div = <31>; 724*724ba675SRob Herring ti,autoidle-shift = <8>; 725*724ba675SRob Herring reg = <0x2db8>; 726*724ba675SRob Herring ti,index-starts-at-one; 727*724ba675SRob Herring ti,invert-autoidle-bit; 728*724ba675SRob Herring }; 729*724ba675SRob Herring 730*724ba675SRob Herring dpll_per_clkdcoldo: clock-dpll-per-clkdcoldo-8@2e14 { 731*724ba675SRob Herring #clock-cells = <0>; 732*724ba675SRob Herring compatible = "ti,fixed-factor-clock"; 733*724ba675SRob Herring clock-output-names = "dpll_per_clkdcoldo"; 734*724ba675SRob Herring clocks = <&dpll_per_ck>; 735*724ba675SRob Herring ti,clock-mult = <1>; 736*724ba675SRob Herring ti,clock-div = <1>; 737*724ba675SRob Herring ti,autoidle-shift = <8>; 738*724ba675SRob Herring reg = <0x2e14>; 739*724ba675SRob Herring ti,invert-autoidle-bit; 740*724ba675SRob Herring }; 741*724ba675SRob Herring 742*724ba675SRob Herring dll_aging_clk_div: clock-dll-aging-clk-div@4250 { 743*724ba675SRob Herring #clock-cells = <0>; 744*724ba675SRob Herring compatible = "ti,divider-clock"; 745*724ba675SRob Herring clock-output-names = "dll_aging_clk_div"; 746*724ba675SRob Herring clocks = <&sys_clkin_ck>; 747*724ba675SRob Herring reg = <0x4250>; 748*724ba675SRob Herring ti,dividers = <8>, <16>, <32>; 749*724ba675SRob Herring }; 750*724ba675SRob Herring 751*724ba675SRob Herring div_core_25m_ck: clock-div-core-25m { 752*724ba675SRob Herring #clock-cells = <0>; 753*724ba675SRob Herring compatible = "fixed-factor-clock"; 754*724ba675SRob Herring clock-output-names = "div_core_25m_ck"; 755*724ba675SRob Herring clocks = <&sysclk_div>; 756*724ba675SRob Herring clock-mult = <1>; 757*724ba675SRob Herring clock-div = <8>; 758*724ba675SRob Herring }; 759*724ba675SRob Herring 760*724ba675SRob Herring func_12m_clk: clock-func-12m { 761*724ba675SRob Herring #clock-cells = <0>; 762*724ba675SRob Herring compatible = "fixed-factor-clock"; 763*724ba675SRob Herring clock-output-names = "func_12m_clk"; 764*724ba675SRob Herring clocks = <&dpll_per_m2_ck>; 765*724ba675SRob Herring clock-mult = <1>; 766*724ba675SRob Herring clock-div = <16>; 767*724ba675SRob Herring }; 768*724ba675SRob Herring 769*724ba675SRob Herring vtp_clk_div: clock-vtp-clk-div { 770*724ba675SRob Herring #clock-cells = <0>; 771*724ba675SRob Herring compatible = "fixed-factor-clock"; 772*724ba675SRob Herring clock-output-names = "vtp_clk_div"; 773*724ba675SRob Herring clocks = <&sys_clkin_ck>; 774*724ba675SRob Herring clock-mult = <1>; 775*724ba675SRob Herring clock-div = <2>; 776*724ba675SRob Herring }; 777*724ba675SRob Herring 778*724ba675SRob Herring usbphy_32khz_clkmux: clock-usbphy-32khz-clkmux@4260 { 779*724ba675SRob Herring #clock-cells = <0>; 780*724ba675SRob Herring compatible = "ti,mux-clock"; 781*724ba675SRob Herring clock-output-names = "usbphy_32khz_clkmux"; 782*724ba675SRob Herring clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>; 783*724ba675SRob Herring reg = <0x4260>; 784*724ba675SRob Herring }; 785*724ba675SRob Herring 786*724ba675SRob Herring usb_phy0_always_on_clk32k: clock-usb-phy0-always-on-clk32k-8@2a40 { 787*724ba675SRob Herring #clock-cells = <0>; 788*724ba675SRob Herring compatible = "ti,gate-clock"; 789*724ba675SRob Herring clock-output-names = "usb_phy0_always_on_clk32k"; 790*724ba675SRob Herring clocks = <&usbphy_32khz_clkmux>; 791*724ba675SRob Herring ti,bit-shift = <8>; 792*724ba675SRob Herring reg = <0x2a40>; 793*724ba675SRob Herring }; 794*724ba675SRob Herring 795*724ba675SRob Herring usb_phy1_always_on_clk32k: clock-usb-phy1-always-on-clk32k-8@2a48 { 796*724ba675SRob Herring #clock-cells = <0>; 797*724ba675SRob Herring compatible = "ti,gate-clock"; 798*724ba675SRob Herring clock-output-names = "usb_phy1_always_on_clk32k"; 799*724ba675SRob Herring clocks = <&usbphy_32khz_clkmux>; 800*724ba675SRob Herring ti,bit-shift = <8>; 801*724ba675SRob Herring reg = <0x2a48>; 802*724ba675SRob Herring }; 803*724ba675SRob Herring 804*724ba675SRob Herring clkout1_osc_div_ck: clock-clkout1-osc-div-ck { 805*724ba675SRob Herring #clock-cells = <0>; 806*724ba675SRob Herring compatible = "ti,divider-clock"; 807*724ba675SRob Herring clock-output-names = "clkout1_osc_div_ck"; 808*724ba675SRob Herring clocks = <&sys_clkin_ck>; 809*724ba675SRob Herring ti,bit-shift = <20>; 810*724ba675SRob Herring ti,max-div = <4>; 811*724ba675SRob Herring reg = <0x4100>; 812*724ba675SRob Herring }; 813*724ba675SRob Herring 814*724ba675SRob Herring clkout1_src2_mux_ck: clock-clkout1-src2-mux-ck { 815*724ba675SRob Herring #clock-cells = <0>; 816*724ba675SRob Herring compatible = "ti,mux-clock"; 817*724ba675SRob Herring clock-output-names = "clkout1_src2_mux_ck"; 818*724ba675SRob Herring clocks = <&clk_rc32k_ck>, <&sysclk_div>, <&dpll_ddr_m2_ck>, 819*724ba675SRob Herring <&dpll_per_m2_ck>, <&dpll_disp_m2_ck>, 820*724ba675SRob Herring <&dpll_mpu_m2_ck>; 821*724ba675SRob Herring reg = <0x4100>; 822*724ba675SRob Herring }; 823*724ba675SRob Herring 824*724ba675SRob Herring clkout1_src2_pre_div_ck: clock-clkout1-src2-pre-div-ck { 825*724ba675SRob Herring #clock-cells = <0>; 826*724ba675SRob Herring compatible = "ti,divider-clock"; 827*724ba675SRob Herring clock-output-names = "clkout1_src2_pre_div_ck"; 828*724ba675SRob Herring clocks = <&clkout1_src2_mux_ck>; 829*724ba675SRob Herring ti,bit-shift = <4>; 830*724ba675SRob Herring ti,max-div = <8>; 831*724ba675SRob Herring reg = <0x4100>; 832*724ba675SRob Herring }; 833*724ba675SRob Herring 834*724ba675SRob Herring clkout1_src2_post_div_ck: clock-clkout1-src2-post-div-ck { 835*724ba675SRob Herring #clock-cells = <0>; 836*724ba675SRob Herring compatible = "ti,divider-clock"; 837*724ba675SRob Herring clock-output-names = "clkout1_src2_post_div_ck"; 838*724ba675SRob Herring clocks = <&clkout1_src2_pre_div_ck>; 839*724ba675SRob Herring ti,bit-shift = <8>; 840*724ba675SRob Herring ti,max-div = <32>; 841*724ba675SRob Herring ti,index-power-of-two; 842*724ba675SRob Herring reg = <0x4100>; 843*724ba675SRob Herring }; 844*724ba675SRob Herring 845*724ba675SRob Herring clkout1_mux_ck: clock-clkout1-mux-ck { 846*724ba675SRob Herring #clock-cells = <0>; 847*724ba675SRob Herring compatible = "ti,mux-clock"; 848*724ba675SRob Herring clock-output-names = "clkout1_mux_ck"; 849*724ba675SRob Herring clocks = <&clkout1_osc_div_ck>, <&clk_rc32k_ck>, 850*724ba675SRob Herring <&clkout1_src2_post_div_ck>, <&dpll_extdev_m2_ck>; 851*724ba675SRob Herring ti,bit-shift = <16>; 852*724ba675SRob Herring reg = <0x4100>; 853*724ba675SRob Herring }; 854*724ba675SRob Herring 855*724ba675SRob Herring clkout1_ck: clock-clkout1-ck { 856*724ba675SRob Herring #clock-cells = <0>; 857*724ba675SRob Herring compatible = "ti,gate-clock"; 858*724ba675SRob Herring clock-output-names = "clkout1_ck"; 859*724ba675SRob Herring clocks = <&clkout1_mux_ck>; 860*724ba675SRob Herring ti,bit-shift = <23>; 861*724ba675SRob Herring reg = <0x4100>; 862*724ba675SRob Herring }; 863*724ba675SRob Herring}; 864*724ba675SRob Herring 865*724ba675SRob Herring&prcm { 866*724ba675SRob Herring wkup_cm: clock@2800 { 867*724ba675SRob Herring compatible = "ti,omap4-cm"; 868*724ba675SRob Herring clock-output-names = "wkup_cm"; 869*724ba675SRob Herring reg = <0x2800 0x400>; 870*724ba675SRob Herring #address-cells = <1>; 871*724ba675SRob Herring #size-cells = <1>; 872*724ba675SRob Herring ranges = <0 0x2800 0x400>; 873*724ba675SRob Herring 874*724ba675SRob Herring l3s_tsc_clkctrl: clock@120 { 875*724ba675SRob Herring compatible = "ti,clkctrl"; 876*724ba675SRob Herring clock-output-names = "l3s_tsc_clkctrl"; 877*724ba675SRob Herring reg = <0x120 0x4>; 878*724ba675SRob Herring #clock-cells = <2>; 879*724ba675SRob Herring }; 880*724ba675SRob Herring 881*724ba675SRob Herring l4_wkup_aon_clkctrl: clock@228 { 882*724ba675SRob Herring compatible = "ti,clkctrl"; 883*724ba675SRob Herring clock-output-names = "l4_wkup_aon_clkctrl"; 884*724ba675SRob Herring reg = <0x228 0xc>; 885*724ba675SRob Herring #clock-cells = <2>; 886*724ba675SRob Herring }; 887*724ba675SRob Herring 888*724ba675SRob Herring l4_wkup_clkctrl: clock@220 { 889*724ba675SRob Herring compatible = "ti,clkctrl"; 890*724ba675SRob Herring clock-output-names = "l4_wkup_clkctrl"; 891*724ba675SRob Herring reg = <0x220 0x4>, <0x328 0x44>; 892*724ba675SRob Herring #clock-cells = <2>; 893*724ba675SRob Herring }; 894*724ba675SRob Herring 895*724ba675SRob Herring }; 896*724ba675SRob Herring 897*724ba675SRob Herring mpu_cm: clock@8300 { 898*724ba675SRob Herring compatible = "ti,omap4-cm"; 899*724ba675SRob Herring clock-output-names = "mpu_cm"; 900*724ba675SRob Herring reg = <0x8300 0x100>; 901*724ba675SRob Herring #address-cells = <1>; 902*724ba675SRob Herring #size-cells = <1>; 903*724ba675SRob Herring ranges = <0 0x8300 0x100>; 904*724ba675SRob Herring 905*724ba675SRob Herring mpu_clkctrl: clock@20 { 906*724ba675SRob Herring compatible = "ti,clkctrl"; 907*724ba675SRob Herring clock-output-names = "mpu_clkctrl"; 908*724ba675SRob Herring reg = <0x20 0x4>; 909*724ba675SRob Herring #clock-cells = <2>; 910*724ba675SRob Herring }; 911*724ba675SRob Herring }; 912*724ba675SRob Herring 913*724ba675SRob Herring gfx_l3_cm: clock@8400 { 914*724ba675SRob Herring compatible = "ti,omap4-cm"; 915*724ba675SRob Herring clock-output-names = "gfx_l3_cm"; 916*724ba675SRob Herring reg = <0x8400 0x100>; 917*724ba675SRob Herring #address-cells = <1>; 918*724ba675SRob Herring #size-cells = <1>; 919*724ba675SRob Herring ranges = <0 0x8400 0x100>; 920*724ba675SRob Herring 921*724ba675SRob Herring gfx_l3_clkctrl: clock@20 { 922*724ba675SRob Herring compatible = "ti,clkctrl"; 923*724ba675SRob Herring clock-output-names = "gfx_l3_clkctrl"; 924*724ba675SRob Herring reg = <0x20 0x4>; 925*724ba675SRob Herring #clock-cells = <2>; 926*724ba675SRob Herring }; 927*724ba675SRob Herring }; 928*724ba675SRob Herring 929*724ba675SRob Herring l4_rtc_cm: clock@8500 { 930*724ba675SRob Herring compatible = "ti,omap4-cm"; 931*724ba675SRob Herring clock-output-names = "l4_rtc_cm"; 932*724ba675SRob Herring reg = <0x8500 0x100>; 933*724ba675SRob Herring #address-cells = <1>; 934*724ba675SRob Herring #size-cells = <1>; 935*724ba675SRob Herring ranges = <0 0x8500 0x100>; 936*724ba675SRob Herring 937*724ba675SRob Herring l4_rtc_clkctrl: clock@20 { 938*724ba675SRob Herring compatible = "ti,clkctrl"; 939*724ba675SRob Herring clock-output-names = "l4_rtc_clkctrl"; 940*724ba675SRob Herring reg = <0x20 0x4>; 941*724ba675SRob Herring #clock-cells = <2>; 942*724ba675SRob Herring }; 943*724ba675SRob Herring }; 944*724ba675SRob Herring 945*724ba675SRob Herring per_cm: clock@8800 { 946*724ba675SRob Herring compatible = "ti,omap4-cm"; 947*724ba675SRob Herring clock-output-names = "per_cm"; 948*724ba675SRob Herring reg = <0x8800 0xc00>; 949*724ba675SRob Herring #address-cells = <1>; 950*724ba675SRob Herring #size-cells = <1>; 951*724ba675SRob Herring ranges = <0 0x8800 0xc00>; 952*724ba675SRob Herring 953*724ba675SRob Herring l3_clkctrl: clock@20 { 954*724ba675SRob Herring compatible = "ti,clkctrl"; 955*724ba675SRob Herring clock-output-names = "l3_clkctrl"; 956*724ba675SRob Herring reg = <0x20 0x3c>, <0x78 0x2c>; 957*724ba675SRob Herring #clock-cells = <2>; 958*724ba675SRob Herring }; 959*724ba675SRob Herring 960*724ba675SRob Herring l3s_clkctrl: clock@68 { 961*724ba675SRob Herring compatible = "ti,clkctrl"; 962*724ba675SRob Herring clock-output-names = "l3s_clkctrl"; 963*724ba675SRob Herring reg = <0x68 0xc>, <0x220 0x4c>; 964*724ba675SRob Herring #clock-cells = <2>; 965*724ba675SRob Herring }; 966*724ba675SRob Herring 967*724ba675SRob Herring pruss_ocp_clkctrl: clock@320 { 968*724ba675SRob Herring compatible = "ti,clkctrl"; 969*724ba675SRob Herring clock-output-names = "pruss_ocp_clkctrl"; 970*724ba675SRob Herring reg = <0x320 0x4>; 971*724ba675SRob Herring #clock-cells = <2>; 972*724ba675SRob Herring }; 973*724ba675SRob Herring 974*724ba675SRob Herring l4ls_clkctrl: clock@420 { 975*724ba675SRob Herring compatible = "ti,clkctrl"; 976*724ba675SRob Herring clock-output-names = "l4ls_clkctrl"; 977*724ba675SRob Herring reg = <0x420 0x1a4>; 978*724ba675SRob Herring #clock-cells = <2>; 979*724ba675SRob Herring }; 980*724ba675SRob Herring 981*724ba675SRob Herring emif_clkctrl: clock@720 { 982*724ba675SRob Herring compatible = "ti,clkctrl"; 983*724ba675SRob Herring clock-output-names = "emif_clkctrl"; 984*724ba675SRob Herring reg = <0x720 0x4>; 985*724ba675SRob Herring #clock-cells = <2>; 986*724ba675SRob Herring }; 987*724ba675SRob Herring 988*724ba675SRob Herring dss_clkctrl: clock@a20 { 989*724ba675SRob Herring compatible = "ti,clkctrl"; 990*724ba675SRob Herring clock-output-names = "dss_clkctrl"; 991*724ba675SRob Herring reg = <0xa20 0x4>; 992*724ba675SRob Herring #clock-cells = <2>; 993*724ba675SRob Herring }; 994*724ba675SRob Herring 995*724ba675SRob Herring cpsw_125mhz_clkctrl: clock@b20 { 996*724ba675SRob Herring compatible = "ti,clkctrl"; 997*724ba675SRob Herring clock-output-names = "cpsw_125mhz_clkctrl"; 998*724ba675SRob Herring reg = <0xb20 0x4>; 999*724ba675SRob Herring #clock-cells = <2>; 1000*724ba675SRob Herring }; 1001*724ba675SRob Herring 1002*724ba675SRob Herring }; 1003*724ba675SRob Herring}; 1004