1724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0+ 2724ba675SRob Herring/* 3724ba675SRob Herring * Copyright (C) 2012 Altera <www.altera.com> 4724ba675SRob Herring */ 5724ba675SRob Herring 6724ba675SRob Herring#include <dt-bindings/reset/altr,rst-mgr.h> 7724ba675SRob Herring 8724ba675SRob Herring/ { 9724ba675SRob Herring #address-cells = <1>; 10724ba675SRob Herring #size-cells = <1>; 11724ba675SRob Herring 12724ba675SRob Herring aliases { 13724ba675SRob Herring serial0 = &uart0; 14724ba675SRob Herring serial1 = &uart1; 15724ba675SRob Herring timer0 = &timer0; 16724ba675SRob Herring timer1 = &timer1; 17724ba675SRob Herring timer2 = &timer2; 18724ba675SRob Herring timer3 = &timer3; 19724ba675SRob Herring }; 20724ba675SRob Herring 21724ba675SRob Herring cpus { 22724ba675SRob Herring #address-cells = <1>; 23724ba675SRob Herring #size-cells = <0>; 24724ba675SRob Herring enable-method = "altr,socfpga-smp"; 25724ba675SRob Herring 26724ba675SRob Herring cpu0: cpu@0 { 27724ba675SRob Herring compatible = "arm,cortex-a9"; 28724ba675SRob Herring device_type = "cpu"; 29724ba675SRob Herring reg = <0>; 30724ba675SRob Herring next-level-cache = <&L2>; 31724ba675SRob Herring }; 32724ba675SRob Herring cpu1: cpu@1 { 33724ba675SRob Herring compatible = "arm,cortex-a9"; 34724ba675SRob Herring device_type = "cpu"; 35724ba675SRob Herring reg = <1>; 36724ba675SRob Herring next-level-cache = <&L2>; 37724ba675SRob Herring }; 38724ba675SRob Herring }; 39724ba675SRob Herring 40724ba675SRob Herring pmu: pmu@ff111000 { 41724ba675SRob Herring compatible = "arm,cortex-a9-pmu"; 42724ba675SRob Herring interrupt-parent = <&intc>; 43724ba675SRob Herring interrupts = <0 176 4>, <0 177 4>; 44724ba675SRob Herring interrupt-affinity = <&cpu0>, <&cpu1>; 45724ba675SRob Herring reg = <0xff111000 0x1000>, 46724ba675SRob Herring <0xff113000 0x1000>; 47724ba675SRob Herring }; 48724ba675SRob Herring 49724ba675SRob Herring intc: interrupt-controller@fffed000 { 50724ba675SRob Herring compatible = "arm,cortex-a9-gic"; 51724ba675SRob Herring #interrupt-cells = <3>; 52724ba675SRob Herring interrupt-controller; 53724ba675SRob Herring reg = <0xfffed000 0x1000>, 54724ba675SRob Herring <0xfffec100 0x100>; 55724ba675SRob Herring }; 56724ba675SRob Herring 57724ba675SRob Herring soc { 58724ba675SRob Herring #address-cells = <1>; 59724ba675SRob Herring #size-cells = <1>; 60724ba675SRob Herring compatible = "simple-bus"; 61724ba675SRob Herring device_type = "soc"; 62724ba675SRob Herring interrupt-parent = <&intc>; 63724ba675SRob Herring ranges; 64724ba675SRob Herring 65724ba675SRob Herring amba { 66724ba675SRob Herring compatible = "simple-bus"; 67724ba675SRob Herring #address-cells = <1>; 68724ba675SRob Herring #size-cells = <1>; 69724ba675SRob Herring ranges; 70724ba675SRob Herring 71724ba675SRob Herring pdma: pdma@ffe01000 { 72724ba675SRob Herring compatible = "arm,pl330", "arm,primecell"; 73724ba675SRob Herring reg = <0xffe01000 0x1000>; 74724ba675SRob Herring interrupts = <0 104 4>, 75724ba675SRob Herring <0 105 4>, 76724ba675SRob Herring <0 106 4>, 77724ba675SRob Herring <0 107 4>, 78724ba675SRob Herring <0 108 4>, 79724ba675SRob Herring <0 109 4>, 80724ba675SRob Herring <0 110 4>, 81724ba675SRob Herring <0 111 4>; 82724ba675SRob Herring #dma-cells = <1>; 83724ba675SRob Herring clocks = <&l4_main_clk>; 84724ba675SRob Herring clock-names = "apb_pclk"; 85724ba675SRob Herring resets = <&rst DMA_RESET>; 86724ba675SRob Herring reset-names = "dma"; 87724ba675SRob Herring }; 88724ba675SRob Herring }; 89724ba675SRob Herring 90724ba675SRob Herring base_fpga_region { 91724ba675SRob Herring compatible = "fpga-region"; 92724ba675SRob Herring fpga-mgr = <&fpgamgr0>; 93724ba675SRob Herring 94724ba675SRob Herring #address-cells = <0x1>; 95724ba675SRob Herring #size-cells = <0x1>; 96724ba675SRob Herring }; 97724ba675SRob Herring 98724ba675SRob Herring can0: can@ffc00000 { 99724ba675SRob Herring compatible = "bosch,d_can"; 100724ba675SRob Herring reg = <0xffc00000 0x1000>; 101724ba675SRob Herring interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>; 102724ba675SRob Herring clocks = <&can0_clk>; 103724ba675SRob Herring resets = <&rst CAN0_RESET>; 104724ba675SRob Herring status = "disabled"; 105724ba675SRob Herring }; 106724ba675SRob Herring 107724ba675SRob Herring can1: can@ffc01000 { 108724ba675SRob Herring compatible = "bosch,d_can"; 109724ba675SRob Herring reg = <0xffc01000 0x1000>; 110724ba675SRob Herring interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>; 111724ba675SRob Herring clocks = <&can1_clk>; 112724ba675SRob Herring resets = <&rst CAN1_RESET>; 113724ba675SRob Herring status = "disabled"; 114724ba675SRob Herring }; 115724ba675SRob Herring 116724ba675SRob Herring clkmgr@ffd04000 { 117724ba675SRob Herring compatible = "altr,clk-mgr"; 118724ba675SRob Herring reg = <0xffd04000 0x1000>; 119724ba675SRob Herring 120724ba675SRob Herring clocks { 121724ba675SRob Herring #address-cells = <1>; 122724ba675SRob Herring #size-cells = <0>; 123724ba675SRob Herring 124724ba675SRob Herring osc1: osc1 { 125724ba675SRob Herring #clock-cells = <0>; 126724ba675SRob Herring compatible = "fixed-clock"; 127724ba675SRob Herring }; 128724ba675SRob Herring 129724ba675SRob Herring osc2: osc2 { 130724ba675SRob Herring #clock-cells = <0>; 131724ba675SRob Herring compatible = "fixed-clock"; 132724ba675SRob Herring }; 133724ba675SRob Herring 134724ba675SRob Herring f2s_periph_ref_clk: f2s_periph_ref_clk { 135724ba675SRob Herring #clock-cells = <0>; 136724ba675SRob Herring compatible = "fixed-clock"; 137724ba675SRob Herring }; 138724ba675SRob Herring 139724ba675SRob Herring f2s_sdram_ref_clk: f2s_sdram_ref_clk { 140724ba675SRob Herring #clock-cells = <0>; 141724ba675SRob Herring compatible = "fixed-clock"; 142724ba675SRob Herring }; 143724ba675SRob Herring 144724ba675SRob Herring main_pll: main_pll@40 { 145724ba675SRob Herring #address-cells = <1>; 146724ba675SRob Herring #size-cells = <0>; 147724ba675SRob Herring #clock-cells = <0>; 148724ba675SRob Herring compatible = "altr,socfpga-pll-clock"; 149724ba675SRob Herring clocks = <&osc1>; 150724ba675SRob Herring reg = <0x40>; 151724ba675SRob Herring 152724ba675SRob Herring mpuclk: mpuclk@48 { 153724ba675SRob Herring #clock-cells = <0>; 154724ba675SRob Herring compatible = "altr,socfpga-perip-clk"; 155724ba675SRob Herring clocks = <&main_pll>; 156724ba675SRob Herring div-reg = <0xe0 0 9>; 157724ba675SRob Herring reg = <0x48>; 158724ba675SRob Herring }; 159724ba675SRob Herring 160724ba675SRob Herring mainclk: mainclk@4c { 161724ba675SRob Herring #clock-cells = <0>; 162724ba675SRob Herring compatible = "altr,socfpga-perip-clk"; 163724ba675SRob Herring clocks = <&main_pll>; 164724ba675SRob Herring div-reg = <0xe4 0 9>; 165724ba675SRob Herring reg = <0x4C>; 166724ba675SRob Herring }; 167724ba675SRob Herring 168724ba675SRob Herring dbg_base_clk: dbg_base_clk@50 { 169724ba675SRob Herring #clock-cells = <0>; 170724ba675SRob Herring compatible = "altr,socfpga-perip-clk"; 171724ba675SRob Herring clocks = <&main_pll>, <&osc1>; 172724ba675SRob Herring div-reg = <0xe8 0 9>; 173724ba675SRob Herring reg = <0x50>; 174724ba675SRob Herring }; 175724ba675SRob Herring 176724ba675SRob Herring main_qspi_clk: main_qspi_clk@54 { 177724ba675SRob Herring #clock-cells = <0>; 178724ba675SRob Herring compatible = "altr,socfpga-perip-clk"; 179724ba675SRob Herring clocks = <&main_pll>; 180724ba675SRob Herring reg = <0x54>; 181724ba675SRob Herring }; 182724ba675SRob Herring 183724ba675SRob Herring main_nand_sdmmc_clk: main_nand_sdmmc_clk@58 { 184724ba675SRob Herring #clock-cells = <0>; 185724ba675SRob Herring compatible = "altr,socfpga-perip-clk"; 186724ba675SRob Herring clocks = <&main_pll>; 187724ba675SRob Herring reg = <0x58>; 188724ba675SRob Herring }; 189724ba675SRob Herring 190724ba675SRob Herring cfg_h2f_usr0_clk: cfg_h2f_usr0_clk@5c { 191724ba675SRob Herring #clock-cells = <0>; 192724ba675SRob Herring compatible = "altr,socfpga-perip-clk"; 193724ba675SRob Herring clocks = <&main_pll>; 194724ba675SRob Herring reg = <0x5C>; 195724ba675SRob Herring }; 196724ba675SRob Herring }; 197724ba675SRob Herring 198724ba675SRob Herring periph_pll: periph_pll@80 { 199724ba675SRob Herring #address-cells = <1>; 200724ba675SRob Herring #size-cells = <0>; 201724ba675SRob Herring #clock-cells = <0>; 202724ba675SRob Herring compatible = "altr,socfpga-pll-clock"; 203724ba675SRob Herring clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>; 204724ba675SRob Herring reg = <0x80>; 205724ba675SRob Herring 206724ba675SRob Herring emac0_clk: emac0_clk@88 { 207724ba675SRob Herring #clock-cells = <0>; 208724ba675SRob Herring compatible = "altr,socfpga-perip-clk"; 209724ba675SRob Herring clocks = <&periph_pll>; 210724ba675SRob Herring reg = <0x88>; 211724ba675SRob Herring }; 212724ba675SRob Herring 213724ba675SRob Herring emac1_clk: emac1_clk@8c { 214724ba675SRob Herring #clock-cells = <0>; 215724ba675SRob Herring compatible = "altr,socfpga-perip-clk"; 216724ba675SRob Herring clocks = <&periph_pll>; 217724ba675SRob Herring reg = <0x8C>; 218724ba675SRob Herring }; 219724ba675SRob Herring 220724ba675SRob Herring per_qspi_clk: per_qsi_clk@90 { 221724ba675SRob Herring #clock-cells = <0>; 222724ba675SRob Herring compatible = "altr,socfpga-perip-clk"; 223724ba675SRob Herring clocks = <&periph_pll>; 224724ba675SRob Herring reg = <0x90>; 225724ba675SRob Herring }; 226724ba675SRob Herring 227724ba675SRob Herring per_nand_mmc_clk: per_nand_mmc_clk@94 { 228724ba675SRob Herring #clock-cells = <0>; 229724ba675SRob Herring compatible = "altr,socfpga-perip-clk"; 230724ba675SRob Herring clocks = <&periph_pll>; 231724ba675SRob Herring reg = <0x94>; 232724ba675SRob Herring }; 233724ba675SRob Herring 234724ba675SRob Herring per_base_clk: per_base_clk@98 { 235724ba675SRob Herring #clock-cells = <0>; 236724ba675SRob Herring compatible = "altr,socfpga-perip-clk"; 237724ba675SRob Herring clocks = <&periph_pll>; 238724ba675SRob Herring reg = <0x98>; 239724ba675SRob Herring }; 240724ba675SRob Herring 241724ba675SRob Herring h2f_usr1_clk: h2f_usr1_clk@9c { 242724ba675SRob Herring #clock-cells = <0>; 243724ba675SRob Herring compatible = "altr,socfpga-perip-clk"; 244724ba675SRob Herring clocks = <&periph_pll>; 245724ba675SRob Herring reg = <0x9C>; 246724ba675SRob Herring }; 247724ba675SRob Herring }; 248724ba675SRob Herring 249724ba675SRob Herring sdram_pll: sdram_pll@c0 { 250724ba675SRob Herring #address-cells = <1>; 251724ba675SRob Herring #size-cells = <0>; 252724ba675SRob Herring #clock-cells = <0>; 253724ba675SRob Herring compatible = "altr,socfpga-pll-clock"; 254724ba675SRob Herring clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>; 255724ba675SRob Herring reg = <0xC0>; 256724ba675SRob Herring 257724ba675SRob Herring ddr_dqs_clk: ddr_dqs_clk@c8 { 258724ba675SRob Herring #clock-cells = <0>; 259724ba675SRob Herring compatible = "altr,socfpga-perip-clk"; 260724ba675SRob Herring clocks = <&sdram_pll>; 261724ba675SRob Herring reg = <0xC8>; 262724ba675SRob Herring }; 263724ba675SRob Herring 264724ba675SRob Herring ddr_2x_dqs_clk: ddr_2x_dqs_clk@cc { 265724ba675SRob Herring #clock-cells = <0>; 266724ba675SRob Herring compatible = "altr,socfpga-perip-clk"; 267724ba675SRob Herring clocks = <&sdram_pll>; 268724ba675SRob Herring reg = <0xCC>; 269724ba675SRob Herring }; 270724ba675SRob Herring 271724ba675SRob Herring ddr_dq_clk: ddr_dq_clk@d0 { 272724ba675SRob Herring #clock-cells = <0>; 273724ba675SRob Herring compatible = "altr,socfpga-perip-clk"; 274724ba675SRob Herring clocks = <&sdram_pll>; 275724ba675SRob Herring reg = <0xD0>; 276724ba675SRob Herring }; 277724ba675SRob Herring 278724ba675SRob Herring h2f_usr2_clk: h2f_usr2_clk@d4 { 279724ba675SRob Herring #clock-cells = <0>; 280724ba675SRob Herring compatible = "altr,socfpga-perip-clk"; 281724ba675SRob Herring clocks = <&sdram_pll>; 282724ba675SRob Herring reg = <0xD4>; 283724ba675SRob Herring }; 284724ba675SRob Herring }; 285724ba675SRob Herring 286724ba675SRob Herring mpu_periph_clk: mpu_periph_clk { 287724ba675SRob Herring #clock-cells = <0>; 288724ba675SRob Herring compatible = "altr,socfpga-perip-clk"; 289724ba675SRob Herring clocks = <&mpuclk>; 290724ba675SRob Herring fixed-divider = <4>; 291724ba675SRob Herring }; 292724ba675SRob Herring 293724ba675SRob Herring mpu_l2_ram_clk: mpu_l2_ram_clk { 294724ba675SRob Herring #clock-cells = <0>; 295724ba675SRob Herring compatible = "altr,socfpga-perip-clk"; 296724ba675SRob Herring clocks = <&mpuclk>; 297724ba675SRob Herring fixed-divider = <2>; 298724ba675SRob Herring }; 299724ba675SRob Herring 300724ba675SRob Herring l4_main_clk: l4_main_clk { 301724ba675SRob Herring #clock-cells = <0>; 302724ba675SRob Herring compatible = "altr,socfpga-gate-clk"; 303724ba675SRob Herring clocks = <&mainclk>; 304724ba675SRob Herring clk-gate = <0x60 0>; 305724ba675SRob Herring }; 306724ba675SRob Herring 307724ba675SRob Herring l3_main_clk: l3_main_clk { 308724ba675SRob Herring #clock-cells = <0>; 309724ba675SRob Herring compatible = "altr,socfpga-perip-clk"; 310724ba675SRob Herring clocks = <&mainclk>; 311724ba675SRob Herring fixed-divider = <1>; 312724ba675SRob Herring }; 313724ba675SRob Herring 314724ba675SRob Herring l3_mp_clk: l3_mp_clk { 315724ba675SRob Herring #clock-cells = <0>; 316724ba675SRob Herring compatible = "altr,socfpga-gate-clk"; 317724ba675SRob Herring clocks = <&mainclk>; 318724ba675SRob Herring div-reg = <0x64 0 2>; 319724ba675SRob Herring clk-gate = <0x60 1>; 320724ba675SRob Herring }; 321724ba675SRob Herring 322724ba675SRob Herring l3_sp_clk: l3_sp_clk { 323724ba675SRob Herring #clock-cells = <0>; 324724ba675SRob Herring compatible = "altr,socfpga-gate-clk"; 325724ba675SRob Herring clocks = <&l3_mp_clk>; 326724ba675SRob Herring div-reg = <0x64 2 2>; 327724ba675SRob Herring }; 328724ba675SRob Herring 329724ba675SRob Herring l4_mp_clk: l4_mp_clk { 330724ba675SRob Herring #clock-cells = <0>; 331724ba675SRob Herring compatible = "altr,socfpga-gate-clk"; 332724ba675SRob Herring clocks = <&mainclk>, <&per_base_clk>; 333724ba675SRob Herring div-reg = <0x64 4 3>; 334724ba675SRob Herring clk-gate = <0x60 2>; 335724ba675SRob Herring }; 336724ba675SRob Herring 337724ba675SRob Herring l4_sp_clk: l4_sp_clk { 338724ba675SRob Herring #clock-cells = <0>; 339724ba675SRob Herring compatible = "altr,socfpga-gate-clk"; 340724ba675SRob Herring clocks = <&mainclk>, <&per_base_clk>; 341724ba675SRob Herring div-reg = <0x64 7 3>; 342724ba675SRob Herring clk-gate = <0x60 3>; 343724ba675SRob Herring }; 344724ba675SRob Herring 345724ba675SRob Herring dbg_at_clk: dbg_at_clk { 346724ba675SRob Herring #clock-cells = <0>; 347724ba675SRob Herring compatible = "altr,socfpga-gate-clk"; 348724ba675SRob Herring clocks = <&dbg_base_clk>; 349724ba675SRob Herring div-reg = <0x68 0 2>; 350724ba675SRob Herring clk-gate = <0x60 4>; 351724ba675SRob Herring }; 352724ba675SRob Herring 353724ba675SRob Herring dbg_clk: dbg_clk { 354724ba675SRob Herring #clock-cells = <0>; 355724ba675SRob Herring compatible = "altr,socfpga-gate-clk"; 356724ba675SRob Herring clocks = <&dbg_at_clk>; 357724ba675SRob Herring div-reg = <0x68 2 2>; 358724ba675SRob Herring clk-gate = <0x60 5>; 359724ba675SRob Herring }; 360724ba675SRob Herring 361724ba675SRob Herring dbg_trace_clk: dbg_trace_clk { 362724ba675SRob Herring #clock-cells = <0>; 363724ba675SRob Herring compatible = "altr,socfpga-gate-clk"; 364724ba675SRob Herring clocks = <&dbg_base_clk>; 365724ba675SRob Herring div-reg = <0x6C 0 3>; 366724ba675SRob Herring clk-gate = <0x60 6>; 367724ba675SRob Herring }; 368724ba675SRob Herring 369724ba675SRob Herring dbg_timer_clk: dbg_timer_clk { 370724ba675SRob Herring #clock-cells = <0>; 371724ba675SRob Herring compatible = "altr,socfpga-gate-clk"; 372724ba675SRob Herring clocks = <&dbg_base_clk>; 373724ba675SRob Herring clk-gate = <0x60 7>; 374724ba675SRob Herring }; 375724ba675SRob Herring 376724ba675SRob Herring cfg_clk: cfg_clk { 377724ba675SRob Herring #clock-cells = <0>; 378724ba675SRob Herring compatible = "altr,socfpga-gate-clk"; 379724ba675SRob Herring clocks = <&cfg_h2f_usr0_clk>; 380724ba675SRob Herring clk-gate = <0x60 8>; 381724ba675SRob Herring }; 382724ba675SRob Herring 383724ba675SRob Herring h2f_user0_clk: h2f_user0_clk { 384724ba675SRob Herring #clock-cells = <0>; 385724ba675SRob Herring compatible = "altr,socfpga-gate-clk"; 386724ba675SRob Herring clocks = <&cfg_h2f_usr0_clk>; 387724ba675SRob Herring clk-gate = <0x60 9>; 388724ba675SRob Herring }; 389724ba675SRob Herring 390724ba675SRob Herring emac_0_clk: emac_0_clk { 391724ba675SRob Herring #clock-cells = <0>; 392724ba675SRob Herring compatible = "altr,socfpga-gate-clk"; 393724ba675SRob Herring clocks = <&emac0_clk>; 394724ba675SRob Herring clk-gate = <0xa0 0>; 395724ba675SRob Herring }; 396724ba675SRob Herring 397724ba675SRob Herring emac_1_clk: emac_1_clk { 398724ba675SRob Herring #clock-cells = <0>; 399724ba675SRob Herring compatible = "altr,socfpga-gate-clk"; 400724ba675SRob Herring clocks = <&emac1_clk>; 401724ba675SRob Herring clk-gate = <0xa0 1>; 402724ba675SRob Herring }; 403724ba675SRob Herring 404724ba675SRob Herring usb_mp_clk: usb_mp_clk { 405724ba675SRob Herring #clock-cells = <0>; 406724ba675SRob Herring compatible = "altr,socfpga-gate-clk"; 407724ba675SRob Herring clocks = <&per_base_clk>; 408724ba675SRob Herring clk-gate = <0xa0 2>; 409724ba675SRob Herring div-reg = <0xa4 0 3>; 410724ba675SRob Herring }; 411724ba675SRob Herring 412724ba675SRob Herring spi_m_clk: spi_m_clk { 413724ba675SRob Herring #clock-cells = <0>; 414724ba675SRob Herring compatible = "altr,socfpga-gate-clk"; 415724ba675SRob Herring clocks = <&per_base_clk>; 416724ba675SRob Herring clk-gate = <0xa0 3>; 417724ba675SRob Herring div-reg = <0xa4 3 3>; 418724ba675SRob Herring }; 419724ba675SRob Herring 420724ba675SRob Herring can0_clk: can0_clk { 421724ba675SRob Herring #clock-cells = <0>; 422724ba675SRob Herring compatible = "altr,socfpga-gate-clk"; 423724ba675SRob Herring clocks = <&per_base_clk>; 424724ba675SRob Herring clk-gate = <0xa0 4>; 425724ba675SRob Herring div-reg = <0xa4 6 3>; 426724ba675SRob Herring }; 427724ba675SRob Herring 428724ba675SRob Herring can1_clk: can1_clk { 429724ba675SRob Herring #clock-cells = <0>; 430724ba675SRob Herring compatible = "altr,socfpga-gate-clk"; 431724ba675SRob Herring clocks = <&per_base_clk>; 432724ba675SRob Herring clk-gate = <0xa0 5>; 433724ba675SRob Herring div-reg = <0xa4 9 3>; 434724ba675SRob Herring }; 435724ba675SRob Herring 436724ba675SRob Herring gpio_db_clk: gpio_db_clk { 437724ba675SRob Herring #clock-cells = <0>; 438724ba675SRob Herring compatible = "altr,socfpga-gate-clk"; 439724ba675SRob Herring clocks = <&per_base_clk>; 440724ba675SRob Herring clk-gate = <0xa0 6>; 441724ba675SRob Herring div-reg = <0xa8 0 24>; 442724ba675SRob Herring }; 443724ba675SRob Herring 444724ba675SRob Herring h2f_user1_clk: h2f_user1_clk { 445724ba675SRob Herring #clock-cells = <0>; 446724ba675SRob Herring compatible = "altr,socfpga-gate-clk"; 447724ba675SRob Herring clocks = <&h2f_usr1_clk>; 448724ba675SRob Herring clk-gate = <0xa0 7>; 449724ba675SRob Herring }; 450724ba675SRob Herring 451724ba675SRob Herring sdmmc_clk: sdmmc_clk { 452724ba675SRob Herring #clock-cells = <0>; 453724ba675SRob Herring compatible = "altr,socfpga-gate-clk"; 454724ba675SRob Herring clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; 455724ba675SRob Herring clk-gate = <0xa0 8>; 456724ba675SRob Herring }; 457724ba675SRob Herring 458724ba675SRob Herring sdmmc_clk_divided: sdmmc_clk_divided { 459724ba675SRob Herring #clock-cells = <0>; 460724ba675SRob Herring compatible = "altr,socfpga-gate-clk"; 461724ba675SRob Herring clocks = <&sdmmc_clk>; 462724ba675SRob Herring clk-gate = <0xa0 8>; 463724ba675SRob Herring fixed-divider = <4>; 464724ba675SRob Herring }; 465724ba675SRob Herring 466724ba675SRob Herring nand_x_clk: nand_x_clk { 467724ba675SRob Herring #clock-cells = <0>; 468724ba675SRob Herring compatible = "altr,socfpga-gate-clk"; 469724ba675SRob Herring clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; 470724ba675SRob Herring clk-gate = <0xa0 9>; 471724ba675SRob Herring }; 472724ba675SRob Herring 473724ba675SRob Herring nand_ecc_clk: nand_ecc_clk { 474724ba675SRob Herring #clock-cells = <0>; 475724ba675SRob Herring compatible = "altr,socfpga-gate-clk"; 476724ba675SRob Herring clocks = <&nand_x_clk>; 477724ba675SRob Herring clk-gate = <0xa0 9>; 478724ba675SRob Herring }; 479724ba675SRob Herring 480724ba675SRob Herring nand_clk: nand_clk { 481724ba675SRob Herring #clock-cells = <0>; 482724ba675SRob Herring compatible = "altr,socfpga-gate-clk"; 483724ba675SRob Herring clocks = <&nand_x_clk>; 484724ba675SRob Herring clk-gate = <0xa0 10>; 485724ba675SRob Herring fixed-divider = <4>; 486724ba675SRob Herring }; 487724ba675SRob Herring 488724ba675SRob Herring qspi_clk: qspi_clk { 489724ba675SRob Herring #clock-cells = <0>; 490724ba675SRob Herring compatible = "altr,socfpga-gate-clk"; 491724ba675SRob Herring clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>; 492724ba675SRob Herring clk-gate = <0xa0 11>; 493724ba675SRob Herring }; 494724ba675SRob Herring 495724ba675SRob Herring ddr_dqs_clk_gate: ddr_dqs_clk_gate { 496724ba675SRob Herring #clock-cells = <0>; 497724ba675SRob Herring compatible = "altr,socfpga-gate-clk"; 498724ba675SRob Herring clocks = <&ddr_dqs_clk>; 499724ba675SRob Herring clk-gate = <0xd8 0>; 500724ba675SRob Herring }; 501724ba675SRob Herring 502724ba675SRob Herring ddr_2x_dqs_clk_gate: ddr_2x_dqs_clk_gate { 503724ba675SRob Herring #clock-cells = <0>; 504724ba675SRob Herring compatible = "altr,socfpga-gate-clk"; 505724ba675SRob Herring clocks = <&ddr_2x_dqs_clk>; 506724ba675SRob Herring clk-gate = <0xd8 1>; 507724ba675SRob Herring }; 508724ba675SRob Herring 509724ba675SRob Herring ddr_dq_clk_gate: ddr_dq_clk_gate { 510724ba675SRob Herring #clock-cells = <0>; 511724ba675SRob Herring compatible = "altr,socfpga-gate-clk"; 512724ba675SRob Herring clocks = <&ddr_dq_clk>; 513724ba675SRob Herring clk-gate = <0xd8 2>; 514724ba675SRob Herring }; 515724ba675SRob Herring 516724ba675SRob Herring h2f_user2_clk: h2f_user2_clk { 517724ba675SRob Herring #clock-cells = <0>; 518724ba675SRob Herring compatible = "altr,socfpga-gate-clk"; 519724ba675SRob Herring clocks = <&h2f_usr2_clk>; 520724ba675SRob Herring clk-gate = <0xd8 3>; 521724ba675SRob Herring }; 522724ba675SRob Herring 523724ba675SRob Herring }; 524724ba675SRob Herring }; 525724ba675SRob Herring 526724ba675SRob Herring fpga_bridge0: fpga_bridge@ff400000 { 527724ba675SRob Herring compatible = "altr,socfpga-lwhps2fpga-bridge"; 528724ba675SRob Herring reg = <0xff400000 0x100000>; 529724ba675SRob Herring resets = <&rst LWHPS2FPGA_RESET>; 530724ba675SRob Herring clocks = <&l4_main_clk>; 531724ba675SRob Herring status = "disabled"; 532724ba675SRob Herring }; 533724ba675SRob Herring 534724ba675SRob Herring fpga_bridge1: fpga_bridge@ff500000 { 535724ba675SRob Herring compatible = "altr,socfpga-hps2fpga-bridge"; 536724ba675SRob Herring reg = <0xff500000 0x10000>; 537724ba675SRob Herring resets = <&rst HPS2FPGA_RESET>; 538724ba675SRob Herring clocks = <&l4_main_clk>; 539724ba675SRob Herring status = "disabled"; 540724ba675SRob Herring }; 541724ba675SRob Herring 542724ba675SRob Herring fpga_bridge2: fpga-bridge@ff600000 { 543724ba675SRob Herring compatible = "altr,socfpga-fpga2hps-bridge"; 544724ba675SRob Herring reg = <0xff600000 0x100000>; 545724ba675SRob Herring resets = <&rst FPGA2HPS_RESET>; 546724ba675SRob Herring clocks = <&l4_main_clk>; 547724ba675SRob Herring status = "disabled"; 548724ba675SRob Herring }; 549724ba675SRob Herring 550724ba675SRob Herring fpga_bridge3: fpga-bridge@ffc25080 { 551724ba675SRob Herring compatible = "altr,socfpga-fpga2sdram-bridge"; 552724ba675SRob Herring reg = <0xffc25080 0x4>; 553724ba675SRob Herring status = "disabled"; 554724ba675SRob Herring }; 555724ba675SRob Herring 556724ba675SRob Herring fpgamgr0: fpgamgr@ff706000 { 557724ba675SRob Herring compatible = "altr,socfpga-fpga-mgr"; 558724ba675SRob Herring reg = <0xff706000 0x1000 559724ba675SRob Herring 0xffb90000 0x4>; 560724ba675SRob Herring interrupts = <0 175 4>; 561724ba675SRob Herring }; 562724ba675SRob Herring 563724ba675SRob Herring socfpga_axi_setup: stmmac-axi-config { 564724ba675SRob Herring snps,wr_osr_lmt = <0xf>; 565724ba675SRob Herring snps,rd_osr_lmt = <0xf>; 566724ba675SRob Herring snps,blen = <0 0 0 0 16 0 0>; 567724ba675SRob Herring }; 568724ba675SRob Herring 569724ba675SRob Herring gmac0: ethernet@ff700000 { 570724ba675SRob Herring compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; 571724ba675SRob Herring altr,sysmgr-syscon = <&sysmgr 0x60 0>; 572724ba675SRob Herring reg = <0xff700000 0x2000>; 573724ba675SRob Herring interrupts = <0 115 4>; 574724ba675SRob Herring interrupt-names = "macirq"; 575724ba675SRob Herring mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ 576724ba675SRob Herring clocks = <&emac_0_clk>; 577724ba675SRob Herring clock-names = "stmmaceth"; 578724ba675SRob Herring resets = <&rst EMAC0_RESET>; 579724ba675SRob Herring reset-names = "stmmaceth"; 580724ba675SRob Herring snps,multicast-filter-bins = <256>; 581724ba675SRob Herring snps,perfect-filter-entries = <128>; 582724ba675SRob Herring tx-fifo-depth = <4096>; 583724ba675SRob Herring rx-fifo-depth = <4096>; 584724ba675SRob Herring snps,axi-config = <&socfpga_axi_setup>; 585724ba675SRob Herring status = "disabled"; 586724ba675SRob Herring }; 587724ba675SRob Herring 588724ba675SRob Herring gmac1: ethernet@ff702000 { 589724ba675SRob Herring compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; 590724ba675SRob Herring altr,sysmgr-syscon = <&sysmgr 0x60 2>; 591724ba675SRob Herring reg = <0xff702000 0x2000>; 592724ba675SRob Herring interrupts = <0 120 4>; 593724ba675SRob Herring interrupt-names = "macirq"; 594724ba675SRob Herring mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ 595724ba675SRob Herring clocks = <&emac_1_clk>; 596724ba675SRob Herring clock-names = "stmmaceth"; 597724ba675SRob Herring resets = <&rst EMAC1_RESET>; 598724ba675SRob Herring reset-names = "stmmaceth"; 599724ba675SRob Herring snps,multicast-filter-bins = <256>; 600724ba675SRob Herring snps,perfect-filter-entries = <128>; 601724ba675SRob Herring tx-fifo-depth = <4096>; 602724ba675SRob Herring rx-fifo-depth = <4096>; 603724ba675SRob Herring snps,axi-config = <&socfpga_axi_setup>; 604724ba675SRob Herring status = "disabled"; 605724ba675SRob Herring }; 606724ba675SRob Herring 607724ba675SRob Herring gpio0: gpio@ff708000 { 608724ba675SRob Herring #address-cells = <1>; 609724ba675SRob Herring #size-cells = <0>; 610724ba675SRob Herring compatible = "snps,dw-apb-gpio"; 611724ba675SRob Herring reg = <0xff708000 0x1000>; 612724ba675SRob Herring clocks = <&l4_mp_clk>; 613724ba675SRob Herring resets = <&rst GPIO0_RESET>; 614724ba675SRob Herring status = "disabled"; 615724ba675SRob Herring 616724ba675SRob Herring porta: gpio-controller@0 { 617724ba675SRob Herring compatible = "snps,dw-apb-gpio-port"; 618724ba675SRob Herring gpio-controller; 619724ba675SRob Herring #gpio-cells = <2>; 620724ba675SRob Herring snps,nr-gpios = <29>; 621724ba675SRob Herring reg = <0>; 622724ba675SRob Herring interrupt-controller; 623724ba675SRob Herring #interrupt-cells = <2>; 624724ba675SRob Herring interrupts = <0 164 4>; 625724ba675SRob Herring }; 626724ba675SRob Herring }; 627724ba675SRob Herring 628724ba675SRob Herring gpio1: gpio@ff709000 { 629724ba675SRob Herring #address-cells = <1>; 630724ba675SRob Herring #size-cells = <0>; 631724ba675SRob Herring compatible = "snps,dw-apb-gpio"; 632724ba675SRob Herring reg = <0xff709000 0x1000>; 633724ba675SRob Herring clocks = <&l4_mp_clk>; 634724ba675SRob Herring resets = <&rst GPIO1_RESET>; 635724ba675SRob Herring status = "disabled"; 636724ba675SRob Herring 637724ba675SRob Herring portb: gpio-controller@0 { 638724ba675SRob Herring compatible = "snps,dw-apb-gpio-port"; 639724ba675SRob Herring gpio-controller; 640724ba675SRob Herring #gpio-cells = <2>; 641724ba675SRob Herring snps,nr-gpios = <29>; 642724ba675SRob Herring reg = <0>; 643724ba675SRob Herring interrupt-controller; 644724ba675SRob Herring #interrupt-cells = <2>; 645724ba675SRob Herring interrupts = <0 165 4>; 646724ba675SRob Herring }; 647724ba675SRob Herring }; 648724ba675SRob Herring 649724ba675SRob Herring gpio2: gpio@ff70a000 { 650724ba675SRob Herring #address-cells = <1>; 651724ba675SRob Herring #size-cells = <0>; 652724ba675SRob Herring compatible = "snps,dw-apb-gpio"; 653724ba675SRob Herring reg = <0xff70a000 0x1000>; 654724ba675SRob Herring clocks = <&l4_mp_clk>; 655724ba675SRob Herring resets = <&rst GPIO2_RESET>; 656724ba675SRob Herring status = "disabled"; 657724ba675SRob Herring 658724ba675SRob Herring portc: gpio-controller@0 { 659724ba675SRob Herring compatible = "snps,dw-apb-gpio-port"; 660724ba675SRob Herring gpio-controller; 661724ba675SRob Herring #gpio-cells = <2>; 662724ba675SRob Herring snps,nr-gpios = <27>; 663724ba675SRob Herring reg = <0>; 664724ba675SRob Herring interrupt-controller; 665724ba675SRob Herring #interrupt-cells = <2>; 666724ba675SRob Herring interrupts = <0 166 4>; 667724ba675SRob Herring }; 668724ba675SRob Herring }; 669724ba675SRob Herring 670724ba675SRob Herring i2c0: i2c@ffc04000 { 671724ba675SRob Herring #address-cells = <1>; 672724ba675SRob Herring #size-cells = <0>; 673724ba675SRob Herring compatible = "snps,designware-i2c"; 674724ba675SRob Herring reg = <0xffc04000 0x1000>; 675724ba675SRob Herring resets = <&rst I2C0_RESET>; 676724ba675SRob Herring clocks = <&l4_sp_clk>; 677724ba675SRob Herring interrupts = <0 158 0x4>; 678724ba675SRob Herring status = "disabled"; 679724ba675SRob Herring }; 680724ba675SRob Herring 681724ba675SRob Herring i2c1: i2c@ffc05000 { 682724ba675SRob Herring #address-cells = <1>; 683724ba675SRob Herring #size-cells = <0>; 684724ba675SRob Herring compatible = "snps,designware-i2c"; 685724ba675SRob Herring reg = <0xffc05000 0x1000>; 686724ba675SRob Herring resets = <&rst I2C1_RESET>; 687724ba675SRob Herring clocks = <&l4_sp_clk>; 688724ba675SRob Herring interrupts = <0 159 0x4>; 689724ba675SRob Herring status = "disabled"; 690724ba675SRob Herring }; 691724ba675SRob Herring 692724ba675SRob Herring i2c2: i2c@ffc06000 { 693724ba675SRob Herring #address-cells = <1>; 694724ba675SRob Herring #size-cells = <0>; 695724ba675SRob Herring compatible = "snps,designware-i2c"; 696724ba675SRob Herring reg = <0xffc06000 0x1000>; 697724ba675SRob Herring resets = <&rst I2C2_RESET>; 698724ba675SRob Herring clocks = <&l4_sp_clk>; 699724ba675SRob Herring interrupts = <0 160 0x4>; 700724ba675SRob Herring status = "disabled"; 701724ba675SRob Herring }; 702724ba675SRob Herring 703724ba675SRob Herring i2c3: i2c@ffc07000 { 704724ba675SRob Herring #address-cells = <1>; 705724ba675SRob Herring #size-cells = <0>; 706724ba675SRob Herring compatible = "snps,designware-i2c"; 707724ba675SRob Herring reg = <0xffc07000 0x1000>; 708724ba675SRob Herring resets = <&rst I2C3_RESET>; 709724ba675SRob Herring clocks = <&l4_sp_clk>; 710724ba675SRob Herring interrupts = <0 161 0x4>; 711724ba675SRob Herring status = "disabled"; 712724ba675SRob Herring }; 713724ba675SRob Herring 714724ba675SRob Herring eccmgr: eccmgr { 715724ba675SRob Herring compatible = "altr,socfpga-ecc-manager"; 716724ba675SRob Herring #address-cells = <1>; 717724ba675SRob Herring #size-cells = <1>; 718724ba675SRob Herring ranges; 719724ba675SRob Herring 720724ba675SRob Herring l2-ecc@ffd08140 { 721724ba675SRob Herring compatible = "altr,socfpga-l2-ecc"; 722724ba675SRob Herring reg = <0xffd08140 0x4>; 723724ba675SRob Herring interrupts = <0 36 1>, <0 37 1>; 724724ba675SRob Herring }; 725724ba675SRob Herring 726724ba675SRob Herring ocram-ecc@ffd08144 { 727724ba675SRob Herring compatible = "altr,socfpga-ocram-ecc"; 728724ba675SRob Herring reg = <0xffd08144 0x4>; 729724ba675SRob Herring iram = <&ocram>; 730724ba675SRob Herring interrupts = <0 178 1>, <0 179 1>; 731724ba675SRob Herring }; 732724ba675SRob Herring }; 733724ba675SRob Herring 734724ba675SRob Herring L2: cache-controller@fffef000 { 735724ba675SRob Herring compatible = "arm,pl310-cache"; 736724ba675SRob Herring reg = <0xfffef000 0x1000>; 737724ba675SRob Herring interrupts = <0 38 0x04>; 738724ba675SRob Herring cache-unified; 739724ba675SRob Herring cache-level = <2>; 740724ba675SRob Herring arm,tag-latency = <1 1 1>; 741724ba675SRob Herring arm,data-latency = <2 1 1>; 742724ba675SRob Herring prefetch-data = <1>; 743724ba675SRob Herring prefetch-instr = <1>; 744724ba675SRob Herring arm,shared-override; 745724ba675SRob Herring arm,double-linefill = <1>; 746724ba675SRob Herring arm,double-linefill-incr = <0>; 747724ba675SRob Herring arm,double-linefill-wrap = <1>; 748724ba675SRob Herring arm,prefetch-drop = <0>; 749724ba675SRob Herring arm,prefetch-offset = <7>; 750724ba675SRob Herring }; 751724ba675SRob Herring 752724ba675SRob Herring l3regs@ff800000 { 753724ba675SRob Herring compatible = "altr,l3regs", "syscon"; 754724ba675SRob Herring reg = <0xff800000 0x1000>; 755724ba675SRob Herring }; 756724ba675SRob Herring 757724ba675SRob Herring mmc: mmc@ff704000 { 758724ba675SRob Herring compatible = "altr,socfpga-dw-mshc"; 759724ba675SRob Herring reg = <0xff704000 0x1000>; 760724ba675SRob Herring interrupts = <0 139 4>; 761724ba675SRob Herring fifo-depth = <0x400>; 762724ba675SRob Herring #address-cells = <1>; 763724ba675SRob Herring #size-cells = <0>; 764724ba675SRob Herring clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>; 765724ba675SRob Herring clock-names = "biu", "ciu"; 766724ba675SRob Herring resets = <&rst SDMMC_RESET>; 767724ba675SRob Herring altr,sysmgr-syscon = <&sysmgr 0x108 3>; 768724ba675SRob Herring status = "disabled"; 769724ba675SRob Herring }; 770724ba675SRob Herring 771*575c726cSKrzysztof Kozlowski nand0: nand-controller@ff900000 { 772724ba675SRob Herring #address-cells = <0x1>; 773724ba675SRob Herring #size-cells = <0x0>; 774724ba675SRob Herring compatible = "altr,socfpga-denali-nand"; 775724ba675SRob Herring reg = <0xff900000 0x100000>, 776724ba675SRob Herring <0xffb80000 0x10000>; 777724ba675SRob Herring reg-names = "nand_data", "denali_reg"; 778724ba675SRob Herring interrupts = <0x0 0x90 0x4>; 779724ba675SRob Herring clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>; 780724ba675SRob Herring clock-names = "nand", "nand_x", "ecc"; 781724ba675SRob Herring resets = <&rst NAND_RESET>; 782724ba675SRob Herring status = "disabled"; 783724ba675SRob Herring }; 784724ba675SRob Herring 785724ba675SRob Herring ocram: sram@ffff0000 { 786724ba675SRob Herring compatible = "mmio-sram"; 787724ba675SRob Herring reg = <0xffff0000 0x10000>; 788724ba675SRob Herring }; 789724ba675SRob Herring 790724ba675SRob Herring qspi: spi@ff705000 { 791724ba675SRob Herring compatible = "intel,socfpga-qspi", "cdns,qspi-nor"; 792724ba675SRob Herring #address-cells = <1>; 793724ba675SRob Herring #size-cells = <0>; 794724ba675SRob Herring reg = <0xff705000 0x1000>, 795724ba675SRob Herring <0xffa00000 0x1000>; 796724ba675SRob Herring interrupts = <0 151 4>; 797724ba675SRob Herring cdns,fifo-depth = <128>; 798724ba675SRob Herring cdns,fifo-width = <4>; 799724ba675SRob Herring cdns,trigger-address = <0x00000000>; 800724ba675SRob Herring clocks = <&qspi_clk>; 801724ba675SRob Herring resets = <&rst QSPI_RESET>; 802724ba675SRob Herring status = "disabled"; 803724ba675SRob Herring }; 804724ba675SRob Herring 805724ba675SRob Herring rst: rstmgr@ffd05000 { 806724ba675SRob Herring #reset-cells = <1>; 807724ba675SRob Herring compatible = "altr,rst-mgr"; 808724ba675SRob Herring reg = <0xffd05000 0x1000>; 809724ba675SRob Herring altr,modrst-offset = <0x10>; 810724ba675SRob Herring }; 811724ba675SRob Herring 812724ba675SRob Herring scu: snoop-control-unit@fffec000 { 813724ba675SRob Herring compatible = "arm,cortex-a9-scu"; 814724ba675SRob Herring reg = <0xfffec000 0x100>; 815724ba675SRob Herring }; 816724ba675SRob Herring 817724ba675SRob Herring sdr: sdr@ffc25000 { 818724ba675SRob Herring compatible = "altr,sdr-ctl", "syscon"; 819724ba675SRob Herring reg = <0xffc25000 0x1000>; 820724ba675SRob Herring resets = <&rst SDR_RESET>; 821724ba675SRob Herring }; 822724ba675SRob Herring 823724ba675SRob Herring sdramedac { 824724ba675SRob Herring compatible = "altr,sdram-edac"; 825724ba675SRob Herring altr,sdr-syscon = <&sdr>; 826724ba675SRob Herring interrupts = <0 39 4>; 827724ba675SRob Herring }; 828724ba675SRob Herring 829724ba675SRob Herring spi0: spi@fff00000 { 830724ba675SRob Herring compatible = "snps,dw-apb-ssi"; 831724ba675SRob Herring #address-cells = <1>; 832724ba675SRob Herring #size-cells = <0>; 833724ba675SRob Herring reg = <0xfff00000 0x1000>; 834724ba675SRob Herring interrupts = <0 154 4>; 835724ba675SRob Herring num-cs = <4>; 836724ba675SRob Herring clocks = <&spi_m_clk>; 837724ba675SRob Herring resets = <&rst SPIM0_RESET>; 838724ba675SRob Herring reset-names = "spi"; 839724ba675SRob Herring status = "disabled"; 840724ba675SRob Herring }; 841724ba675SRob Herring 842724ba675SRob Herring spi1: spi@fff01000 { 843724ba675SRob Herring compatible = "snps,dw-apb-ssi"; 844724ba675SRob Herring #address-cells = <1>; 845724ba675SRob Herring #size-cells = <0>; 846724ba675SRob Herring reg = <0xfff01000 0x1000>; 847724ba675SRob Herring interrupts = <0 155 4>; 848724ba675SRob Herring num-cs = <4>; 849724ba675SRob Herring clocks = <&spi_m_clk>; 850724ba675SRob Herring resets = <&rst SPIM1_RESET>; 851724ba675SRob Herring reset-names = "spi"; 852724ba675SRob Herring status = "disabled"; 853724ba675SRob Herring }; 854724ba675SRob Herring 855724ba675SRob Herring sysmgr: sysmgr@ffd08000 { 856724ba675SRob Herring compatible = "altr,sys-mgr", "syscon"; 857724ba675SRob Herring reg = <0xffd08000 0x4000>; 858724ba675SRob Herring }; 859724ba675SRob Herring 860724ba675SRob Herring /* Local timer */ 861724ba675SRob Herring timer@fffec600 { 862724ba675SRob Herring compatible = "arm,cortex-a9-twd-timer"; 863724ba675SRob Herring reg = <0xfffec600 0x100>; 864724ba675SRob Herring interrupts = <1 13 0xf01>; 865724ba675SRob Herring clocks = <&mpu_periph_clk>; 866724ba675SRob Herring }; 867724ba675SRob Herring 868724ba675SRob Herring timer0: timer0@ffc08000 { 869724ba675SRob Herring compatible = "snps,dw-apb-timer"; 870724ba675SRob Herring interrupts = <0 167 4>; 871724ba675SRob Herring reg = <0xffc08000 0x1000>; 872724ba675SRob Herring clocks = <&l4_sp_clk>; 873724ba675SRob Herring clock-names = "timer"; 874724ba675SRob Herring resets = <&rst SPTIMER0_RESET>; 875724ba675SRob Herring reset-names = "timer"; 876724ba675SRob Herring }; 877724ba675SRob Herring 878724ba675SRob Herring timer1: timer1@ffc09000 { 879724ba675SRob Herring compatible = "snps,dw-apb-timer"; 880724ba675SRob Herring interrupts = <0 168 4>; 881724ba675SRob Herring reg = <0xffc09000 0x1000>; 882724ba675SRob Herring clocks = <&l4_sp_clk>; 883724ba675SRob Herring clock-names = "timer"; 884724ba675SRob Herring resets = <&rst SPTIMER1_RESET>; 885724ba675SRob Herring reset-names = "timer"; 886724ba675SRob Herring }; 887724ba675SRob Herring 888724ba675SRob Herring timer2: timer2@ffd00000 { 889724ba675SRob Herring compatible = "snps,dw-apb-timer"; 890724ba675SRob Herring interrupts = <0 169 4>; 891724ba675SRob Herring reg = <0xffd00000 0x1000>; 892724ba675SRob Herring clocks = <&osc1>; 893724ba675SRob Herring clock-names = "timer"; 894724ba675SRob Herring resets = <&rst OSC1TIMER0_RESET>; 895724ba675SRob Herring reset-names = "timer"; 896724ba675SRob Herring }; 897724ba675SRob Herring 898724ba675SRob Herring timer3: timer3@ffd01000 { 899724ba675SRob Herring compatible = "snps,dw-apb-timer"; 900724ba675SRob Herring interrupts = <0 170 4>; 901724ba675SRob Herring reg = <0xffd01000 0x1000>; 902724ba675SRob Herring clocks = <&osc1>; 903724ba675SRob Herring clock-names = "timer"; 904724ba675SRob Herring resets = <&rst OSC1TIMER1_RESET>; 905724ba675SRob Herring reset-names = "timer"; 906724ba675SRob Herring }; 907724ba675SRob Herring 908724ba675SRob Herring uart0: serial@ffc02000 { 909724ba675SRob Herring compatible = "snps,dw-apb-uart"; 910724ba675SRob Herring reg = <0xffc02000 0x1000>; 911724ba675SRob Herring interrupts = <0 162 4>; 912724ba675SRob Herring reg-shift = <2>; 913724ba675SRob Herring reg-io-width = <4>; 914724ba675SRob Herring clocks = <&l4_sp_clk>; 915724ba675SRob Herring dmas = <&pdma 28>, 916724ba675SRob Herring <&pdma 29>; 917724ba675SRob Herring dma-names = "tx", "rx"; 918724ba675SRob Herring resets = <&rst UART0_RESET>; 919724ba675SRob Herring }; 920724ba675SRob Herring 921724ba675SRob Herring uart1: serial@ffc03000 { 922724ba675SRob Herring compatible = "snps,dw-apb-uart"; 923724ba675SRob Herring reg = <0xffc03000 0x1000>; 924724ba675SRob Herring interrupts = <0 163 4>; 925724ba675SRob Herring reg-shift = <2>; 926724ba675SRob Herring reg-io-width = <4>; 927724ba675SRob Herring clocks = <&l4_sp_clk>; 928724ba675SRob Herring dmas = <&pdma 30>, 929724ba675SRob Herring <&pdma 31>; 930724ba675SRob Herring dma-names = "tx", "rx"; 931724ba675SRob Herring resets = <&rst UART1_RESET>; 932724ba675SRob Herring }; 933724ba675SRob Herring 934724ba675SRob Herring usbphy0: usbphy { 935724ba675SRob Herring #phy-cells = <0>; 936724ba675SRob Herring compatible = "usb-nop-xceiv"; 937724ba675SRob Herring status = "okay"; 938724ba675SRob Herring }; 939724ba675SRob Herring 940724ba675SRob Herring usb0: usb@ffb00000 { 941724ba675SRob Herring compatible = "snps,dwc2"; 942724ba675SRob Herring reg = <0xffb00000 0xffff>; 943724ba675SRob Herring interrupts = <0 125 4>; 944724ba675SRob Herring clocks = <&usb_mp_clk>; 945724ba675SRob Herring clock-names = "otg"; 946724ba675SRob Herring resets = <&rst USB0_RESET>; 947724ba675SRob Herring reset-names = "dwc2"; 948724ba675SRob Herring phys = <&usbphy0>; 949724ba675SRob Herring phy-names = "usb2-phy"; 950724ba675SRob Herring status = "disabled"; 951724ba675SRob Herring }; 952724ba675SRob Herring 953724ba675SRob Herring usb1: usb@ffb40000 { 954724ba675SRob Herring compatible = "snps,dwc2"; 955724ba675SRob Herring reg = <0xffb40000 0xffff>; 956724ba675SRob Herring interrupts = <0 128 4>; 957724ba675SRob Herring clocks = <&usb_mp_clk>; 958724ba675SRob Herring clock-names = "otg"; 959724ba675SRob Herring resets = <&rst USB1_RESET>; 960724ba675SRob Herring reset-names = "dwc2"; 961724ba675SRob Herring phys = <&usbphy0>; 962724ba675SRob Herring phy-names = "usb2-phy"; 963724ba675SRob Herring status = "disabled"; 964724ba675SRob Herring }; 965724ba675SRob Herring 966724ba675SRob Herring watchdog0: watchdog@ffd02000 { 967724ba675SRob Herring compatible = "snps,dw-wdt"; 968724ba675SRob Herring reg = <0xffd02000 0x1000>; 969724ba675SRob Herring interrupts = <0 171 4>; 970724ba675SRob Herring clocks = <&osc1>; 971724ba675SRob Herring resets = <&rst L4WD0_RESET>; 972724ba675SRob Herring status = "disabled"; 973724ba675SRob Herring }; 974724ba675SRob Herring 975724ba675SRob Herring watchdog1: watchdog@ffd03000 { 976724ba675SRob Herring compatible = "snps,dw-wdt"; 977724ba675SRob Herring reg = <0xffd03000 0x1000>; 978724ba675SRob Herring interrupts = <0 172 4>; 979724ba675SRob Herring clocks = <&osc1>; 980724ba675SRob Herring resets = <&rst L4WD1_RESET>; 981724ba675SRob Herring status = "disabled"; 982724ba675SRob Herring }; 983724ba675SRob Herring }; 984724ba675SRob Herring}; 985