Lines Matching +full:mac +full:- +full:divider
1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/ingenic,x1000-cgu.h>
70 usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); in x1000_otg_phy_recalc_rate()
119 return -EINVAL; in x1000_otg_phy_set_rate()
122 spin_lock_irqsave(&cgu->lock, flags); in x1000_otg_phy_set_rate()
124 usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); in x1000_otg_phy_set_rate()
127 writel(usbpcr1, cgu->base + CGU_REG_USBPCR1); in x1000_otg_phy_set_rate()
129 spin_unlock_irqrestore(&cgu->lock, flags); in x1000_otg_phy_set_rate()
135 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in x1000_usb_phy_enable()
136 void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; in x1000_usb_phy_enable()
145 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in x1000_usb_phy_disable()
146 void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; in x1000_usb_phy_disable()
154 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in x1000_usb_phy_is_enabled()
155 void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; in x1000_usb_phy_is_enabled()
177 const unsigned long m_max = GENMASK(pll_info->m_bits - 1, 0); in x1000_i2spll_calc_m_n_od()
178 const unsigned long n_max = GENMASK(pll_info->n_bits - 1, 0); in x1000_i2spll_calc_m_n_od()
199 * the divider to function correctly. in x1000_i2spll_set_rate_hook()
201 writel(0, cgu->base + CGU_REG_I2SCDR1); in x1000_i2spll_set_rate_hook()
205 0x0, 0x1, -1, 0x2, -1, -1, -1, 0x3,
263 /* Custom (SoC-specific) OTG PHY */
267 .parents = { -1, -1, X1000_CLK_EXCLK, -1 },
275 .parents = { -1, X1000_CLK_EXCLK, X1000_CLK_APLL, -1 },
281 .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
293 .div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1 },
305 .div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1 },
310 .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
312 .div = { CGU_REG_CPCCR, 8, 1, 4, 21, -1, -1 },
317 .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
324 .div = { CGU_REG_CPCCR, 12, 1, 4, 20, -1, -1 },
330 .div = { CGU_REG_CPCCR, 16, 1, 4, 20, -1, -1 },
341 .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
348 "mac", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
378 .parents = { X1000_CLK_EXCLK, -1, -1, X1000_CLK_I2SPLL },
380 * NOTE: the mux is at bit 30; bit 29 enables the M/N divider.
381 * Therefore, the divider is disabled when EXCLK is selected.
409 .parents = { X1000_CLK_MSCMUX, -1, -1, -1 },
416 .parents = { X1000_CLK_EXCLK, -1, X1000_CLK_APLL, X1000_CLK_MPLL },
454 /* Gate-only clocks */
562 * in the case where the device node is compatible with "simple-mfd".
564 CLK_OF_DECLARE_DRIVER(x1000_cgu, "ingenic,x1000-cgu", x1000_cgu_init);